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e525d34b NI |
1 | /* |
2 | * include/configs/salvator-x.h | |
3 | * This file is Salvator-X board configuration. | |
4 | * | |
5 | * Copyright (C) 2015 Renesas Electronics Corporation | |
6 | * | |
7 | * SPDX-License-Identifier: GPL-2.0+ | |
8 | */ | |
9 | ||
10 | #ifndef __SALVATOR_X_H | |
11 | #define __SALVATOR_X_H | |
12 | ||
13 | #undef DEBUG | |
14 | ||
15 | #define CONFIG_RCAR_BOARD_STRING "Salvator-X" | |
16 | ||
17 | #include "rcar-gen3-common.h" | |
18 | ||
19 | /* SCIF */ | |
e525d34b NI |
20 | #define CONFIG_CONS_SCIF2 |
21 | #define CONFIG_CONS_INDEX 2 | |
8474681c | 22 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ |
e525d34b NI |
23 | |
24 | /* [A] Hyper Flash */ | |
25 | /* use to RPC(SPI Multi I/O Bus Controller) */ | |
e525d34b | 26 | |
90e53f8b MV |
27 | /* Ethernet RAVB */ |
28 | #define CONFIG_NET_MULTI | |
90e53f8b MV |
29 | #define CONFIG_BITBANGMII |
30 | #define CONFIG_BITBANGMII_MULTI | |
31 | ||
e525d34b NI |
32 | /* Board Clock */ |
33 | /* XTAL_CLK : 33.33MHz */ | |
34 | #define RCAR_XTAL_CLK 33333333u | |
35 | #define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK | |
36 | /* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */ | |
8474681c | 37 | /* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */ |
e525d34b NI |
38 | #define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) |
39 | #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2) | |
40 | #define CONFIG_S3D2_CLK_FREQ (266666666u/2) | |
8474681c | 41 | #define CONFIG_S3D4_CLK_FREQ (266666666u/4) |
e525d34b NI |
42 | |
43 | /* Generic Timer Definitions (use in assembler source) */ | |
44 | #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ | |
45 | ||
46 | /* Generic Interrupt Controller Definitions */ | |
47 | #define CONFIG_GICV2 | |
48 | #define GICD_BASE 0xF1010000 | |
49 | #define GICC_BASE 0xF1020000 | |
50 | ||
fe2e8ff9 MV |
51 | /* i2c */ |
52 | #define CONFIG_SYS_I2C | |
53 | #define CONFIG_SYS_I2C_SH | |
54 | #define CONFIG_SYS_I2C_SLAVE 0x60 | |
55 | #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1 | |
56 | #define CONFIG_SYS_I2C_SH_SPEED0 400000 | |
57 | #define CONFIG_SH_I2C_DATA_HIGH 4 | |
58 | #define CONFIG_SH_I2C_DATA_LOW 5 | |
59 | #define CONFIG_SH_I2C_CLOCK 10000000 | |
60 | ||
61 | #define CONFIG_SYS_I2C_POWERIC_ADDR 0x30 | |
62 | ||
d1018f5f MV |
63 | /* USB */ |
64 | #ifdef CONFIG_R8A7795 | |
65 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 | |
66 | #else | |
67 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 | |
68 | #endif | |
69 | ||
50fb0c45 MV |
70 | /* SDHI */ |
71 | #define CONFIG_SH_SDHI_FREQ 200000000 | |
72 | ||
73 | /* Environment in eMMC, at the end of 2nd "boot sector" */ | |
50fb0c45 MV |
74 | #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) |
75 | #define CONFIG_SYS_MMC_ENV_DEV 1 | |
76 | #define CONFIG_SYS_MMC_ENV_PART 2 | |
77 | ||
e525d34b NI |
78 | /* Module stop status bits */ |
79 | /* MFIS, SCIF1 */ | |
80 | #define CONFIG_SMSTP2_ENA 0x00002040 | |
4c443bdb MV |
81 | /* SCIF2 */ |
82 | #define CONFIG_SMSTP3_ENA 0x00000400 | |
e525d34b NI |
83 | /* INTC-AP, IRQC */ |
84 | #define CONFIG_SMSTP4_ENA 0x00000180 | |
85 | ||
86 | #endif /* __SALVATOR_X_H */ |