[J-u-boot.git] / include / configs / lubbock.h

/*
 * (C) Copyright 2002
 * Kyle Harris, Nexus Technologies, Inc. [email protected]
 *
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <[email protected]>
 *
 * Configuation settings for the LUBBOCK board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_PXA250		1	/* This is an PXA250 CPU    */
#define CONFIG_LUBBOCK		1	/* on an LUBBOCK Board	    */
#define CONFIG_LCD		1
#ifdef CONFIG_LCD
#define CONFIG_SHARP_LM8V31
#endif
#define CONFIG_MMC		1
#define BOARD_LATE_INIT		1

#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */

/*
 * Size of malloc() pool
 */
#define CFG_MALLOC_LEN	    (CFG_ENV_SIZE + 128*1024)
#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */

/*
 * Hardware drivers
 */
#define CONFIG_DRIVER_LAN91C96
#define CONFIG_LAN91C96_BASE 0x0C000000

/*
 * select serial console configuration
 */
#define CONFIG_FFUART	       1       /* we use FFUART on LUBBOCK */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_BAUDRATE		115200

#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#define CONFIG_BOOTDELAY	3
#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
#define CONFIG_NETMASK		255.255.0.0
#define CONFIG_IPADDR		192.168.0.21
#define CONFIG_SERVERIP		192.168.0.250
#define CONFIG_BOOTCOMMAND	"bootm 40000"
#define CONFIG_BOOTARGS		"root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
#define CONFIG_CMDLINE_TAG

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
#endif

/*
 * Miscellaneous configurable options
 */
#define CFG_HUSH_PARSER		1
#define CFG_PROMPT_HUSH_PS2	"> "

#define CFG_LONGHELP				/* undef to save memory		*/
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT		"$ "		/* Monitor Command Prompt */
#else
#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
#endif
#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS		16		/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
#define CFG_DEVICE_NULLDEV	1

#define CFG_MEMTEST_START	0xa0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/

#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */

#define CFG_LOAD_ADDR		0xa8000000	/* default load address */

#define CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
#define CFG_CPUSPEED		0x161		/* set core clock to 400/200/100 MHz */

						/* valid baudrates */
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define CFG_MMC_BASE		0xF0000000

/*
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
#endif

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	4	   /* we have 2 banks of DRAM */
#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2 */
#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB */
#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3 */
#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB */
#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4 */
#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB */

#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_2		0x04000000 /* Flash Bank #2 */
#define PHYS_FLASH_SIZE		0x02000000 /* 32 MB */
#define PHYS_FLASH_BANK_SIZE	0x02000000 /* 32 MB Banks */
#define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */

#define CFG_DRAM_BASE		0xa0000000
#define CFG_DRAM_SIZE		0x04000000

#define CFG_FLASH_BASE		PHYS_FLASH_1

#define FPGA_REGS_BASE_PHYSICAL 0x08000000

/*
 * GPIO settings
 */
#define CFG_GPSR0_VAL		0x00008000
#define CFG_GPSR1_VAL		0x00FC0382
#define CFG_GPSR2_VAL		0x0001FFFF
#define CFG_GPCR0_VAL		0x00000000
#define CFG_GPCR1_VAL		0x00000000
#define CFG_GPCR2_VAL		0x00000000
#define CFG_GPDR0_VAL		0x0060A800
#define CFG_GPDR1_VAL		0x00FF0382
#define CFG_GPDR2_VAL		0x0001C000
#define CFG_GAFR0_L_VAL		0x98400000
#define CFG_GAFR0_U_VAL		0x00002950
#define CFG_GAFR1_L_VAL		0x000A9558
#define CFG_GAFR1_U_VAL		0x0005AAAA
#define CFG_GAFR2_L_VAL		0xA0000000
#define CFG_GAFR2_U_VAL		0x00000002

#define CFG_PSSR_VAL		0x20

/*
 * Memory settings
 */
#define CFG_MSC0_VAL		0x23F223F2
#define CFG_MSC1_VAL		0x3FF1A441
#define CFG_MSC2_VAL		0x7FF97FF1
#define CFG_MDCNFG_VAL		0x00001AC9
#define CFG_MDREFR_VAL		0x00018018
#define CFG_MDMRS_VAL		0x00000000

/*
 * PCMCIA and CF Interfaces
 */
#define CFG_MECR_VAL		0x00000000
#define CFG_MCMEM0_VAL		0x00010504
#define CFG_MCMEM1_VAL		0x00010504
#define CFG_MCATT0_VAL		0x00010504
#define CFG_MCATT1_VAL		0x00010504
#define CFG_MCIO0_VAL		0x00004715
#define CFG_MCIO1_VAL		0x00004715

#define _LED			0x08000010
#define LED_BLANK		0x08000040

/*
 * FLASH and environment organization
 */
#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	128  /* max number of sectors on one chip    */

/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT	(25*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT	(25*CFG_HZ) /* Timeout for Flash Write */

/* FIXME */
#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x1C000)	/* Addr of Environment Sector	*/
#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/


/*
 * FPGA Offsets
 */
#define WHOAMI_OFFSET		0x00
#define HEXLED_OFFSET		0x10
#define BLANKLED_OFFSET		0x40
#define DISCRETELED_OFFSET	0x40
#define CNFG_SWITCHES_OFFSET	0x50
#define USER_SWITCHES_OFFSET	0x60
#define MISC_WR_OFFSET		0x80
#define MISC_RD_OFFSET		0x90
#define INT_MASK_OFFSET		0xC0
#define INT_CLEAR_OFFSET	0xD0
#define GP_OFFSET		0x100

#endif	/* __CONFIG_H */
Commit	Line	Data
da27dcf0 WD	1	/*
	2	* (C) Copyright 2002
	3	* Kyle Harris, Nexus Technologies, Inc. [email protected]
	4	*
	5	* (C) Copyright 2002
	6	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	7	* Marius Groeger <[email protected]>
	8	*
	9	* Configuation settings for the LUBBOCK board.
	10	*
	11	* See file CREDITS for list of people who contributed to this
	12	* project.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
71f95118	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
da27dcf0 WD	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*/
	29
	30	#ifndef __CONFIG_H
	31	#define __CONFIG_H
	32
da27dcf0 WD	33	/*
	34	* High Level Configuration Options
	35	* (easy to change)
	36	*/
71f95118 WD	37	#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
	38	#define CONFIG_LUBBOCK 1 /* on an LUBBOCK Board */
	39	#define CONFIG_LCD 1
63cfcbb4 WD	40	#ifdef CONFIG_LCD
	41	#define CONFIG_SHARP_LM8V31
	42	#endif
71f95118	43	#define CONFIG_MMC 1
c837dcb1	44	#define BOARD_LATE_INIT 1
da27dcf0	45
71f95118	46	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
da27dcf0 WD	47
	48	/*
	49	* Size of malloc() pool
	50	*/
71f95118	51	#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
a8c7c708	52	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
da27dcf0 WD	53
	54	/*
	55	* Hardware drivers
	56	*/
45219c46 WD	57	#define CONFIG_DRIVER_LAN91C96
45219c46 WD	58	#define CONFIG_LAN91C96_BASE 0x0C000000
da27dcf0 WD	59
	60	/*
	61	* select serial console configuration
	62	*/
71f95118	63	#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
da27dcf0 WD	64
	65	/* allow to overwrite serial and ethaddr */
	66	#define CONFIG_ENV_OVERWRITE
	67
71f95118	68	#define CONFIG_BAUDRATE 115200
da27dcf0	69
71f95118	70	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| CFG_CMD_MMC \| CFG_CMD_FAT)
da27dcf0 WD	71
	72	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	73	#include <cmd_confdefs.h>
	74
71f95118 WD	75	#define CONFIG_BOOTDELAY 3
	76	#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
	77	#define CONFIG_NETMASK 255.255.0.0
	78	#define CONFIG_IPADDR 192.168.0.21
	79	#define CONFIG_SERVERIP 192.168.0.250
	80	#define CONFIG_BOOTCOMMAND "bootm 40000"
	81	#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
	82	#define CONFIG_CMDLINE_TAG
da27dcf0 WD	83
da27dcf0 WD	84	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
71f95118 WD	85	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
71f95118 WD	86	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
da27dcf0 WD	87	#endif
	88
	89	/*
	90	* Miscellaneous configurable options
	91	*/
71f95118 WD	92	#define CFG_HUSH_PARSER 1
	93	#define CFG_PROMPT_HUSH_PS2 "> "
	94
	95	#define CFG_LONGHELP /* undef to save memory */
	96	#ifdef CFG_HUSH_PARSER
	97	#define CFG_PROMPT "$ " /* Monitor Command Prompt */
	98	#else
	99	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	100	#endif
	101	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
da27dcf0	102	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
71f95118 WD	103	#define CFG_MAXARGS 16 /* max number of command args */
	104	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	105	#define CFG_DEVICE_NULLDEV 1
	106
	107	#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
	108	#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
da27dcf0	109
71f95118	110	#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
da27dcf0	111
71f95118	112	#define CFG_LOAD_ADDR 0xa8000000 /* default load address */
da27dcf0	113
71f95118 WD	114	#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
71f95118 WD	115	#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
da27dcf0	116
71f95118 WD	117	/* valid baudrates */
71f95118 WD	118	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
da27dcf0	119
71f95118	120	#define CFG_MMC_BASE 0xF0000000
da27dcf0 WD	121
	122	/*
	123	* Stack sizes
	124	*
	125	* The stack sizes are set up in start.S using the settings below
	126	*/
71f95118	127	#define CONFIG_STACKSIZE (1281024) / regular stack */
da27dcf0	128	#ifdef CONFIG_USE_IRQ
71f95118 WD	129	#define CONFIG_STACKSIZE_IRQ (41024) / IRQ stack */
71f95118 WD	130	#define CONFIG_STACKSIZE_FIQ (41024) / FIQ stack */
da27dcf0 WD	131	#endif
	132
	133	/*
	134	* Physical Memory Map
	135	*/
71f95118 WD	136	#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
	137	#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
	138	#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
	139	#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
	140	#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
	141	#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
	142	#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
	143	#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
	144	#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
	145
	146	#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
	147	#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
	148	#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
	149	#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
	150	#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
	151
	152	#define CFG_DRAM_BASE 0xa0000000
	153	#define CFG_DRAM_SIZE 0x04000000
	154
	155	#define CFG_FLASH_BASE PHYS_FLASH_1
da27dcf0 WD	156
	157	#define FPGA_REGS_BASE_PHYSICAL 0x08000000
	158
	159	/*
	160	* GPIO settings
	161	*/
71f95118 WD	162	#define CFG_GPSR0_VAL 0x00008000
	163	#define CFG_GPSR1_VAL 0x00FC0382
	164	#define CFG_GPSR2_VAL 0x0001FFFF
	165	#define CFG_GPCR0_VAL 0x00000000
	166	#define CFG_GPCR1_VAL 0x00000000
	167	#define CFG_GPCR2_VAL 0x00000000
	168	#define CFG_GPDR0_VAL 0x0060A800
	169	#define CFG_GPDR1_VAL 0x00FF0382
	170	#define CFG_GPDR2_VAL 0x0001C000
	171	#define CFG_GAFR0_L_VAL 0x98400000
	172	#define CFG_GAFR0_U_VAL 0x00002950
	173	#define CFG_GAFR1_L_VAL 0x000A9558
	174	#define CFG_GAFR1_U_VAL 0x0005AAAA
	175	#define CFG_GAFR2_L_VAL 0xA0000000
	176	#define CFG_GAFR2_U_VAL 0x00000002
	177
	178	#define CFG_PSSR_VAL 0x20
da27dcf0 WD	179
	180	/*
	181	* Memory settings
	182	*/
71f95118 WD	183	#define CFG_MSC0_VAL 0x23F223F2
	184	#define CFG_MSC1_VAL 0x3FF1A441
	185	#define CFG_MSC2_VAL 0x7FF97FF1
	186	#define CFG_MDCNFG_VAL 0x00001AC9
	187	#define CFG_MDREFR_VAL 0x00018018
	188	#define CFG_MDMRS_VAL 0x00000000
da27dcf0 WD	189
	190	/*
	191	* PCMCIA and CF Interfaces
	192	*/
71f95118 WD	193	#define CFG_MECR_VAL 0x00000000
	194	#define CFG_MCMEM0_VAL 0x00010504
	195	#define CFG_MCMEM1_VAL 0x00010504
	196	#define CFG_MCATT0_VAL 0x00010504
	197	#define CFG_MCATT1_VAL 0x00010504
	198	#define CFG_MCIO0_VAL 0x00004715
	199	#define CFG_MCIO1_VAL 0x00004715
da27dcf0	200
71f95118 WD	201	#define _LED 0x08000010
71f95118 WD	202	#define LED_BLANK 0x08000040
da27dcf0 WD	203
	204	/*
	205	* FLASH and environment organization
	206	*/
71f95118 WD	207	#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
71f95118 WD	208	#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
da27dcf0 WD	209
da27dcf0 WD	210	/* timeout values are in ticks */
71f95118 WD	211	#define CFG_FLASH_ERASE_TOUT (25CFG_HZ) / Timeout for Flash Erase */
71f95118 WD	212	#define CFG_FLASH_WRITE_TOUT (25CFG_HZ) / Timeout for Flash Write */
da27dcf0 WD	213
da27dcf0 WD	214	/* FIXME */
71f95118 WD	215	#define CFG_ENV_IS_IN_FLASH 1
	216	#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */
	217	#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
da27dcf0 WD	218
	219
	220	/*
	221	* FPGA Offsets
	222	*/
71f95118 WD	223	#define WHOAMI_OFFSET 0x00
	224	#define HEXLED_OFFSET 0x10
	225	#define BLANKLED_OFFSET 0x40
	226	#define DISCRETELED_OFFSET 0x40
	227	#define CNFG_SWITCHES_OFFSET 0x50
	228	#define USER_SWITCHES_OFFSET 0x60
	229	#define MISC_WR_OFFSET 0x80
	230	#define MISC_RD_OFFSET 0x90
	231	#define INT_MASK_OFFSET 0xC0
	232	#define INT_CLEAR_OFFSET 0xD0
	233	#define GP_OFFSET 0x100
	234
	235	#endif /* __CONFIG_H */