[J-u-boot.git] / include / configs / CRAYL1.h

/*
 * (C) Copyright 2000-2004
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 * David Updegraff, Cray, Inc.  [email protected]: our 405 is walnut-lite..
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_CRAYL1
/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405GP		1	/* This is a PPC405 CPU	*/
#define CONFIG_4xx		    1   /* ...member of PPC405 family */
#define CONFIG_SYS_CLK_FREQ 25000000
#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#define CONFIG_MII		    1	/* MII PHY management */
#define	CONFIG_PHY_ADDR		1	/* PHY address; handling of ENET */
#define CONFIG_BOARD_EARLY_INIT_F 1	/* early setup for 405gp */
#define CONFIG_MISC_INIT_R	1	/* so that a misc_init_r() is called */

/* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to
 * keep possible initrd ramdisk decompression out.  This is in k (1024 bytes)
 #define CONFIG_PRAM			16
 */
#define	CONFIG_LOADADDR		0x100000	/* where TFTP images go */
#undef CONFIG_BOOTARGS

/* Bootcmd is overridden by the bootscript in board/cray/L1
 */
#define	CFG_AUTOLOAD		"no"
#define CONFIG_BOOTCOMMAND	"dhcp"

/*
 * ..during experiments..
 #define CONFIG_SERVERIP         10.0.0.1
 #define CONFIG_ETHADDR          00:40:a6:80:14:5
 */
#define CONFIG_HARD_I2C         1		/* hardware support for i2c */
#define CONFIG_SDRAM_BANK0		1
#define CFG_I2C_SPEED		    400000	/* I2C speed and slave address	*/
#define CFG_I2C_SLAVE		    0x7F
#define CFG_I2C_EEPROM_ADDR     0x57
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_IDENT_STRING     "Cray L1"
#define CONFIG_ENV_OVERWRITE     1
#define	CFG_HZ		             1000	/* decrementer freq: 1 ms ticks	*/
#define CFG_HUSH_PARSER			1
#define CFG_PROMPT_HUSH_PS2		"> "
#define CONFIG_AUTOSCRIPT		1


#define CONFIG_COMMANDS	 (\
	CFG_CMD_BDI|\
	CFG_CMD_IMI|\
	CFG_CMD_FLASH|\
	CFG_CMD_MEMORY|\
	CFG_CMD_NET|\
	CFG_CMD_ENV|\
	CFG_CMD_CONSOLE|\
	CFG_CMD_ASKENV|\
	CFG_CMD_ECHO|\
	CFG_CMD_IMMAP|\
	CFG_CMD_REGINFO|\
	CFG_CMD_DHCP|\
	CFG_CMD_DATE|\
	CFG_CMD_RUN|\
	CFG_CMD_I2C|\
	CFG_CMD_EEPROM|\
	CFG_CMD_DIAG|\
	CFG_CMD_AUTOSCRIPT|\
	CFG_CMD_SETGETDCR)

/*
 * optional BOOTP / DHCP fields
 */
#define CONFIG_BOOTP_MASK (\
	CONFIG_BOOTP_VENDOREX|\
	CONFIG_BOOTP_SUBNETMASK|\
	CONFIG_BOOTP_GATEWAY|\
	CONFIG_BOOTP_DNS|\
	CONFIG_BOOTP_HOSTNAME|\
	CONFIG_BOOTP_BOOTFILESIZE|\
	CONFIG_BOOTP_BOOTPATH)

/*
 * how many time to fail & restart a net-TFTP before giving up & resetting
 * the board hoping that a reset of net interface might help..
 */
#define CONFIG_NET_RESET 5

/*
 * bauds.  Just to make it compile; in our case, I read the base_baud
 * from the DCR anyway, so its kinda-tied to the above ref. clock which in turn
 * drives the system clock.
 */
#define CFG_BASE_BAUD       403225
#define CFG_BAUDRATE_TABLE  \
    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*
 * Miscellaneous configurable options
 */
#define CFG_PROMPT	"=> "			/* Monitor Command Prompt	*/
#define	CFG_CBSIZE	256				/* Console I/O Buffer Size	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16				/* max number of command args	*/


#define CFG_LOAD_ADDR   	0x100000/* where to load what we get from TFTP */
#define CFG_TFTP_LOADADDR	CFG_LOAD_ADDR
#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
#define CFG_DRAM_TEST		1

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xFFC00000
#define CFG_MONITOR_BASE	TEXT_BASE


#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	 1		/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	 64		/* max number of sectors on one chip	*/
#define CFG_FLASH_ERASE_TOUT 120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT 500	/* Timeout for Flash Write (in ms)	*/

/* BEG ENVIRONNEMENT FLASH: needs to be a whole FlashSector  */
#define CFG_ENV_OFFSET		0x3c8000
#define CFG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
#define	CFG_ENV_SIZE		0x1000	 /* Total Size of Environment area	*/
#define CFG_ENV_SECT_SIZE	0x10000	 /* see README - env sector total size	*/

/* Memory tests: U-BOOT relocates itself to the top of Ram, so its at
 * 32meg-(128k+some_malloc_space+copy-of-ENV sector)..
 */
#define CFG_SDRAM_SIZE		32		/* megs of ram */
#define CFG_MEMTEST_START	0x2000  /* memtest works from the end of */
									/* the exception vector table */
									/* to the end of the DRAM  */
									/* less monitor and malloc area */
#define CFG_STACK_USAGE		0x10000 /* Reserve 64k for the stack usage */
#define CFG_MALLOC_LEN		(128 << 10)	/* 128k for malloc space */
#define CFG_MEM_END_USAGE	( CFG_MONITOR_LEN \
				+ CFG_MALLOC_LEN \
				+ CFG_ENV_SECT_SIZE \
				+ CFG_STACK_USAGE )

#define CFG_MEMTEST_END		(CFG_SDRAM_SIZE * 1024 * 1024 - CFG_MEM_END_USAGE)
/* END ENVIRONNEMENT FLASH */

/*-----------------------------------------------------------------------
 * Cache Configuration.  Only used to ..?? clear it, I guess..
 */
#define CFG_DCACHE_SIZE		16384
#define CFG_CACHELINE_SIZE	32

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/


/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in OnChipMem )
 */
#if 1
/* On Chip Memory location */
#define CFG_TEMP_STACK_OCM	1
#define CFG_OCM_DATA_ADDR	0xF0000000
#define CFG_OCM_DATA_SIZE	0x1000

#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
#define CFG_GBL_DATA_SIZE      256  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
#else
#define CFG_OCM_DATA_ADDR	0xF0000000
#define CFG_OCM_DATA_SIZE	0x1000
#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR 	/* inside of On Chip SRAM    */
#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE	/* End of On Chip SRAM	     */
#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
#endif

/*-----------------------------------------------------------------------
 * Definitions for Serial Presence Detect EEPROM address
 */
#define EEPROM_WRITE_ADDRESS 0xA0
#define EEPROM_READ_ADDRESS  0xA1

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */
Commit	Line	Data
c609719b	1	/*
c837dcb1	2	* (C) Copyright 2000-2004
c609719b WD	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	* David Updegraff, Cray, Inc. [email protected]: our 405 is walnut-lite..
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	#define CONFIG_CRAYL1
	32	/*
	33	* High Level Configuration Options
	34	* (easy to change)
	35	*/
	36
	37	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
	38	#define CONFIG_4xx 1 /* ...member of PPC405 family */
	39	#define CONFIG_SYS_CLK_FREQ 25000000
	40	#define CONFIG_BAUDRATE 9600
	41	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	42	#define CONFIG_MII 1 /* MII PHY management */
	43	#define CONFIG_PHY_ADDR 1 /* PHY address; handling of ENET */
c837dcb1	44	#define CONFIG_BOARD_EARLY_INIT_F 1 /* early setup for 405gp */
c609719b WD	45	#define CONFIG_MISC_INIT_R 1 /* so that a misc_init_r() is called */
	46
	47	/* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to
	48	* keep possible initrd ramdisk decompression out. This is in k (1024 bytes)
8bde7f77	49	#define CONFIG_PRAM 16
c609719b	50	*/
7f70e853	51	#define CONFIG_LOADADDR 0x100000 /* where TFTP images go */
c609719b WD	52	#undef CONFIG_BOOTARGS
c609719b WD	53
7f70e853 WD	54	/* Bootcmd is overridden by the bootscript in board/cray/L1
	55	*/
	56	#define CFG_AUTOLOAD "no"
	57	#define CONFIG_BOOTCOMMAND "dhcp"
c609719b	58
8bde7f77	59	/*
c609719b WD	60	* ..during experiments..
c609719b WD	61	#define CONFIG_SERVERIP 10.0.0.1
8bde7f77	62	#define CONFIG_ETHADDR 00:40:a6:80:14:5
c609719b WD	63	*/
c609719b WD	64	#define CONFIG_HARD_I2C 1 /* hardware support for i2c */
7f70e853	65	#define CONFIG_SDRAM_BANK0 1
c609719b WD	66	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	67	#define CFG_I2C_SLAVE 0x7F
	68	#define CFG_I2C_EEPROM_ADDR 0x57
	69	#define CFG_I2C_EEPROM_ADDR_LEN 1
	70	#define CONFIG_IDENT_STRING "Cray L1"
	71	#define CONFIG_ENV_OVERWRITE 1
	72	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	73	#define CFG_HUSH_PARSER 1
	74	#define CFG_PROMPT_HUSH_PS2 "> "
7f70e853	75	#define CONFIG_AUTOSCRIPT 1
c609719b WD	76
	77
	78	#define CONFIG_COMMANDS (\
	79	CFG_CMD_BDI\|\
	80	CFG_CMD_IMI\|\
	81	CFG_CMD_FLASH\|\
	82	CFG_CMD_MEMORY\|\
	83	CFG_CMD_NET\|\
	84	CFG_CMD_ENV\|\
	85	CFG_CMD_CONSOLE\|\
	86	CFG_CMD_ASKENV\|\
	87	CFG_CMD_ECHO\|\
	88	CFG_CMD_IMMAP\|\
	89	CFG_CMD_REGINFO\|\
	90	CFG_CMD_DHCP\|\
	91	CFG_CMD_DATE\|\
	92	CFG_CMD_RUN\|\
	93	CFG_CMD_I2C\|\
	94	CFG_CMD_EEPROM\|\
7f70e853 WD	95	CFG_CMD_DIAG\|\
7f70e853 WD	96	CFG_CMD_AUTOSCRIPT\|\
c609719b WD	97	CFG_CMD_SETGETDCR)
	98
	99	/*
	100	* optional BOOTP / DHCP fields
	101	*/
	102	#define CONFIG_BOOTP_MASK (\
	103	CONFIG_BOOTP_VENDOREX\|\
	104	CONFIG_BOOTP_SUBNETMASK\|\
	105	CONFIG_BOOTP_GATEWAY\|\
	106	CONFIG_BOOTP_DNS\|\
	107	CONFIG_BOOTP_HOSTNAME\|\
	108	CONFIG_BOOTP_BOOTFILESIZE\|\
	109	CONFIG_BOOTP_BOOTPATH)
	110
8bde7f77	111	/*
7f70e853 WD	112	* how many time to fail & restart a net-TFTP before giving up & resetting
	113	* the board hoping that a reset of net interface might help..
	114	*/
	115	#define CONFIG_NET_RESET 5
	116
8bde7f77	117	/*
c609719b WD	118	* bauds. Just to make it compile; in our case, I read the base_baud
	119	* from the DCR anyway, so its kinda-tied to the above ref. clock which in turn
	120	* drives the system clock.
	121	*/
	122	#define CFG_BASE_BAUD 403225
	123	#define CFG_BAUDRATE_TABLE \
	124	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
	125
	126	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	127	#include <cmd_confdefs.h>
	128
	129	/*
	130	* Miscellaneous configurable options
	131	*/
	132	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	133	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	134	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	135	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	136	#define CFG_MAXARGS 16 /* max number of command args */
	137
	138
	139	#define CFG_LOAD_ADDR 0x100000/* where to load what we get from TFTP */
	140	#define CFG_TFTP_LOADADDR CFG_LOAD_ADDR
	141	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
7f70e853	142	#define CFG_DRAM_TEST 1
c609719b WD	143
	144	/*-----------------------------------------------------------------------
	145	* Start addresses for the final memory configuration
	146	* (Set up by the startup code)
	147	* Please note that CFG_SDRAM_BASE _must_ start at 0
	148	*/
	149	#define CFG_SDRAM_BASE 0x00000000
	150	#define CFG_FLASH_BASE 0xFFC00000
	151	#define CFG_MONITOR_BASE TEXT_BASE
	152
c609719b	153
7f70e853	154	#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
c609719b WD	155
	156	/*
	157	* For booting Linux, the board info and command line data
	158	* have to be in the first 8 MB of memory, since this is
	159	* the maximum mapped by the Linux kernel during initialization.
	160	*/
	161	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	162	/*-----------------------------------------------------------------------
	163	* FLASH organization
	164	*/
	165	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	166	#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
	167	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	168	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	169
	170	/* BEG ENVIRONNEMENT FLASH: needs to be a whole FlashSector */
8bde7f77	171	#define CFG_ENV_OFFSET 0x3c8000
c609719b	172	#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
7f70e853	173	#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment area */
c609719b WD	174	#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
c609719b WD	175
7f70e853	176	/* Memory tests: U-BOOT relocates itself to the top of Ram, so its at
c609719b WD	177	* 32meg-(128k+some_malloc_space+copy-of-ENV sector)..
	178	*/
	179	#define CFG_SDRAM_SIZE 32 /* megs of ram */
	180	#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */
	181	/* the exception vector table */
	182	/* to the end of the DRAM */
	183	/* less monitor and malloc area */
	184	#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
7f70e853	185	#define CFG_MALLOC_LEN (128 << 10) /* 128k for malloc space */
c609719b	186	#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \
8bde7f77 WD	187	+ CFG_MALLOC_LEN \
	188	+ CFG_ENV_SECT_SIZE \
	189	+ CFG_STACK_USAGE )
c609719b WD	190
	191	#define CFG_MEMTEST_END (CFG_SDRAM_SIZE * 1024 * 1024 - CFG_MEM_END_USAGE)
	192	/* END ENVIRONNEMENT FLASH */
	193
	194	/*-----------------------------------------------------------------------
8bde7f77	195	* Cache Configuration. Only used to ..?? clear it, I guess..
c609719b WD	196	*/
	197	#define CFG_DCACHE_SIZE 16384
	198	#define CFG_CACHELINE_SIZE 32
	199
	200	/*
	201	* Init Memory Controller:
	202	*
	203	* BR0/1 and OR0/1 (FLASH)
	204	*/
	205
	206	#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
	207
	208
	209	/*-----------------------------------------------------------------------
	210	* Definitions for initial stack pointer and data area (in OnChipMem )
	211	*/
7f70e853 WD	212	#if 1
7f70e853 WD	213	/* On Chip Memory location */
c609719b WD	214	#define CFG_TEMP_STACK_OCM 1
	215	#define CFG_OCM_DATA_ADDR 0xF0000000
	216	#define CFG_OCM_DATA_SIZE 0x1000
7f70e853 WD	217
	218	#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
	219	#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
	220	#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
	221	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	222	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	223	#else
	224	#define CFG_OCM_DATA_ADDR 0xF0000000
	225	#define CFG_OCM_DATA_SIZE 0x1000
c609719b WD	226	#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */
c609719b WD	227	#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */
c609719b WD	228	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	229	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	230	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
7f70e853	231	#endif
c609719b WD	232
	233	/*-----------------------------------------------------------------------
	234	* Definitions for Serial Presence Detect EEPROM address
	235	*/
	236	#define EEPROM_WRITE_ADDRESS 0xA0
	237	#define EEPROM_READ_ADDRESS 0xA1
	238
	239	/*
	240	* Internal Definitions
	241	*
	242	* Boot Flags
	243	*/
	244	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	245	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	246
	247	#endif /* __CONFIG_H */