[J-u-boot.git] / include / configs / mgcoge.h

/*
 * (C) Copyright 2007
 * Heiko Schocher, DENX Software Engineering, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC8247		1
#define CONFIG_MPC8272_FAMILY   1
#define CONFIG_MGCOGE		1
#define CONFIG_HOSTNAME		mgcoge

#define	CONFIG_SYS_TEXT_BASE	0xFE000000

#define CONFIG_CPM2		1	/* Has a CPM2 */

/* include common defines/options for all Keymile boards */
#include "keymile-common.h"

/*
 * Select serial console configuration
 *
 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 */
#define	CONFIG_CONS_ON_SMC		/* Console is on SMC         */
#undef  CONFIG_CONS_ON_SCC		/* It's not on SCC           */
#undef	CONFIG_CONS_NONE		/* It's not on external UART */
#define CONFIG_CONS_INDEX	2	/* SMC2 is used for console  */
#define CONFIG_SYS_SMC_RXBUFLEN	128
#define CONFIG_SYS_MAXIDLE	10

/*
 * Select ethernet configuration
 *
 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
 * SCC, 1-3 for FCC)
 *
 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
 * must be unset.
 */
#define	CONFIG_ETHER_ON_SCC		/* Ethernet is on SCC */
#undef	CONFIG_ETHER_ON_FCC		/* Ethernet is not on FCC     */
#undef	CONFIG_ETHER_NONE		/* No external Ethernet   */
#define CONFIG_NET_MULTI	1

#define CONFIG_ETHER_INDEX	4
#define CONFIG_HAS_ETH0
#define CONFIG_SYS_SCC_TOUT_LOOP	10000000

# define CONFIG_SYS_CMXSCR_VALUE	(CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)

#ifndef CONFIG_8260_CLKIN
#define CONFIG_8260_CLKIN	66000000	/* in Hz */
#endif

#define BOOTFLASH_START	FE000000
#define CONFIG_PRAM	512	/* protected RAM [KBytes] */

#define MTDIDS_DEFAULT		"nor0=boot,nor1=app"
#define MTDPARTS_DEFAULT	\
	"mtdparts=boot:384k(u-boot),128k(env),128k(envred),3456k(free);" \
	"app:3m(esw0),10m(rootfs0),3m(esw1),10m(rootfs1),1m(var),5m(cfg)"

#ifndef CONFIG_KM_DEF_ENV		/* if not set by keymile-common.h */
#define CONFIG_KM_DEF_ENV "km-common=empty\0"
#endif
/*
 * Default environment settings
 */
#define	CONFIG_EXTRA_ENV_SETTINGS	\
	CONFIG_KM_DEF_ENV						\
	"rootpath=/opt/eldk/ppc_82xx\0"					\
	"addcon=setenv bootargs ${bootargs} "				\
		"console=ttyCPM0,${baudrate}\0"				\
	"mtdids=nor0=boot,nor1=app \0"					\
	"partition=nor1,5 \0"						\
	"new_env=prot off FE060000 FE09FFFF; era FE060000 FE09FFFF \0" 	\
	"EEprom_ivm=pca9544a:70:4 \0"					\
	"mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0"			\
	"unlock=yes\0"							\
	""

#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xFE000000
#define CONFIG_SYS_FLASH_SIZE		32
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_MAX_FLASH_BANKS	3	/* max num of flash banks	*/
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */

#define CONFIG_SYS_FLASH_BASE_1	0x50000000
#define CONFIG_SYS_FLASH_SIZE_1	32
#define CONFIG_SYS_FLASH_BASE_2	0x52000000
#define CONFIG_SYS_FLASH_SIZE_2	32

#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
					CONFIG_SYS_FLASH_BASE_1, \
					CONFIG_SYS_FLASH_BASE_2 }

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 384KB for Monitor */

#define CONFIG_ENV_IS_IN_FLASH

#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_OFFSET	CONFIG_SYS_MONITOR_LEN

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
#endif /* CONFIG_ENV_IS_IN_FLASH */
#define CONFIG_ENV_BUFFER_PRINT		1

/* enable I2C and select the hardware/software driver */
#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
#define	CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
#define CONFIG_SYS_I2C_SPEED		50000	/* I2C speed and slave address	*/
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * Software (bit-bang) I2C driver configuration
 */

#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
#define I2C_READ	((iop->pdat & 0x00010000) != 0)
#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
			else    iop->pdat &= ~0x00010000
#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
			else    iop->pdat &= ~0x00020000
#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */

/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
#define CONFIG_DTT_LM75		1	/* ON Semi's LM75		*/
#define CONFIG_DTT_SENSORS	{0}	/* Sensor addresses		*/
#define CONFIG_SYS_DTT_MAX_TEMP	70
#define CONFIG_SYS_DTT_LOW_TEMP	-30
#define CONFIG_SYS_DTT_HYSTERESIS	3
#define CONFIG_SYS_DTT_BUS_NUM		(CONFIG_SYS_MAX_I2C_BUS)

#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1

#define CONFIG_SYS_IMMR		0xF0000000

#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/* Hard reset configuration word */
#define CONFIG_SYS_HRCW_MASTER		0x0604b211

/* No slaves */
#define CONFIG_SYS_HRCW_SLAVE1		0
#define CONFIG_SYS_HRCW_SLAVE2		0
#define CONFIG_SYS_HRCW_SLAVE3		0
#define CONFIG_SYS_HRCW_SLAVE4		0
#define CONFIG_SYS_HRCW_SLAVE5		0
#define CONFIG_SYS_HRCW_SLAVE6		0
#define CONFIG_SYS_HRCW_SLAVE7		0

#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

#define CONFIG_SYS_HID0_INIT		0
#define CONFIG_SYS_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)

#define CONFIG_SYS_HID2		0

#define CONFIG_SYS_SIUMCR		0x4020c200
#define CONFIG_SYS_SYPCR		0xFFFFFFC3
#define CONFIG_SYS_BCR			0x10000000
#define CONFIG_SYS_SCCR		(SCCR_PCI_MODE | SCCR_PCI_MODCK)

/*-----------------------------------------------------------------------
 * RMR - Reset Mode Register                                     5-5
 *-----------------------------------------------------------------------
 * turn on Checkstop Reset Enable
 */
#define CONFIG_SYS_RMR         0

/*-----------------------------------------------------------------------
 * TMCNTSC - Time Counter Status and Control                     4-40
 *-----------------------------------------------------------------------
 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 * and enable Time Counter
 */
#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control                 4-42
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 * Periodic timer
 */
#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)

/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration                         13-7
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RCCR        0

/*
 * Init Memory Controller:
 *
 * Bank Bus     Machine PortSz  Device
 * ---- ---     ------- ------  ------
 *  0   60x     GPCM     8 bit  FLASH
 *  1   60x     SDRAM   32 bit  SDRAM
 *  3   60x     GPCM     8 bit  GPIO/PIGGY
 *  5   60x     GPCM    16 bit  CFG-Flash
 *
 */
/* Bank 0 - FLASH
 */
#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)	|\
			 BRx_PS_8			|\
			 BRx_MS_GPCM_P			|\
			 BRx_V)

#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)	|\
			 ORxG_CSNT			|\
			 ORxG_ACS_DIV2			|\
			 ORxG_SCY_5_CLK			|\
			 ORxG_TRLX )


/* Bank 1 - 60x bus SDRAM
 */
#define SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT	(256 << 20)	/* less than 256 MB */

#define CONFIG_SYS_MPTPR       0x1800

/*-----------------------------------------------------------------------------
 * Address for Mode Register Set (MRS) command
 *-----------------------------------------------------------------------------
 */
#define CONFIG_SYS_MRS_OFFS	0x00000110
#define CONFIG_SYS_PSRT        0x0e

#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
			 BRx_PS_64                      |\
			 BRx_MS_SDRAM_P                 |\
			 BRx_V)

#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR1

/* SDRAM initialization values
*/

#define CONFIG_SYS_OR1    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
			 ORxS_BPD_8                     |\
			 ORxS_ROWST_PBI0_A7		|\
			 ORxS_NUMR_13)

#define CONFIG_SYS_PSDMR  (PSDMR_SDAM_A14_IS_A5 |\
			 PSDMR_BSMA_A14_A16           |\
			 PSDMR_SDA10_PBI0_A9		|\
			 PSDMR_RFRC_5_CLK               |\
			 PSDMR_PRETOACT_2W              |\
			 PSDMR_ACTTORW_2W               |\
			 PSDMR_LDOTOPRE_1C              |\
			 PSDMR_WRC_1C                   |\
			 PSDMR_CL_2)

/* GPIO/PIGGY on CS3 initialization values
*/
#define CONFIG_SYS_PIGGY_BASE	0x30000000
#define CONFIG_SYS_PIGGY_SIZE	128

#define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_PIGGY_BASE & BRx_BA_MSK) |\
			 BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)

#define CONFIG_SYS_OR3_PRELIM	(MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) |\
			 ORxG_CSNT | ORxG_ACS_DIV2 |\
			 ORxG_SCY_3_CLK | ORxG_TRLX )

/* Board FPGA on CS4 initialization values
*/
#define CONFIG_SYS_FPGA_BASE	0x40000000
#define CONFIG_SYS_FPGA_SIZE	1 /*1KB*/

#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\
			BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)

#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\
			 ORxG_CSNT | ORxG_ACS_DIV2 |\
			 ORxG_SCY_3_CLK | ORxG_TRLX )

/* CFG-Flash on CS5 initialization values
*/
#define CONFIG_SYS_BR5_PRELIM	((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
			 BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)

#define CONFIG_SYS_OR5_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \
				 CONFIG_SYS_FLASH_SIZE_2) |\
				 ORxG_CSNT | ORxG_ACS_DIV2 |\
				 ORxG_SCY_5_CLK | ORxG_TRLX )

#define	CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/

/* pass open firmware flat tree */
#define CONFIG_FIT		1
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1

#define OF_TBCLK		(bd->bi_busfreq / 4)
#define OF_STDOUT_PATH		"/soc/cpm/serial@11a90"

#endif /* __CONFIG_H */
Commit	Line	Data
ac9db066 HS	1	/*
	2	* (C) Copyright 2007
	3	* Heiko Schocher, DENX Software Engineering, [email protected].
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
	27	/*
	28	* High Level Configuration Options
	29	* (easy to change)
	30	*/
	31
	32	#define CONFIG_MPC8247 1
	33	#define CONFIG_MPC8272_FAMILY 1
	34	#define CONFIG_MGCOGE 1
9e80bb21	35	#define CONFIG_HOSTNAME mgcoge
ac9db066	36
2ae18241 WD	37	#define CONFIG_SYS_TEXT_BASE 0xFE000000
2ae18241 WD	38
ac9db066 HS	39	#define CONFIG_CPM2 1 /* Has a CPM2 */
ac9db066 HS	40
1e8f4e78 HS	41	/* include common defines/options for all Keymile boards */
1e8f4e78 HS	42	#include "keymile-common.h"
e492c90c	43
ac9db066 HS	44	/*
	45	* Select serial console configuration
	46	*
	47	* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
	48	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
	49	* for SCC).
	50	*/
	51	#define CONFIG_CONS_ON_SMC /* Console is on SMC */
	52	#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
	53	#undef CONFIG_CONS_NONE /* It's not on external UART */
	54	#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
9e80bb21 HS	55	#define CONFIG_SYS_SMC_RXBUFLEN 128
9e80bb21 HS	56	#define CONFIG_SYS_MAXIDLE 10
ac9db066 HS	57
	58	/*
	59	* Select ethernet configuration
	60	*
	61	* If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
	62	* then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
	63	* SCC, 1-3 for FCC)
	64	*
	65	* If CONFIG_ETHER_NONE is defined, then either the ethernet routines
	66	* must be defined elsewhere (as for the console), or CONFIG_CMD_NET
	67	* must be unset.
	68	*/
	69	#define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */
	70	#undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */
	71	#undef CONFIG_ETHER_NONE /* No external Ethernet */
c2d9befa	72	#define CONFIG_NET_MULTI 1
ac9db066 HS	73
ac9db066 HS	74	#define CONFIG_ETHER_INDEX 4
3ca55bce	75	#define CONFIG_HAS_ETH0
6d0f6bcf	76	#define CONFIG_SYS_SCC_TOUT_LOOP 10000000
ac9db066	77
6d0f6bcf	78	# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 \| CMXSCR_TS4CS_CLK8)
ac9db066 HS	79
	80	#ifndef CONFIG_8260_CLKIN
	81	#define CONFIG_8260_CLKIN 66000000 /* in Hz */
	82	#endif
	83
9e80bb21 HS	84	#define BOOTFLASH_START FE000000
	85	#define CONFIG_PRAM 512 /* protected RAM [KBytes] */
	86
	87	#define MTDIDS_DEFAULT "nor0=boot,nor1=app"
	88	#define MTDPARTS_DEFAULT \
	89	"mtdparts=boot:384k(u-boot),128k(env),128k(envred),3456k(free);" \
	90	"app:3m(esw0),10m(rootfs0),3m(esw1),10m(rootfs1),1m(var),5m(cfg)"
	91
364123db HS	92	#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
	93	#define CONFIG_KM_DEF_ENV "km-common=empty\0"
	94	#endif
ac9db066 HS	95	/*
	96	* Default environment settings
	97	*/
364123db HS	98	#define CONFIG_EXTRA_ENV_SETTINGS \
	99	CONFIG_KM_DEF_ENV \
	100	"rootpath=/opt/eldk/ppc_82xx\0" \
	101	"addcon=setenv bootargs ${bootargs} " \
	102	"console=ttyCPM0,${baudrate}\0" \
	103	"mtdids=nor0=boot,nor1=app \0" \
364123db HS	104	"partition=nor1,5 \0" \
	105	"new_env=prot off FE060000 FE09FFFF; era FE060000 FE09FFFF \0" \
	106	"EEprom_ivm=pca9544a:70:4 \0" \
dc71b248 HS	107	"mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0" \
dc71b248 HS	108	"unlock=yes\0" \
ac9db066	109	""
ac9db066	110
6d0f6bcf JCPV	111	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	112	#define CONFIG_SYS_FLASH_BASE 0xFE000000
	113	#define CONFIG_SYS_FLASH_SIZE 32
	114	#define CONFIG_SYS_FLASH_CFI
00b1883a	115	#define CONFIG_FLASH_CFI_DRIVER
dc71b248	116	#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */
6d0f6bcf	117	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
e492c90c	118
6d0f6bcf	119	#define CONFIG_SYS_FLASH_BASE_1 0x50000000
dc71b248 HS	120	#define CONFIG_SYS_FLASH_SIZE_1 32
	121	#define CONFIG_SYS_FLASH_BASE_2 0x52000000
	122	#define CONFIG_SYS_FLASH_SIZE_2 32
e492c90c	123
dc71b248 HS	124	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
	125	CONFIG_SYS_FLASH_BASE_1, \
	126	CONFIG_SYS_FLASH_BASE_2 }
ac9db066	127
14d0a02a	128	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	129	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	130	#define CONFIG_SYS_RAMBOOT
ac9db066 HS	131	#endif
ac9db066 HS	132
364123db	133	#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384KB for Monitor */
ac9db066	134
5a1aceb0	135	#define CONFIG_ENV_IS_IN_FLASH
ac9db066	136
5a1aceb0	137	#ifdef CONFIG_ENV_IS_IN_FLASH
cabf7b9c	138	#define CONFIG_ENV_SECT_SIZE 0x20000
6d0f6bcf	139	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
360fe71e HS	140	#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
	141
	142	/* Address and size of Redundant Environment Sector */
	143	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
	144	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
5a1aceb0	145	#endif /* CONFIG_ENV_IS_IN_FLASH */
9e80bb21	146	#define CONFIG_ENV_BUFFER_PRINT 1
ac9db066	147
9661bf9d HS	148	/* enable I2C and select the hardware/software driver */
	149	#undef CONFIG_HARD_I2C /* I2C with hardware support */
	150	#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
6d0f6bcf JCPV	151	#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */
6d0f6bcf JCPV	152	#define CONFIG_SYS_I2C_SLAVE 0x7F
9661bf9d HS	153
	154	/*
	155	* Software (bit-bang) I2C driver configuration
	156	*/
	157
	158	#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
	159	#define I2C_ACTIVE (iop->pdir \|= 0x00010000)
	160	#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
	161	#define I2C_READ ((iop->pdat & 0x00010000) != 0)
	162	#define I2C_SDA(bit) if(bit) iop->pdat \|= 0x00010000; \
	163	else iop->pdat &= ~0x00010000
	164	#define I2C_SCL(bit) if(bit) iop->pdat \|= 0x00020000; \
	165	else iop->pdat &= ~0x00020000
	166	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
	167
e5e4edd9 HS	168	/* I2C SYSMON (LM75, AD7414 is almost compatible) */
	169	#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
	170	#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
6d0f6bcf JCPV	171	#define CONFIG_SYS_DTT_MAX_TEMP 70
	172	#define CONFIG_SYS_DTT_LOW_TEMP -30
	173	#define CONFIG_SYS_DTT_HYSTERESIS 3
	174	#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
e5e4edd9	175
9e80bb21 HS	176	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
9e80bb21 HS	177
6d0f6bcf	178	#define CONFIG_SYS_IMMR 0xF0000000
ac9db066	179
6d0f6bcf JCPV	180	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
	181	#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
	182	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	183	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	184	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
ac9db066 HS	185
ac9db066 HS	186	/* Hard reset configuration word */
6d0f6bcf	187	#define CONFIG_SYS_HRCW_MASTER 0x0604b211
ac9db066 HS	188
ac9db066 HS	189	/* No slaves */
6d0f6bcf JCPV	190	#define CONFIG_SYS_HRCW_SLAVE1 0
	191	#define CONFIG_SYS_HRCW_SLAVE2 0
	192	#define CONFIG_SYS_HRCW_SLAVE3 0
	193	#define CONFIG_SYS_HRCW_SLAVE4 0
	194	#define CONFIG_SYS_HRCW_SLAVE5 0
	195	#define CONFIG_SYS_HRCW_SLAVE6 0
	196	#define CONFIG_SYS_HRCW_SLAVE7 0
ac9db066	197
6d0f6bcf	198	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
ac9db066	199
6d0f6bcf	200	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
ac9db066	201	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	202	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
ac9db066 HS	203	#endif
ac9db066 HS	204
6d0f6bcf JCPV	205	#define CONFIG_SYS_HID0_INIT 0
6d0f6bcf JCPV	206	#define CONFIG_SYS_HID0_FINAL (HID0_ICE \| HID0_IFEM \| HID0_ABE)
ac9db066	207
6d0f6bcf	208	#define CONFIG_SYS_HID2 0
ac9db066	209
6d0f6bcf JCPV	210	#define CONFIG_SYS_SIUMCR 0x4020c200
	211	#define CONFIG_SYS_SYPCR 0xFFFFFFC3
	212	#define CONFIG_SYS_BCR 0x10000000
	213	#define CONFIG_SYS_SCCR (SCCR_PCI_MODE \| SCCR_PCI_MODCK)
ac9db066 HS	214
	215	/*-----------------------------------------------------------------------
	216	* RMR - Reset Mode Register 5-5
	217	*-----------------------------------------------------------------------
	218	* turn on Checkstop Reset Enable
	219	*/
6d0f6bcf	220	#define CONFIG_SYS_RMR 0
ac9db066 HS	221
	222	/*-----------------------------------------------------------------------
	223	* TMCNTSC - Time Counter Status and Control 4-40
	224	*-----------------------------------------------------------------------
	225	* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
	226	* and enable Time Counter
	227	*/
6d0f6bcf	228	#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR\|TMCNTSC_TCF\|TMCNTSC_TCE)
ac9db066 HS	229
	230	/*-----------------------------------------------------------------------
	231	* PISCR - Periodic Interrupt Status and Control 4-42
	232	*-----------------------------------------------------------------------
	233	* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
	234	* Periodic timer
	235	*/
6d0f6bcf	236	#define CONFIG_SYS_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
ac9db066 HS	237
	238	/*-----------------------------------------------------------------------
	239	* RCCR - RISC Controller Configuration 13-7
	240	*-----------------------------------------------------------------------
	241	*/
6d0f6bcf	242	#define CONFIG_SYS_RCCR 0
ac9db066 HS	243
	244	/*
	245	* Init Memory Controller:
	246	*
	247	* Bank Bus Machine PortSz Device
	248	* ---- --- ------- ------ ------
	249	* 0 60x GPCM 8 bit FLASH
	250	* 1 60x SDRAM 32 bit SDRAM
e492c90c HS	251	* 3 60x GPCM 8 bit GPIO/PIGGY
e492c90c HS	252	* 5 60x GPCM 16 bit CFG-Flash
ac9db066 HS	253	*
	254	*/
	255	/* Bank 0 - FLASH
	256	*/
6d0f6bcf	257	#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) \|\
ac9db066 HS	258	BRx_PS_8 \|\
	259	BRx_MS_GPCM_P \|\
	260	BRx_V)
	261
6d0f6bcf	262	#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \|\
ac9db066 HS	263	ORxG_CSNT \|\
	264	ORxG_ACS_DIV2 \|\
	265	ORxG_SCY_5_CLK \|\
	266	ORxG_TRLX )
	267
	268
	269	/* Bank 1 - 60x bus SDRAM
	270	*/
	271	#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
6d0f6bcf	272	#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */
ac9db066	273
6d0f6bcf	274	#define CONFIG_SYS_MPTPR 0x1800
ac9db066 HS	275
	276	/*-----------------------------------------------------------------------------
	277	* Address for Mode Register Set (MRS) command
	278	*-----------------------------------------------------------------------------
	279	*/
6d0f6bcf JCPV	280	#define CONFIG_SYS_MRS_OFFS 0x00000110
6d0f6bcf JCPV	281	#define CONFIG_SYS_PSRT 0x0e
ac9db066	282
6d0f6bcf	283	#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) \|\
ac9db066 HS	284	BRx_PS_64 \|\
	285	BRx_MS_SDRAM_P \|\
	286	BRx_V)
	287
6d0f6bcf	288	#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1
ac9db066 HS	289
	290	/* SDRAM initialization values
	291	*/
	292
6d0f6bcf	293	#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) \|\
ac9db066 HS	294	ORxS_BPD_8 \|\
	295	ORxS_ROWST_PBI0_A7 \|\
	296	ORxS_NUMR_13)
	297
6d0f6bcf	298	#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 \|\
ac9db066 HS	299	PSDMR_BSMA_A14_A16 \|\
	300	PSDMR_SDA10_PBI0_A9 \|\
	301	PSDMR_RFRC_5_CLK \|\
	302	PSDMR_PRETOACT_2W \|\
	303	PSDMR_ACTTORW_2W \|\
	304	PSDMR_LDOTOPRE_1C \|\
	305	PSDMR_WRC_1C \|\
	306	PSDMR_CL_2)
	307
e492c90c HS	308	/* GPIO/PIGGY on CS3 initialization values
e492c90c HS	309	*/
6d0f6bcf JCPV	310	#define CONFIG_SYS_PIGGY_BASE 0x30000000
6d0f6bcf JCPV	311	#define CONFIG_SYS_PIGGY_SIZE 128
e492c90c	312
6d0f6bcf	313	#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIGGY_BASE & BRx_BA_MSK) \|\
e492c90c HS	314	BRx_PS_8 \| BRx_MS_GPCM_P \| BRx_V)
e492c90c HS	315
6d0f6bcf	316	#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) \|\
e492c90c HS	317	ORxG_CSNT \| ORxG_ACS_DIV2 \|\
	318	ORxG_SCY_3_CLK \| ORxG_TRLX )
	319
9e80bb21 HS	320	/* Board FPGA on CS4 initialization values
	321	*/
	322	#define CONFIG_SYS_FPGA_BASE 0x40000000
	323	#define CONFIG_SYS_FPGA_SIZE 1 /1KB/
	324
	325	#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) \|\
	326	BRx_PS_8 \| BRx_MS_GPCM_P \| BRx_V)
	327
	328	#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) \|\
	329	ORxG_CSNT \| ORxG_ACS_DIV2 \|\
	330	ORxG_SCY_3_CLK \| ORxG_TRLX )
	331
e492c90c HS	332	/* CFG-Flash on CS5 initialization values
e492c90c HS	333	*/
6d0f6bcf	334	#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) \|\
e492c90c HS	335	BRx_PS_16 \| BRx_MS_GPCM_P \| BRx_V)
e492c90c HS	336
dc71b248 HS	337	#define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \
	338	CONFIG_SYS_FLASH_SIZE_2) \|\
	339	ORxG_CSNT \| ORxG_ACS_DIV2 \|\
	340	ORxG_SCY_5_CLK \| ORxG_TRLX )
e492c90c	341
6d0f6bcf	342	#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
ac9db066 HS	343
ac9db066 HS	344	/* pass open firmware flat tree */
e02d4a99	345	#define CONFIG_FIT 1
ac9db066 HS	346	#define CONFIG_OF_LIBFDT 1
	347	#define CONFIG_OF_BOARD_SETUP 1
	348
ac9db066 HS	349	#define OF_TBCLK (bd->bi_busfreq / 4)
	350	#define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
	351
	352	#endif /* __CONFIG_H */