[J-u-boot.git] / include / configs / ep82xxm.h

/*
 * Copyright (C) 2006 Embedded Planet, LLC.
 *
 * U-Boot configuration for Embedded Planet EP82xxM boards.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_MPC8260
#define CPU_ID_STR		"MPC8270"

#define CONFIG_EP82XXM	/* Embedded Planet EP82xxM H 1.0 board */
			/* 256MB SDRAM / 64MB FLASH */

#define	CONFIG_SYS_TEXT_BASE	0xFFF00000

#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f */

/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
#define CONFIG_ENV_OVERWRITE

/*
 * Select serial console configuration
 *
 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 */
#define	CONFIG_CONS_ON_SMC		/* Console is on SMC         */
#undef  CONFIG_CONS_ON_SCC		/* It's not on SCC           */
#undef	CONFIG_CONS_NONE		/* It's not on external UART */
#define CONFIG_CONS_INDEX	1	/* SMC1 is used for console  */

#define CONFIG_SYS_BCSR		0xFA000000

/*
 * Select ethernet configuration
 *
 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
 * SCC, 1-3 for FCC)
 *
 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
 * must be unset.
 */
#undef	CONFIG_ETHER_ON_SCC		/* Ethernet is not on SCC */
#define CONFIG_ETHER_ON_FCC		/* Ethernet is on FCC     */
#undef	CONFIG_ETHER_NONE		/* No external Ethernet   */

#define CONFIG_NET_MULTI

#define CONFIG_ETHER_ON_FCC2
#define CONFIG_ETHER_ON_FCC3

#define CONFIG_SYS_CMXFCR_MASK3	(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
#define CONFIG_SYS_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16)
#define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
#define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)

#define CONFIG_SYS_CPMFCR_RAMTYPE	0
#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)

#define CONFIG_MII			/* MII PHY management        */
#define CONFIG_BITBANGMII		/* Bit-banged MDIO interface */

/*
 * GPIO pins used for bit-banged MII communications
 */
#define MDIO_PORT		0	/* Not used - implemented in BCSR */

#define MDIO_ACTIVE		(*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB)
#define MDIO_TRISTATE		(*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04)
#define MDIO_READ		(*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1)

#define MDIO(bit)		if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \
				else	*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE

#define MDC(bit)		if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \
				else	*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD

#define MIIDELAY		udelay(1)


#ifndef CONFIG_8260_CLKIN
#define CONFIG_8260_CLKIN	66000000 /* in Hz */
#endif

#define CONFIG_BAUDRATE		115200

#define CONFIG_SYS_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>


#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DTT
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_PCI
#define CONFIG_CMD_DIAG


#define CONFIG_ETHADDR		00:10:EC:00:88:65
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR		00:10:EC:80:88:65
#define CONFIG_IPADDR		10.0.0.245
#define CONFIG_HOSTNAME		EP82xxM
#define CONFIG_SERVERIP		10.0.0.26
#define CONFIG_GATEWAYIP	10.0.0.1
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
#define CONFIG_ENV_IN_OWN_SECT	1
#define CONFIG_AUTO_COMPLETE	1
#define	CONFIG_EXTRA_ENV_SETTINGS	"ethprime=FCC3"

#if defined(CONFIG_CMD_KGDB)
#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
#define CONFIG_KGDB_INDEX	1	/* which serial channel for kgdb */
#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
#endif

#define CONFIG_BZIP2	/* include support for bzip2 compressed images */
#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
#define CONFIG_SYS_PROMPT		"ep82xxm=> "	/* Monitor Command Prompt   */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size  */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size  */

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*-----------------------------------------------------------------------
 * Environment
 *----------------------------------------------------------------------*/
/*
 * Define here the location of the environment variables (FLASH or EEPROM).
 * Note: DENX encourages to use redundant environment in FLASH.
 */
#if 1
#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
#else
#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars	*/
#endif

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH_BASE		0xFC000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector in flinfo */

#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#endif /* CONFIG_ENV_IS_IN_FLASH */

/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
/* EEPROM Configuration */
#define CONFIG_SYS_EEPROM_SIZE	0x1000
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x54
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10

#ifdef CONFIG_ENV_IS_IN_EEPROM
#define CONFIG_ENV_SIZE		0x200	    /* Size of Environment vars */
#define CONFIG_ENV_OFFSET		0x0
#endif /* CONFIG_ENV_IS_IN_EEPROM */

/* RTC Configuration */
#define CONFIG_RTC_M41T11	1	/* uses a M41T81 */
#define CONFIG_SYS_I2C_RTC_ADDR	0x68
#define CONFIG_M41T11_BASE_YEAR	1900

/* I2C SYSMON (LM75) */
#define CONFIG_DTT_LM75		1
#define CONFIG_DTT_SENSORS	{0}
#define CONFIG_SYS_DTT_MAX_TEMP	70
#define CONFIG_SYS_DTT_LOW_TEMP	-30
#define	CONFIG_SYS_DTT_HYSTERESIS	3

/*-----------------------------------------------------------------------
 * NVRAM Configuration
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_NVRAM_BASE_ADDR	0xFA080000
#define CONFIG_SYS_NVRAM_SIZE		(128*1024)-16


/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
/* General PCI */
#define CONFIG_PCI			/* include pci support	        */
#define CONFIG_PCI_PNP			/* do pci plug-and-play   */
#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
#define CONFIG_PCI_BOOTDELAY	0

/* PCI Memory map (if different from default map */
#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE		/* Local base */
#define CONFIG_SYS_PCI_SLV_MEM_BUS		0x00000000	/* PCI base */
#define CONFIG_SYS_PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
				 PICMR_PREFETCH_EN)

/*
 * These are the windows that allow the CPU to access PCI address space.
 * All three PCI master windows, which allow the CPU to access PCI
 * prefetch, non prefetch, and IO space (see below), must all fit within
 * these windows.
 */

/*
 * Master window that allows the CPU to access PCI Memory (prefetch).
 * This window will be setup with the second set of Outbound ATU registers
 * in the bridge.
 */

#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL	0x80000000          /* Local base */
#define CONFIG_SYS_PCI_MSTR_MEM_BUS	0x80000000          /* PCI base   */
#define	CONFIG_SYS_CPU_PCI_MEM_START	PCI_MSTR_MEM_LOCAL
#define CONFIG_SYS_PCI_MSTR_MEM_SIZE	0x20000000          /* 512MB */
#define CONFIG_SYS_POCMR0_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)

/*
 * Master window that allows the CPU to access PCI Memory (non-prefetch).
 * This window will be setup with the second set of Outbound ATU registers
 * in the bridge.
 */

#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL    0xA0000000          /* Local base */
#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS      0xA0000000          /* PCI base   */
#define CONFIG_SYS_CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
#define CONFIG_SYS_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)

/*
 * Master window that allows the CPU to access PCI IO space.
 * This window will be setup with the first set of Outbound ATU registers
 * in the bridge.
 */

#define CONFIG_SYS_PCI_MSTR_IO_LOCAL       0xF6000000          /* Local base */
#define CONFIG_SYS_PCI_MSTR_IO_BUS         0x00000000          /* PCI base   */
#define CONFIG_SYS_CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
#define CONFIG_SYS_PCI_MSTR_IO_SIZE        0x02000000          /* 64MB */
#define CONFIG_SYS_POCMR2_MASK_ATTRIB      (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)


/* PCIBR0 - for PCI IO*/
#define CONFIG_SYS_PCI_MSTR0_LOCAL		CONFIG_SYS_PCI_MSTR_IO_LOCAL		/* Local base */
#define CONFIG_SYS_PCIMSK0_MASK		~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U)	/* Size of window */
/* PCIBR1 - prefetch and non-prefetch regions joined together */
#define CONFIG_SYS_PCI_MSTR1_LOCAL		CONFIG_SYS_PCI_MSTR_MEM_LOCAL
#define CONFIG_SYS_PCIMSK1_MASK		~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U)


#define	CONFIG_SYS_DIRECT_FLASH_TFTP

#if defined(CONFIG_CMD_JFFS2)
#define CONFIG_SYS_JFFS2_FIRST_BANK	0
#define CONFIG_SYS_JFFS2_NUM_BANKS	CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_FIRST_SECTOR  0
#define CONFIG_SYS_JFFS2_LAST_SECTOR   62
#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
#define CONFIG_SYS_JFFS_CUSTOM_PART
#endif

#if defined(CONFIG_CMD_I2C)
#define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed			*/
#define CONFIG_SYS_I2C_SLAVE		0x7F	/* I2C slave address		*/
#endif

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* Reserve 256KB for Monitor */

#define CONFIG_SYS_DEFAULT_IMMR	0x00010000
#define CONFIG_SYS_IMMR		0xF0000000

#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET


/* Hard reset configuration word */
#define CONFIG_SYS_HRCW_MASTER		0 /*0x1C800641*/  /* Not used - provided by CPLD */
/* No slaves */
#define CONFIG_SYS_HRCW_SLAVE1		0
#define CONFIG_SYS_HRCW_SLAVE2		0
#define CONFIG_SYS_HRCW_SLAVE3		0
#define CONFIG_SYS_HRCW_SLAVE4		0
#define CONFIG_SYS_HRCW_SLAVE5		0
#define CONFIG_SYS_HRCW_SLAVE6		0
#define CONFIG_SYS_HRCW_SLAVE7		0

#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

#define CONFIG_SYS_HID0_INIT		0
#define CONFIG_SYS_HID0_FINAL		0

#define CONFIG_SYS_HID2		0

#define CONFIG_SYS_SIUMCR		0x02610000
#define CONFIG_SYS_SYPCR		0xFFFF0689
#define CONFIG_SYS_BCR			0x8080E000
#define CONFIG_SYS_SCCR		0x00000001

#define CONFIG_SYS_RMR			0
#define CONFIG_SYS_TMCNTSC		0x000000C3
#define CONFIG_SYS_PISCR		0x00000083
#define CONFIG_SYS_RCCR		0

#define CONFIG_SYS_MPTPR		0x0A00
#define CONFIG_SYS_PSDMR		0xC432246E
#define CONFIG_SYS_PSRT		0x32

#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_BR		(CONFIG_SYS_SDRAM_BASE | 0x00000041)
#define CONFIG_SYS_SDRAM_OR		0xF0002900

#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | 0x00001801)
#define CONFIG_SYS_OR0_PRELIM		0xFC000882
#define CONFIG_SYS_BR4_PRELIM		(CONFIG_SYS_BCSR | 0x00001001)
#define CONFIG_SYS_OR4_PRELIM		0xFFF00050

#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100

#endif /* __CONFIG_H */
Commit	Line	Data
7ce343e4 WD	1	/*
	2	* Copyright (C) 2006 Embedded Planet, LLC.
	3	*
	4	* U-Boot configuration for Embedded Planet EP82xxM boards.
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#ifndef __CONFIG_H
	26	#define __CONFIG_H
	27
	28	#define CONFIG_MPC8260
	29	#define CPU_ID_STR "MPC8270"
	30
f836e414	31	#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board */
7ce343e4 WD	32	/* 256MB SDRAM / 64MB FLASH */
7ce343e4 WD	33
2ae18241 WD	34	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
2ae18241 WD	35
7ce343e4 WD	36	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
	37
	38	/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
	39	#define CONFIG_ENV_OVERWRITE
	40
	41	/*
	42	* Select serial console configuration
	43	*
	44	* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
	45	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
	46	* for SCC).
	47	*/
	48	#define CONFIG_CONS_ON_SMC /* Console is on SMC */
	49	#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
	50	#undef CONFIG_CONS_NONE /* It's not on external UART */
	51	#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
	52
6d0f6bcf	53	#define CONFIG_SYS_BCSR 0xFA000000
7ce343e4 WD	54
	55	/*
	56	* Select ethernet configuration
	57	*
	58	* If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
	59	* then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
	60	* SCC, 1-3 for FCC)
	61	*
	62	* If CONFIG_ETHER_NONE is defined, then either the ethernet routines
639221c7 JL	63	* must be defined elsewhere (as for the console), or CONFIG_CMD_NET
639221c7 JL	64	* must be unset.
7ce343e4 WD	65	*/
	66	#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
	67	#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
	68	#undef CONFIG_ETHER_NONE /* No external Ethernet */
	69
	70	#define CONFIG_NET_MULTI
	71
	72	#define CONFIG_ETHER_ON_FCC2
	73	#define CONFIG_ETHER_ON_FCC3
	74
6d0f6bcf JCPV	75	#define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 \| CMXFCR_RF3CS_MSK \| CMXFCR_TF3CS_MSK)
	76	#define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 \| CMXFCR_TF3CS_CLK16)
	77	#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 \| CMXFCR_RF2CS_MSK \| CMXFCR_TF2CS_MSK)
	78	#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 \| CMXFCR_TF2CS_CLK14)
7ce343e4	79
6d0f6bcf JCPV	80	#define CONFIG_SYS_CPMFCR_RAMTYPE 0
6d0f6bcf JCPV	81	#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE \| FCC_PSMR_LPB)
7ce343e4 WD	82
	83	#define CONFIG_MII /* MII PHY management */
	84	#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
	85
	86	/*
	87	* GPIO pins used for bit-banged MII communications
	88	*/
	89	#define MDIO_PORT 0 /* Not used - implemented in BCSR */
be225442	90
6d0f6bcf JCPV	91	#define MDIO_ACTIVE ((vu_char )(CONFIG_SYS_BCSR + 8) &= 0xFB)
	92	#define MDIO_TRISTATE ((vu_char )(CONFIG_SYS_BCSR + 8) \|= 0x04)
	93	#define MDIO_READ ((vu_char )(CONFIG_SYS_BCSR + 8) & 1)
7ce343e4	94
6d0f6bcf JCPV	95	#define MDIO(bit) if(bit) (vu_char )(CONFIG_SYS_BCSR + 8) \|= 0x01; \
6d0f6bcf JCPV	96	else (vu_char )(CONFIG_SYS_BCSR + 8) &= 0xFE
7ce343e4	97
6d0f6bcf JCPV	98	#define MDC(bit) if(bit) (vu_char )(CONFIG_SYS_BCSR + 8) \|= 0x02; \
6d0f6bcf JCPV	99	else (vu_char )(CONFIG_SYS_BCSR + 8) &= 0xFD
7ce343e4 WD	100
	101	#define MIIDELAY udelay(1)
	102
	103
	104	#ifndef CONFIG_8260_CLKIN
	105	#define CONFIG_8260_CLKIN 66000000 /* in Hz */
	106	#endif
	107
	108	#define CONFIG_BAUDRATE 115200
	109
6d0f6bcf	110	#define CONFIG_SYS_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */
7ce343e4	111
1bec3d30	112
80ff4f99 JL	113	/*
	114	* BOOTP options
	115	*/
	116	#define CONFIG_BOOTP_BOOTFILESIZE
	117	#define CONFIG_BOOTP_BOOTPATH
	118	#define CONFIG_BOOTP_GATEWAY
	119	#define CONFIG_BOOTP_HOSTNAME
	120
	121
1bec3d30 JL	122	/*
	123	* Command line configuration.
	124	*/
	125	#include <config_cmd_default.h>
	126
	127
	128	#define CONFIG_CMD_DHCP
	129	#define CONFIG_CMD_ECHO
	130	#define CONFIG_CMD_I2C
	131	#define CONFIG_CMD_IMMAP
	132	#define CONFIG_CMD_MII
	133	#define CONFIG_CMD_PING
	134	#define CONFIG_CMD_DATE
	135	#define CONFIG_CMD_DTT
	136	#define CONFIG_CMD_EEPROM
	137	#define CONFIG_CMD_PCI
	138	#define CONFIG_CMD_DIAG
	139
7ce343e4 WD	140
	141	#define CONFIG_ETHADDR 00:10:EC:00:88:65
	142	#define CONFIG_HAS_ETH1
	143	#define CONFIG_ETH1ADDR 00:10:EC:80:88:65
	144	#define CONFIG_IPADDR 10.0.0.245
	145	#define CONFIG_HOSTNAME EP82xxM
	146	#define CONFIG_SERVERIP 10.0.0.26
	147	#define CONFIG_GATEWAYIP 10.0.0.1
	148	#define CONFIG_NETMASK 255.255.255.0
	149	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
0e8d1586	150	#define CONFIG_ENV_IN_OWN_SECT 1
8078f1a5	151	#define CONFIG_AUTO_COMPLETE 1
48690d80	152	#define CONFIG_EXTRA_ENV_SETTINGS "ethprime=FCC3"
7ce343e4	153
1bec3d30	154	#if defined(CONFIG_CMD_KGDB)
7ce343e4 WD	155	#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
	156	#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
	157	#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
	158	#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */
	159	#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
	160	#endif
	161
	162	#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
	163	#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
	164
	165	/*
	166	* Miscellaneous configurable options
	167	*/
6d0f6bcf JCPV	168	#define CONFIG_SYS_HUSH_PARSER
	169	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	170	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	171	#define CONFIG_SYS_PROMPT "ep82xxm=> " /* Monitor Command Prompt */
1bec3d30	172	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	173	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
7ce343e4	174	#else
6d0f6bcf	175	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
7ce343e4	176	#endif
6d0f6bcf JCPV	177	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	178	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	179	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
7ce343e4	180
6d0f6bcf JCPV	181	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	182	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
7ce343e4	183
6d0f6bcf	184	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
7ce343e4	185
6d0f6bcf	186	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
7ce343e4	187
6d0f6bcf	188	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
7ce343e4 WD	189
	190	/*-----------------------------------------------------------------------
	191	* Environment
	192	----------------------------------------------------------------------/
	193	/*
	194	* Define here the location of the environment variables (FLASH or EEPROM).
	195	* Note: DENX encourages to use redundant environment in FLASH.
	196	*/
	197	#if 1
5a1aceb0	198	#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
7ce343e4	199	#else
bb1f8b4f	200	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
7ce343e4 WD	201	#endif
	202
	203	/*-----------------------------------------------------------------------
	204	* FLASH related
	205	----------------------------------------------------------------------/
6d0f6bcf JCPV	206	#define CONFIG_SYS_FLASH_BASE 0xFC000000
6d0f6bcf JCPV	207	#define CONFIG_SYS_FLASH_CFI
00b1883a	208	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	209	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
	210	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
	211	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector in flinfo */
7ce343e4	212
5a1aceb0	213	#ifdef CONFIG_ENV_IS_IN_FLASH
0e8d1586	214	#define CONFIG_ENV_SECT_SIZE 0x20000
6d0f6bcf	215	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
5a1aceb0	216	#endif /* CONFIG_ENV_IS_IN_FLASH */
7ce343e4 WD	217
	218	/*-----------------------------------------------------------------------
	219	* I2C
	220	----------------------------------------------------------------------/
	221	/* EEPROM Configuration */
6d0f6bcf JCPV	222	#define CONFIG_SYS_EEPROM_SIZE 0x1000
	223	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
	224	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	225	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	226	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
7ce343e4	227
bb1f8b4f	228	#ifdef CONFIG_ENV_IS_IN_EEPROM
0e8d1586 JCPV	229	#define CONFIG_ENV_SIZE 0x200 /* Size of Environment vars */
0e8d1586 JCPV	230	#define CONFIG_ENV_OFFSET 0x0
bb1f8b4f	231	#endif /* CONFIG_ENV_IS_IN_EEPROM */
7ce343e4 WD	232
7ce343e4 WD	233	/* RTC Configuration */
53677ef1	234	#define CONFIG_RTC_M41T11 1 /* uses a M41T81 */
6d0f6bcf	235	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
7ce343e4 WD	236	#define CONFIG_M41T11_BASE_YEAR 1900
	237
	238	/* I2C SYSMON (LM75) */
	239	#define CONFIG_DTT_LM75 1
	240	#define CONFIG_DTT_SENSORS {0}
6d0f6bcf JCPV	241	#define CONFIG_SYS_DTT_MAX_TEMP 70
	242	#define CONFIG_SYS_DTT_LOW_TEMP -30
	243	#define CONFIG_SYS_DTT_HYSTERESIS 3
7ce343e4 WD	244
	245	/*-----------------------------------------------------------------------
	246	* NVRAM Configuration
	247	*-----------------------------------------------------------------------
	248	*/
6d0f6bcf JCPV	249	#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA080000
6d0f6bcf JCPV	250	#define CONFIG_SYS_NVRAM_SIZE (128*1024)-16
7ce343e4 WD	251
	252
	253	/*-----------------------------------------------------------------------
	254	* PCI stuff
	255	*-----------------------------------------------------------------------
	256	*/
	257	/* General PCI */
	258	#define CONFIG_PCI /* include pci support */
	259	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	260	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	261	#define CONFIG_PCI_BOOTDELAY 0
	262
	263	/* PCI Memory map (if different from default map */
6d0f6bcf JCPV	264	#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
	265	#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
	266	#define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB \| PICMR_ENABLE \| \
7ce343e4 WD	267	PICMR_PREFETCH_EN)
	268
	269	/*
	270	* These are the windows that allow the CPU to access PCI address space.
	271	* All three PCI master windows, which allow the CPU to access PCI
	272	* prefetch, non prefetch, and IO space (see below), must all fit within
	273	* these windows.
	274	*/
	275
	276	/*
	277	* Master window that allows the CPU to access PCI Memory (prefetch).
	278	* This window will be setup with the second set of Outbound ATU registers
	279	* in the bridge.
	280	*/
	281
6d0f6bcf JCPV	282	#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
	283	#define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
	284	#define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
	285	#define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
	286	#define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB \| POCMR_ENABLE \| POCMR_PREFETCH_EN)
7ce343e4 WD	287
	288	/*
	289	* Master window that allows the CPU to access PCI Memory (non-prefetch).
	290	* This window will be setup with the second set of Outbound ATU registers
	291	* in the bridge.
	292	*/
	293
6d0f6bcf JCPV	294	#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
	295	#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
	296	#define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
	297	#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
	298	#define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB \| POCMR_ENABLE)
7ce343e4 WD	299
	300	/*
	301	* Master window that allows the CPU to access PCI IO space.
	302	* This window will be setup with the first set of Outbound ATU registers
	303	* in the bridge.
	304	*/
	305
6d0f6bcf JCPV	306	#define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */
	307	#define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
	308	#define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
	309	#define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */
	310	#define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB \| POCMR_ENABLE \| POCMR_PCI_IO)
7ce343e4 WD	311
	312
	313	/* PCIBR0 - for PCI IO*/
6d0f6bcf JCPV	314	#define CONFIG_SYS_PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL /* Local base */
6d0f6bcf JCPV	315	#define CONFIG_SYS_PCIMSK0_MASK ~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U) /* Size of window */
7ce343e4	316	/* PCIBR1 - prefetch and non-prefetch regions joined together */
6d0f6bcf JCPV	317	#define CONFIG_SYS_PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL
6d0f6bcf JCPV	318	#define CONFIG_SYS_PCIMSK1_MASK ~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U)
7ce343e4 WD	319
7ce343e4 WD	320
6d0f6bcf	321	#define CONFIG_SYS_DIRECT_FLASH_TFTP
7ce343e4	322
1bec3d30	323	#if defined(CONFIG_CMD_JFFS2)
6d0f6bcf JCPV	324	#define CONFIG_SYS_JFFS2_FIRST_BANK 0
	325	#define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS
	326	#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0
	327	#define CONFIG_SYS_JFFS2_LAST_SECTOR 62
	328	#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
	329	#define CONFIG_SYS_JFFS_CUSTOM_PART
80ff4f99	330	#endif
7ce343e4	331
1bec3d30	332	#if defined(CONFIG_CMD_I2C)
7ce343e4	333	#define CONFIG_HARD_I2C 1 /* To enable I2C support */
6d0f6bcf JCPV	334	#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
6d0f6bcf JCPV	335	#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
80ff4f99	336	#endif
7ce343e4	337
14d0a02a	338	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	339	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	340	#define CONFIG_SYS_RAMBOOT
7ce343e4 WD	341	#endif
7ce343e4 WD	342
6d0f6bcf	343	#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 256KB for Monitor */
7ce343e4	344
6d0f6bcf JCPV	345	#define CONFIG_SYS_DEFAULT_IMMR 0x00010000
6d0f6bcf JCPV	346	#define CONFIG_SYS_IMMR 0xF0000000
7ce343e4	347
6d0f6bcf JCPV	348	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
	349	#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
	350	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	351	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	352	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
7ce343e4 WD	353
	354
	355	/* Hard reset configuration word */
6d0f6bcf	356	#define CONFIG_SYS_HRCW_MASTER 0 /0x1C800641/ /* Not used - provided by CPLD */
7ce343e4	357	/* No slaves */
6d0f6bcf JCPV	358	#define CONFIG_SYS_HRCW_SLAVE1 0
	359	#define CONFIG_SYS_HRCW_SLAVE2 0
	360	#define CONFIG_SYS_HRCW_SLAVE3 0
	361	#define CONFIG_SYS_HRCW_SLAVE4 0
	362	#define CONFIG_SYS_HRCW_SLAVE5 0
	363	#define CONFIG_SYS_HRCW_SLAVE6 0
	364	#define CONFIG_SYS_HRCW_SLAVE7 0
7ce343e4	365
6d0f6bcf JCPV	366	#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
6d0f6bcf JCPV	367	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
7ce343e4	368
6d0f6bcf	369	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
1bec3d30	370	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	371	#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
7ce343e4 WD	372	#endif
7ce343e4 WD	373
6d0f6bcf JCPV	374	#define CONFIG_SYS_HID0_INIT 0
6d0f6bcf JCPV	375	#define CONFIG_SYS_HID0_FINAL 0
7ce343e4	376
6d0f6bcf	377	#define CONFIG_SYS_HID2 0
7ce343e4	378
6d0f6bcf JCPV	379	#define CONFIG_SYS_SIUMCR 0x02610000
	380	#define CONFIG_SYS_SYPCR 0xFFFF0689
	381	#define CONFIG_SYS_BCR 0x8080E000
	382	#define CONFIG_SYS_SCCR 0x00000001
7ce343e4	383
6d0f6bcf JCPV	384	#define CONFIG_SYS_RMR 0
	385	#define CONFIG_SYS_TMCNTSC 0x000000C3
	386	#define CONFIG_SYS_PISCR 0x00000083
	387	#define CONFIG_SYS_RCCR 0
7ce343e4	388
6d0f6bcf JCPV	389	#define CONFIG_SYS_MPTPR 0x0A00
	390	#define CONFIG_SYS_PSDMR 0xC432246E
	391	#define CONFIG_SYS_PSRT 0x32
7ce343e4	392
6d0f6bcf JCPV	393	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	394	#define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE \| 0x00000041)
	395	#define CONFIG_SYS_SDRAM_OR 0xF0002900
7ce343e4	396
6d0f6bcf JCPV	397	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \| 0x00001801)
	398	#define CONFIG_SYS_OR0_PRELIM 0xFC000882
	399	#define CONFIG_SYS_BR4_PRELIM (CONFIG_SYS_BCSR \| 0x00001001)
	400	#define CONFIG_SYS_OR4_PRELIM 0xFFF00050
7ce343e4	401
6d0f6bcf	402	#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
7ce343e4 WD	403
7ce343e4 WD	404	#endif /* __CONFIG_H */