projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| f12e568c | 1 | /* |
| 29f8f58f | 2 | * (C) Copyright 2000-2008 |
| f12e568c WD |
3 | * Wolfgang Denk, DENX Software Engineering, [email protected]. |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | /* | |
| 25 | * board/config.h - configuration options, board specific | |
| 26 | */ | |
| 27 | ||
| 28 | #ifndef __CONFIG_H | |
| 29 | #define __CONFIG_H | |
| 30 | ||
| 31 | /* | |
| 32 | * High Level Configuration Options | |
| 33 | * (easy to change) | |
| 34 | */ | |
| 35 | ||
| 36 | #define CONFIG_MPC855 1 /* This is a MPC855 CPU */ | |
| 37 | #define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ | |
| e7df029f | 38 | #define CONFIG_NSCU 1 |
| f12e568c | 39 | |
| 2ae18241 WD |
40 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
| 41 | ||
| f12e568c | 42 | #define CONFIG_8xx_CONS_SCC1 1 /* Console is on SMC1 */ |
| 3cb7a480 WD |
43 | #define CONFIG_SYS_SMC_RXBUFLEN 128 |
| 44 | #define CONFIG_SYS_MAXIDLE 10 | |
| f12e568c WD |
45 | |
| 46 | #define CONFIG_66MHz 1 /* running at 66 MHz, 1:1 clock */ | |
| 47 | ||
| 48 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ | |
| 49 | ||
| 50 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
| 51 | ||
| f12e568c WD |
52 | #define CONFIG_BOARD_TYPES 1 /* support board types */ |
| 53 | ||
| 54 | #define CONFIG_PREBOOT "echo;" \ | |
| 32bf3d14 | 55 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
| f12e568c WD |
56 | "echo" |
| 57 | ||
| 58 | #undef CONFIG_BOOTARGS | |
| 59 | ||
| 60 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 61 | "netdev=eth0\0" \ | |
| 62 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
| fe126d8b | 63 | "nfsroot=${serverip}:${rootpath}\0" \ |
| f12e568c | 64 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
| fe126d8b WD |
65 | "addip=setenv bootargs ${bootargs} " \ |
| 66 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
| 67 | ":${hostname}:${netdev}:off panic=1\0" \ | |
| f12e568c | 68 | "flash_nfs=run nfsargs addip;" \ |
| fe126d8b | 69 | "bootm ${kernel_addr}\0" \ |
| f12e568c | 70 | "flash_self=run ramargs addip;" \ |
| fe126d8b WD |
71 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
| 72 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
| f12e568c | 73 | "rootpath=/opt/eldk/ppc_8xx\0" \ |
| 29f8f58f WD |
74 | "hostname=NSCU\0" \ |
| 75 | "bootfile=${hostname}/uImage\0" \ | |
| f12e568c WD |
76 | "kernel_addr=40080000\0" \ |
| 77 | "ramdisk_addr=40180000\0" \ | |
| 29f8f58f WD |
78 | "u-boot=${hostname}/u-image.bin\0" \ |
| 79 | "load=tftp 200000 ${u-boot}\0" \ | |
| 80 | "update=prot off 40000000 +${filesize};" \ | |
| 81 | "era 40000000 +${filesize};" \ | |
| 82 | "cp.b 200000 40000000 ${filesize};" \ | |
| 83 | "sete filesize;save\0" \ | |
| f12e568c WD |
84 | "" |
| 85 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
| 86 | ||
| cfca5e60 WD |
87 | #define CONFIG_MISC_INIT_R 1 |
| 88 | ||
| f12e568c | 89 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| 6d0f6bcf | 90 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
| f12e568c WD |
91 | |
| 92 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 93 | ||
| 94 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
| 95 | ||
| 96 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
| 97 | ||
| 7be044e4 JL |
98 | /* |
| 99 | * BOOTP options | |
| 100 | */ | |
| 101 | #define CONFIG_BOOTP_SUBNETMASK | |
| 102 | #define CONFIG_BOOTP_GATEWAY | |
| 103 | #define CONFIG_BOOTP_HOSTNAME | |
| 104 | #define CONFIG_BOOTP_BOOTPATH | |
| 105 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 106 | ||
| f12e568c WD |
107 | |
| 108 | #define CONFIG_MAC_PARTITION | |
| 109 | #define CONFIG_DOS_PARTITION | |
| 110 | ||
| 111 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ | |
| 112 | ||
| bdccc4fe WD |
113 | #define CONFIG_ISP1362_USB /* ISP1362 USB OTG controller */ |
| 114 | ||
| f12e568c | 115 | |
| e18a1061 JL |
116 | /* |
| 117 | * Command line configuration. | |
| 118 | */ | |
| 119 | #include <config_cmd_default.h> | |
| 120 | ||
| 121 | #define CONFIG_CMD_ASKENV | |
| 122 | #define CONFIG_CMD_DATE | |
| 123 | #define CONFIG_CMD_DHCP | |
| 29f8f58f | 124 | #define CONFIG_CMD_ELF |
| e18a1061 JL |
125 | #define CONFIG_CMD_IDE |
| 126 | #define CONFIG_CMD_NFS | |
| 127 | #define CONFIG_CMD_SNTP | |
| 128 | ||
| f12e568c | 129 | |
| 29f8f58f WD |
130 | #define CONFIG_NETCONSOLE |
| 131 | ||
| 132 | ||
| f12e568c WD |
133 | /* |
| 134 | * Miscellaneous configurable options | |
| 135 | */ | |
| 6d0f6bcf JCPV |
136 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 137 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| f12e568c | 138 | |
| 29f8f58f WD |
139 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history |
| 140 | */ | |
| 6d0f6bcf JCPV |
141 | #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ |
| 142 | #ifdef CONFIG_SYS_HUSH_PARSER | |
| 143 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| f12e568c WD |
144 | #endif |
| 145 | ||
| e18a1061 | 146 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 147 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| f12e568c | 148 | #else |
| 6d0f6bcf | 149 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| f12e568c | 150 | #endif |
| 6d0f6bcf JCPV |
151 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 152 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 153 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| f12e568c | 154 | |
| 6d0f6bcf JCPV |
155 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
| 156 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
| f12e568c | 157 | |
| 6d0f6bcf | 158 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
| f12e568c | 159 | |
| 6d0f6bcf | 160 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
| f12e568c | 161 | |
| 6d0f6bcf | 162 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
| f12e568c WD |
163 | |
| 164 | /* | |
| 165 | * Low Level Configuration Settings | |
| 166 | * (address mappings, register initial values, etc.) | |
| 167 | * You should know what you are doing if you make changes here. | |
| 168 | */ | |
| 169 | /*----------------------------------------------------------------------- | |
| 170 | * Internal Memory Mapped Register | |
| 171 | */ | |
| 6d0f6bcf | 172 | #define CONFIG_SYS_IMMR 0xFFF00000 |
| f12e568c WD |
173 | |
| 174 | /*----------------------------------------------------------------------- | |
| 175 | * Definitions for initial stack pointer and data area (in DPRAM) | |
| 176 | */ | |
| 6d0f6bcf JCPV |
177 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
| 178 | #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ | |
| 179 | #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
| 180 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
| 181 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| f12e568c WD |
182 | |
| 183 | /*----------------------------------------------------------------------- | |
| 184 | * Start addresses for the final memory configuration | |
| 185 | * (Set up by the startup code) | |
| 6d0f6bcf | 186 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
| f12e568c | 187 | */ |
| 6d0f6bcf JCPV |
188 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 189 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
| 190 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
| 191 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
| 192 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
| f12e568c WD |
193 | |
| 194 | /* | |
| 195 | * For booting Linux, the board info and command line data | |
| 196 | * have to be in the first 8 MB of memory, since this is | |
| 197 | * the maximum mapped by the Linux kernel during initialization. | |
| 198 | */ | |
| 6d0f6bcf | 199 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| f12e568c WD |
200 | |
| 201 | /*----------------------------------------------------------------------- | |
| 202 | * FLASH organization | |
| 203 | */ | |
| f12e568c | 204 | |
| 29f8f58f | 205 | /* use CFI flash driver */ |
| 6d0f6bcf | 206 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
| 00b1883a | 207 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
| 6d0f6bcf JCPV |
208 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } |
| 209 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 210 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
| 211 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
| 212 | #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ | |
| f12e568c | 213 | |
| 5a1aceb0 | 214 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 0e8d1586 JCPV |
215 | #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
| 216 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
| f12e568c WD |
217 | |
| 218 | /* Address and size of Redundant Environment Sector */ | |
| 0e8d1586 JCPV |
219 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) |
| 220 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
| f12e568c | 221 | |
| 6d0f6bcf | 222 | #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ |
| 29f8f58f | 223 | |
| f12e568c WD |
224 | /*----------------------------------------------------------------------- |
| 225 | * Hardware Information Block | |
| 226 | */ | |
| 6d0f6bcf JCPV |
227 | #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
| 228 | #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
| 229 | #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
| f12e568c WD |
230 | |
| 231 | /*----------------------------------------------------------------------- | |
| 232 | * Cache Configuration | |
| 233 | */ | |
| 6d0f6bcf | 234 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
| e18a1061 | 235 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 236 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
| f12e568c WD |
237 | #endif |
| 238 | ||
| 239 | /*----------------------------------------------------------------------- | |
| 240 | * SYPCR - System Protection Control 11-9 | |
| 241 | * SYPCR can only be written once after reset! | |
| 242 | *----------------------------------------------------------------------- | |
| 243 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
| 244 | */ | |
| 245 | #if defined(CONFIG_WATCHDOG) | |
| 6d0f6bcf | 246 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
| f12e568c WD |
247 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
| 248 | #else | |
| 6d0f6bcf | 249 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
| f12e568c WD |
250 | #endif |
| 251 | ||
| 252 | /*----------------------------------------------------------------------- | |
| 253 | * SIUMCR - SIU Module Configuration 11-6 | |
| 254 | *----------------------------------------------------------------------- | |
| 255 | * PCMCIA config., multi-function pin tri-state | |
| 256 | */ | |
| 257 | #ifndef CONFIG_CAN_DRIVER | |
| 6d0f6bcf | 258 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
| f12e568c | 259 | #else /* we must activate GPL5 in the SIUMCR for CAN */ |
| 6d0f6bcf | 260 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
| f12e568c WD |
261 | #endif /* CONFIG_CAN_DRIVER */ |
| 262 | ||
| 263 | /*----------------------------------------------------------------------- | |
| 264 | * TBSCR - Time Base Status and Control 11-26 | |
| 265 | *----------------------------------------------------------------------- | |
| 266 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
| 267 | */ | |
| 6d0f6bcf | 268 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
| f12e568c WD |
269 | |
| 270 | /*----------------------------------------------------------------------- | |
| 271 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
| 272 | *----------------------------------------------------------------------- | |
| 273 | */ | |
| 6d0f6bcf | 274 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
| f12e568c WD |
275 | |
| 276 | /*----------------------------------------------------------------------- | |
| 277 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
| 278 | *----------------------------------------------------------------------- | |
| 279 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
| 280 | */ | |
| 6d0f6bcf | 281 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
| f12e568c WD |
282 | |
| 283 | /*----------------------------------------------------------------------- | |
| 284 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
| 285 | *----------------------------------------------------------------------- | |
| 286 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
| 287 | * interrupt status bit | |
| f12e568c | 288 | */ |
| 6d0f6bcf | 289 | #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
| f12e568c WD |
290 | |
| 291 | /*----------------------------------------------------------------------- | |
| 292 | * SCCR - System Clock and reset Control Register 15-27 | |
| 293 | *----------------------------------------------------------------------- | |
| 294 | * Set clock output, timebase and RTC source and divider, | |
| 295 | * power management and some other internal clocks | |
| 296 | */ | |
| 297 | #define SCCR_MASK SCCR_EBDF11 | |
| 6d0f6bcf | 298 | #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
| f12e568c WD |
299 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ |
| 300 | SCCR_DFALCD00) | |
| f12e568c WD |
301 | |
| 302 | /*----------------------------------------------------------------------- | |
| 303 | * PCMCIA stuff | |
| 304 | *----------------------------------------------------------------------- | |
| 305 | * | |
| 306 | */ | |
| e7df029f | 307 | /* NSCU use both slots, SLOT_A as "primary". */ |
| 308 | #define CONFIG_PCMCIA_SLOT_A 1 | |
| 309 | ||
| 6d0f6bcf JCPV |
310 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
| 311 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
| 312 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
| 313 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
| 314 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
| 315 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
| 316 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
| 317 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
| 53677ef1 WD |
318 | #define PCMCIA_MEM_WIN_NO 8 /* override default 4 in pcmcia.h */ |
| 319 | #define PCMCIA_SOCKETS_NO 2 /* we have two sockets */ | |
| 79536a6e | 320 | #undef NSCU_OE_INV /* PCMCIA_GCRX_CXOE was inverted on early boards */ |
| f12e568c WD |
321 | |
| 322 | /*----------------------------------------------------------------------- | |
| 323 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
| 324 | *----------------------------------------------------------------------- | |
| 325 | */ | |
| 326 | ||
| 327 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ | |
| 328 | ||
| 329 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
| 330 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
| 331 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
| 332 | ||
| 6d0f6bcf JCPV |
333 | #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE buses */ |
| 334 | #define CONFIG_SYS_IDE_MAXDEVICE 4 /* max. 2 drives per IDE bus */ | |
| f12e568c | 335 | |
| 6d0f6bcf JCPV |
336 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
| 337 | #define CONFIG_SYS_ATA_IDE1_OFFSET (4 * CONFIG_SYS_PCMCIA_MEM_SIZE) /* starts @ 4th window */ | |
| f12e568c | 338 | |
| 6d0f6bcf | 339 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
| f12e568c WD |
340 | |
| 341 | /* Offset for data I/O */ | |
| 6d0f6bcf | 342 | #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
| f12e568c WD |
343 | |
| 344 | /* Offset for normal register accesses */ | |
| 6d0f6bcf | 345 | #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
| f12e568c WD |
346 | |
| 347 | /* Offset for alternate registers */ | |
| 6d0f6bcf | 348 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
| f12e568c WD |
349 | |
| 350 | /*----------------------------------------------------------------------- | |
| 351 | * | |
| 352 | *----------------------------------------------------------------------- | |
| 353 | * | |
| 354 | */ | |
| 6d0f6bcf | 355 | #define CONFIG_SYS_DER 0 |
| f12e568c WD |
356 | |
| 357 | /* | |
| 358 | * Init Memory Controller: | |
| 359 | * | |
| 360 | * BR0/1 and OR0/1 (FLASH) | |
| 361 | */ | |
| 362 | ||
| 363 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
| 364 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ | |
| 365 | ||
| 366 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
| 367 | * restrict access enough to keep SRAM working (if any) | |
| 368 | * but not too much to meddle with FLASH accesses | |
| 369 | */ | |
| 6d0f6bcf JCPV |
370 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
| 371 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
| f12e568c WD |
372 | |
| 373 | /* | |
| 374 | * FLASH timing: | |
| 375 | */ | |
| 6d0f6bcf | 376 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ |
| f12e568c | 377 | OR_SCY_3_CLK | OR_EHTR | OR_BI) |
| f12e568c | 378 | |
| 6d0f6bcf JCPV |
379 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
| 380 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
| 381 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) | |
| f12e568c | 382 | |
| 6d0f6bcf JCPV |
383 | #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
| 384 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM | |
| 385 | #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) | |
| f12e568c WD |
386 | |
| 387 | /* | |
| 388 | * BR2/3 and OR2/3 (SDRAM) | |
| 389 | * | |
| 390 | */ | |
| 391 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
| 392 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ | |
| 393 | #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ | |
| 394 | ||
| 395 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
| 6d0f6bcf | 396 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
| f12e568c | 397 | |
| 6d0f6bcf JCPV |
398 | #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) |
| 399 | #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
| f12e568c WD |
400 | |
| 401 | #ifndef CONFIG_CAN_DRIVER | |
| 6d0f6bcf JCPV |
402 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM |
| 403 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
| f12e568c | 404 | #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ |
| 6d0f6bcf JCPV |
405 | #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ |
| 406 | #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ | |
| 407 | #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) | |
| 408 | #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ | |
| f12e568c WD |
409 | BR_PS_8 | BR_MS_UPMB | BR_V ) |
| 410 | #endif /* CONFIG_CAN_DRIVER */ | |
| 411 | ||
| bdccc4fe | 412 | #ifdef CONFIG_ISP1362_USB |
| 6d0f6bcf JCPV |
413 | #define CONFIG_SYS_ISP1362_BASE 0xD0000000 /* ISP1362 mapped at 0xD0000000 */ |
| 414 | #define CONFIG_SYS_ISP1362_OR_AM 0xFFFF8000 /* 32 kB address mask */ | |
| 415 | #define CONFIG_SYS_OR5_ISP1362 (CONFIG_SYS_ISP1362_OR_AM | OR_CSNT_SAM | \ | |
| bdccc4fe | 416 | OR_ACS_DIV2 | OR_BI | OR_SCY_5_CLK) |
| 6d0f6bcf | 417 | #define CONFIG_SYS_BR5_ISP1362 ((CONFIG_SYS_ISP1362_BASE & BR_BA_MSK) | \ |
| bdccc4fe WD |
418 | BR_PS_16 | BR_MS_GPCM | BR_V ) |
| 419 | #endif /* CONFIG_ISP1362_USB */ | |
| 42d1f039 | 420 | |
| f12e568c WD |
421 | /* |
| 422 | * Memory Periodic Timer Prescaler | |
| 423 | * | |
| 424 | * The Divider for PTA (refresh timer) configuration is based on an | |
| 425 | * example SDRAM configuration (64 MBit, one bank). The adjustment to | |
| 426 | * the number of chip selects (NCS) and the actually needed refresh | |
| 427 | * rate is done by setting MPTPR. | |
| 428 | * | |
| 429 | * PTA is calculated from | |
| 430 | * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) | |
| 431 | * | |
| 432 | * gclk CPU clock (not bus clock!) | |
| 433 | * Trefresh Refresh cycle * 4 (four word bursts used) | |
| 434 | * | |
| 435 | * 4096 Rows from SDRAM example configuration | |
| 436 | * 1000 factor s -> ms | |
| 437 | * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
| 438 | * 4 Number of refresh cycles per period | |
| 439 | * 64 Refresh cycle in ms per number of rows | |
| 440 | * -------------------------------------------- | |
| 441 | * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 | |
| 442 | * | |
| 443 | * 50 MHz => 50.000.000 / Divider = 98 | |
| 444 | * 66 Mhz => 66.000.000 / Divider = 129 | |
| 445 | * 80 Mhz => 80.000.000 / Divider = 156 | |
| 446 | */ | |
| cfca5e60 | 447 | |
| 6d0f6bcf JCPV |
448 | #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) |
| 449 | #define CONFIG_SYS_MAMR_PTA 98 | |
| f12e568c WD |
450 | |
| 451 | /* | |
| 452 | * For 16 MBit, refresh rates could be 31.3 us | |
| 453 | * (= 64 ms / 2K = 125 / quad bursts). | |
| 454 | * For a simpler initialization, 15.6 us is used instead. | |
| 455 | * | |
| 6d0f6bcf JCPV |
456 | * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks |
| 457 | * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank | |
| f12e568c | 458 | */ |
| 6d0f6bcf JCPV |
459 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
| 460 | #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
| f12e568c WD |
461 | |
| 462 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
| 6d0f6bcf JCPV |
463 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
| 464 | #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
| f12e568c WD |
465 | |
| 466 | /* | |
| 467 | * MAMR settings for SDRAM | |
| 468 | */ | |
| 469 | ||
| 470 | /* 8 column SDRAM */ | |
| 6d0f6bcf | 471 | #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
| f12e568c WD |
472 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ |
| 473 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
| 474 | /* 9 column SDRAM */ | |
| 6d0f6bcf | 475 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
| f12e568c WD |
476 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
| 477 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
| 478 | ||
| f12e568c WD |
479 | #undef CONFIG_SCC1_ENET |
| 480 | #define CONFIG_FEC_ENET | |
| f12e568c | 481 | |
| 7026ead0 HS |
482 | /* pass open firmware flat tree */ |
| 483 | #define CONFIG_OF_LIBFDT 1 | |
| 484 | #define CONFIG_OF_BOARD_SETUP 1 | |
| 485 | #define CONFIG_HWCONFIG 1 | |
| 486 | ||
| f12e568c | 487 | #endif /* __CONFIG_H */ |