[J-u-boot.git] / drivers / mmc / sdhci.c

/*
 * Copyright 2011, Marvell Semiconductor Inc.
 * Lei Wen <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * Back ported to the 8xx platform (from the 8260 platform) by
 * [email protected], 27-Jan-01.
 */

#include <common.h>
#include <malloc.h>
#include <mmc.h>
#include <sdhci.h>

#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
#else
void *aligned_buffer;
#endif

static void sdhci_reset(struct sdhci_host *host, u8 mask)
{
	unsigned long timeout;

	/* Wait max 100 ms */
	timeout = 100;
	sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
	while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
		if (timeout == 0) {
			printf("%s: Reset 0x%x never completed.\n",
			       __func__, (int)mask);
			return;
		}
		timeout--;
		udelay(1000);
	}
}

static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
{
	int i;
	if (cmd->resp_type & MMC_RSP_136) {
		/* CRC is stripped so we need to do some shifting. */
		for (i = 0; i < 4; i++) {
			cmd->response[i] = sdhci_readl(host,
					SDHCI_RESPONSE + (3-i)*4) << 8;
			if (i != 3)
				cmd->response[i] |= sdhci_readb(host,
						SDHCI_RESPONSE + (3-i)*4-1);
		}
	} else {
		cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
	}
}

static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
{
	int i;
	char *offs;
	for (i = 0; i < data->blocksize; i += 4) {
		offs = data->dest + i;
		if (data->flags == MMC_DATA_READ)
			*(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
		else
			sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
	}
}

static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
				unsigned int start_addr)
{
	unsigned int stat, rdy, mask, timeout, block = 0;
#ifdef CONFIG_MMC_SDMA
	unsigned char ctrl;
	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	ctrl &= ~SDHCI_CTRL_DMA_MASK;
	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
#endif

	timeout = 1000000;
	rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
	mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
	do {
		stat = sdhci_readl(host, SDHCI_INT_STATUS);
		if (stat & SDHCI_INT_ERROR) {
			printf("%s: Error detected in status(0x%X)!\n",
			       __func__, stat);
			return -1;
		}
		if (stat & rdy) {
			if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
				continue;
			sdhci_writel(host, rdy, SDHCI_INT_STATUS);
			sdhci_transfer_pio(host, data);
			data->dest += data->blocksize;
			if (++block >= data->blocks)
				break;
		}
#ifdef CONFIG_MMC_SDMA
		if (stat & SDHCI_INT_DMA_END) {
			sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
			start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
			start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
			sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
		}
#endif
		if (timeout-- > 0)
			udelay(10);
		else {
			printf("%s: Transfer data timeout\n", __func__);
			return -1;
		}
	} while (!(stat & SDHCI_INT_DATA_END));
	return 0;
}

/*
 * No command will be sent by driver if card is busy, so driver must wait
 * for card ready state.
 * Every time when card is busy after timeout then (last) timeout value will be
 * increased twice but only if it doesn't exceed global defined maximum.
 * Each function call will use last timeout value. Max timeout can be redefined
 * in board config file.
 */
#ifndef CONFIG_SDHCI_CMD_MAX_TIMEOUT
#define CONFIG_SDHCI_CMD_MAX_TIMEOUT		3200
#endif
#define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT	100
#define SDHCI_READ_STATUS_TIMEOUT		1000

static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
		       struct mmc_data *data)
{
	struct sdhci_host *host = mmc->priv;
	unsigned int stat = 0;
	int ret = 0;
	int trans_bytes = 0, is_aligned = 1;
	u32 mask, flags, mode;
	unsigned int time = 0, start_addr = 0;
	int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
	unsigned start = get_timer(0);

	/* Timeout unit - ms */
	static unsigned int cmd_timeout = CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT;

	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
	mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;

	/* We shouldn't wait for data inihibit for stop commands, even
	   though they might use busy signaling */
	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
		mask &= ~SDHCI_DATA_INHIBIT;

	while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
		if (time >= cmd_timeout) {
			printf("%s: MMC: %d busy ", __func__, mmc_dev);
			if (2 * cmd_timeout <= CONFIG_SDHCI_CMD_MAX_TIMEOUT) {
				cmd_timeout += cmd_timeout;
				printf("timeout increasing to: %u ms.\n",
				       cmd_timeout);
			} else {
				puts("timeout.\n");
				return COMM_ERR;
			}
		}
		time++;
		udelay(1000);
	}

	mask = SDHCI_INT_RESPONSE;
	if (!(cmd->resp_type & MMC_RSP_PRESENT))
		flags = SDHCI_CMD_RESP_NONE;
	else if (cmd->resp_type & MMC_RSP_136)
		flags = SDHCI_CMD_RESP_LONG;
	else if (cmd->resp_type & MMC_RSP_BUSY) {
		flags = SDHCI_CMD_RESP_SHORT_BUSY;
		mask |= SDHCI_INT_DATA_END;
	} else
		flags = SDHCI_CMD_RESP_SHORT;

	if (cmd->resp_type & MMC_RSP_CRC)
		flags |= SDHCI_CMD_CRC;
	if (cmd->resp_type & MMC_RSP_OPCODE)
		flags |= SDHCI_CMD_INDEX;
	if (data)
		flags |= SDHCI_CMD_DATA;

	/* Set Transfer mode regarding to data flag */
	if (data != 0) {
		sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
		mode = SDHCI_TRNS_BLK_CNT_EN;
		trans_bytes = data->blocks * data->blocksize;
		if (data->blocks > 1)
			mode |= SDHCI_TRNS_MULTI;

		if (data->flags == MMC_DATA_READ)
			mode |= SDHCI_TRNS_READ;

#ifdef CONFIG_MMC_SDMA
		if (data->flags == MMC_DATA_READ)
			start_addr = (unsigned long)data->dest;
		else
			start_addr = (unsigned long)data->src;
		if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
				(start_addr & 0x7) != 0x0) {
			is_aligned = 0;
			start_addr = (unsigned long)aligned_buffer;
			if (data->flags != MMC_DATA_READ)
				memcpy(aligned_buffer, data->src, trans_bytes);
		}

#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
		/*
		 * Always use this bounce-buffer when
		 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
		 */
		is_aligned = 0;
		start_addr = (unsigned long)aligned_buffer;
		if (data->flags != MMC_DATA_READ)
			memcpy(aligned_buffer, data->src, trans_bytes);
#endif

		sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
		mode |= SDHCI_TRNS_DMA;
#endif
		sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
				data->blocksize),
				SDHCI_BLOCK_SIZE);
		sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
		sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
	} else if (cmd->resp_type & MMC_RSP_BUSY) {
		sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
	}

	sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
#ifdef CONFIG_MMC_SDMA
	flush_cache(start_addr, trans_bytes);
#endif
	sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
	start = get_timer(0);
	do {
		stat = sdhci_readl(host, SDHCI_INT_STATUS);
		if (stat & SDHCI_INT_ERROR)
			break;
	} while (((stat & mask) != mask) &&
		 (get_timer(start) < SDHCI_READ_STATUS_TIMEOUT));

	if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
		if (host->quirks & SDHCI_QUIRK_BROKEN_R1B)
			return 0;
		else {
			printf("%s: Timeout for status update!\n", __func__);
			return TIMEOUT;
		}
	}

	if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
		sdhci_cmd_done(host, cmd);
		sdhci_writel(host, mask, SDHCI_INT_STATUS);
	} else
		ret = -1;

	if (!ret && data)
		ret = sdhci_transfer_data(host, data, start_addr);

	if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
		udelay(1000);

	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
	if (!ret) {
		if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
				!is_aligned && (data->flags == MMC_DATA_READ))
			memcpy(data->dest, aligned_buffer, trans_bytes);
		return 0;
	}

	sdhci_reset(host, SDHCI_RESET_CMD);
	sdhci_reset(host, SDHCI_RESET_DATA);
	if (stat & SDHCI_INT_TIMEOUT)
		return TIMEOUT;
	else
		return COMM_ERR;
}

static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
{
	struct sdhci_host *host = mmc->priv;
	unsigned int div, clk, timeout, reg;

	/* Wait max 20 ms */
	timeout = 200;
	while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
			   (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
		if (timeout == 0) {
			printf("%s: Timeout to wait cmd & data inhibit\n",
			       __func__);
			return -1;
		}

		timeout--;
		udelay(100);
	}

	reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
	reg &= ~SDHCI_CLOCK_CARD_EN;
	sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);

	if (clock == 0)
		return 0;

	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
		/* Version 3.00 divisors must be a multiple of 2. */
		if (mmc->cfg->f_max <= clock)
			div = 1;
		else {
			for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
				if ((mmc->cfg->f_max / div) <= clock)
					break;
			}
		}
	} else {
		/* Version 2.00 divisors must be a power of 2. */
		for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
			if ((mmc->cfg->f_max / div) <= clock)
				break;
		}
	}
	div >>= 1;

	if (host->set_clock)
		host->set_clock(host->index, div);

	clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
	clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
		<< SDHCI_DIVIDER_HI_SHIFT;
	clk |= SDHCI_CLOCK_INT_EN;
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);

	/* Wait max 20 ms */
	timeout = 20;
	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
		& SDHCI_CLOCK_INT_STABLE)) {
		if (timeout == 0) {
			printf("%s: Internal clock never stabilised.\n",
			       __func__);
			return -1;
		}
		timeout--;
		udelay(1000);
	}

	clk |= SDHCI_CLOCK_CARD_EN;
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	return 0;
}

static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
{
	u8 pwr = 0;

	if (power != (unsigned short)-1) {
		switch (1 << power) {
		case MMC_VDD_165_195:
			pwr = SDHCI_POWER_180;
			break;
		case MMC_VDD_29_30:
		case MMC_VDD_30_31:
			pwr = SDHCI_POWER_300;
			break;
		case MMC_VDD_32_33:
		case MMC_VDD_33_34:
			pwr = SDHCI_POWER_330;
			break;
		}
	}

	if (pwr == 0) {
		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
		return;
	}

	if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
		sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);

	pwr |= SDHCI_POWER_ON;

	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
}

static void sdhci_set_ios(struct mmc *mmc)
{
	u32 ctrl;
	struct sdhci_host *host = mmc->priv;

	if (host->set_control_reg)
		host->set_control_reg(host);

	if (mmc->clock != host->clock)
		sdhci_set_clock(mmc, mmc->clock);

	/* Set bus width */
	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	if (mmc->bus_width == 8) {
		ctrl &= ~SDHCI_CTRL_4BITBUS;
		if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
				(host->quirks & SDHCI_QUIRK_USE_WIDE8))
			ctrl |= SDHCI_CTRL_8BITBUS;
	} else {
		if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
				(host->quirks & SDHCI_QUIRK_USE_WIDE8))
			ctrl &= ~SDHCI_CTRL_8BITBUS;
		if (mmc->bus_width == 4)
			ctrl |= SDHCI_CTRL_4BITBUS;
		else
			ctrl &= ~SDHCI_CTRL_4BITBUS;
	}

	if (mmc->clock > 26000000)
		ctrl |= SDHCI_CTRL_HISPD;
	else
		ctrl &= ~SDHCI_CTRL_HISPD;

	if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
		ctrl &= ~SDHCI_CTRL_HISPD;

	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
}

static int sdhci_init(struct mmc *mmc)
{
	struct sdhci_host *host = mmc->priv;

	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
		aligned_buffer = memalign(8, 512*1024);
		if (!aligned_buffer) {
			printf("%s: Aligned buffer alloc failed!!!\n",
			       __func__);
			return -1;
		}
	}

	sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);

	if (host->quirks & SDHCI_QUIRK_NO_CD) {
#if defined(CONFIG_PIC32_SDHCI)
		/* PIC32 SDHCI CD errata:
		 * - set CD_TEST and clear CD_TEST_INS bit
		 */
		sdhci_writeb(host, SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL);
#else
		unsigned int status;

		sdhci_writeb(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST,
			SDHCI_HOST_CONTROL);

		status = sdhci_readl(host, SDHCI_PRESENT_STATE);
		while ((!(status & SDHCI_CARD_PRESENT)) ||
		    (!(status & SDHCI_CARD_STATE_STABLE)) ||
		    (!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
			status = sdhci_readl(host, SDHCI_PRESENT_STATE);
#endif
	}

	/* Enable only interrupts served by the SD controller */
	sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
		     SDHCI_INT_ENABLE);
	/* Mask all sdhci interrupt sources */
	sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);

	return 0;
}


static const struct mmc_ops sdhci_ops = {
	.send_cmd	= sdhci_send_command,
	.set_ios	= sdhci_set_ios,
	.init		= sdhci_init,
};

int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
{
	unsigned int caps;

	host->cfg.name = host->name;
	host->cfg.ops = &sdhci_ops;

	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
#ifdef CONFIG_MMC_SDMA
	if (!(caps & SDHCI_CAN_DO_SDMA)) {
		printf("%s: Your controller doesn't support SDMA!!\n",
		       __func__);
		return -1;
	}
#endif

	if (max_clk)
		host->cfg.f_max = max_clk;
	else {
		if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
			host->cfg.f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
				>> SDHCI_CLOCK_BASE_SHIFT;
		else
			host->cfg.f_max = (caps & SDHCI_CLOCK_BASE_MASK)
				>> SDHCI_CLOCK_BASE_SHIFT;
		host->cfg.f_max *= 1000000;
	}
	if (host->cfg.f_max == 0) {
		printf("%s: Hardware doesn't specify base clock frequency\n",
		       __func__);
		return -1;
	}
	if (min_clk)
		host->cfg.f_min = min_clk;
	else {
		if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
			host->cfg.f_min = host->cfg.f_max /
				SDHCI_MAX_DIV_SPEC_300;
		else
			host->cfg.f_min = host->cfg.f_max /
				SDHCI_MAX_DIV_SPEC_200;
	}

	host->cfg.voltages = 0;
	if (caps & SDHCI_CAN_VDD_330)
		host->cfg.voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
	if (caps & SDHCI_CAN_VDD_300)
		host->cfg.voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
	if (caps & SDHCI_CAN_VDD_180)
		host->cfg.voltages |= MMC_VDD_165_195;

	if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
		host->cfg.voltages |= host->voltages;

	host->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
		if (caps & SDHCI_CAN_DO_8BIT)
			host->cfg.host_caps |= MMC_MODE_8BIT;
	}

	if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
		host->cfg.host_caps &= ~(MMC_MODE_HS | MMC_MODE_HS_52MHz);

	if (host->host_caps)
		host->cfg.host_caps |= host->host_caps;

	host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;

	sdhci_reset(host, SDHCI_RESET_ALL);

	host->mmc = mmc_create(&host->cfg, host);
	if (host->mmc == NULL) {
		printf("%s: mmc create fail!\n", __func__);
		return -1;
	}

	return 0;
}
Commit	Line	Data
af62a557 LW	1	/*
	2	* Copyright 2011, Marvell Semiconductor Inc.
	3	* Lei Wen <[email protected]>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
af62a557 LW	6	*
	7	* Back ported to the 8xx platform (from the 8260 platform) by
	8	* [email protected], 27-Jan-01.
	9	*/
	10
	11	#include <common.h>
	12	#include <malloc.h>
	13	#include <mmc.h>
	14	#include <sdhci.h>
	15
492d3223 SR	16	#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
	17	void aligned_buffer = (void )CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
	18	#else
af62a557	19	void *aligned_buffer;
492d3223	20	#endif
af62a557 LW	21
	22	static void sdhci_reset(struct sdhci_host *host, u8 mask)
	23	{
	24	unsigned long timeout;
	25
	26	/* Wait max 100 ms */
	27	timeout = 100;
	28	sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
	29	while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
	30	if (timeout == 0) {
30e6d979 DR	31	printf("%s: Reset 0x%x never completed.\n",
30e6d979 DR	32	__func__, (int)mask);
af62a557 LW	33	return;
	34	}
	35	timeout--;
	36	udelay(1000);
	37	}
	38	}
	39
	40	static void sdhci_cmd_done(struct sdhci_host host, struct mmc_cmd cmd)
	41	{
	42	int i;
	43	if (cmd->resp_type & MMC_RSP_136) {
	44	/* CRC is stripped so we need to do some shifting. */
	45	for (i = 0; i < 4; i++) {
	46	cmd->response[i] = sdhci_readl(host,
	47	SDHCI_RESPONSE + (3-i)*4) << 8;
	48	if (i != 3)
	49	cmd->response[i] \|= sdhci_readb(host,
	50	SDHCI_RESPONSE + (3-i)*4-1);
	51	}
	52	} else {
	53	cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
	54	}
	55	}
	56
	57	static void sdhci_transfer_pio(struct sdhci_host host, struct mmc_data data)
	58	{
	59	int i;
	60	char *offs;
	61	for (i = 0; i < data->blocksize; i += 4) {
	62	offs = data->dest + i;
	63	if (data->flags == MMC_DATA_READ)
	64	(u32 )offs = sdhci_readl(host, SDHCI_BUFFER);
	65	else
	66	sdhci_writel(host, (u32 )offs, SDHCI_BUFFER);
	67	}
	68	}
	69
	70	static int sdhci_transfer_data(struct sdhci_host host, struct mmc_data data,
	71	unsigned int start_addr)
	72	{
a004abde	73	unsigned int stat, rdy, mask, timeout, block = 0;
804c7f42 JC	74	#ifdef CONFIG_MMC_SDMA
804c7f42 JC	75	unsigned char ctrl;
2c011847	76	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
804c7f42	77	ctrl &= ~SDHCI_CTRL_DMA_MASK;
2c011847	78	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
804c7f42	79	#endif
af62a557	80
5d48e422	81	timeout = 1000000;
af62a557 LW	82	rdy = SDHCI_INT_SPACE_AVAIL \| SDHCI_INT_DATA_AVAIL;
	83	mask = SDHCI_DATA_AVAILABLE \| SDHCI_SPACE_AVAILABLE;
	84	do {
	85	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	86	if (stat & SDHCI_INT_ERROR) {
30e6d979 DR	87	printf("%s: Error detected in status(0x%X)!\n",
30e6d979 DR	88	__func__, stat);
af62a557 LW	89	return -1;
	90	}
	91	if (stat & rdy) {
	92	if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
	93	continue;
	94	sdhci_writel(host, rdy, SDHCI_INT_STATUS);
	95	sdhci_transfer_pio(host, data);
	96	data->dest += data->blocksize;
	97	if (++block >= data->blocks)
	98	break;
	99	}
	100	#ifdef CONFIG_MMC_SDMA
	101	if (stat & SDHCI_INT_DMA_END) {
	102	sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
3e81c772	103	start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
af62a557 LW	104	start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
	105	sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
	106	}
	107	#endif
a004abde LW	108	if (timeout-- > 0)
	109	udelay(10);
	110	else {
30e6d979	111	printf("%s: Transfer data timeout\n", __func__);
a004abde LW	112	return -1;
a004abde LW	113	}
af62a557 LW	114	} while (!(stat & SDHCI_INT_DATA_END));
	115	return 0;
	116	}
	117
56b34bc6 PM	118	/*
	119	* No command will be sent by driver if card is busy, so driver must wait
	120	* for card ready state.
	121	* Every time when card is busy after timeout then (last) timeout value will be
	122	* increased twice but only if it doesn't exceed global defined maximum.
	123	* Each function call will use last timeout value. Max timeout can be redefined
	124	* in board config file.
	125	*/
	126	#ifndef CONFIG_SDHCI_CMD_MAX_TIMEOUT
	127	#define CONFIG_SDHCI_CMD_MAX_TIMEOUT 3200
	128	#endif
	129	#define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT 100
d90bb439	130	#define SDHCI_READ_STATUS_TIMEOUT 1000
56b34bc6	131
6588c78b	132	static int sdhci_send_command(struct mmc mmc, struct mmc_cmd cmd,
af62a557 LW	133	struct mmc_data *data)
af62a557 LW	134	{
93bfd616	135	struct sdhci_host *host = mmc->priv;
af62a557 LW	136	unsigned int stat = 0;
	137	int ret = 0;
	138	int trans_bytes = 0, is_aligned = 1;
	139	u32 mask, flags, mode;
56b34bc6	140	unsigned int time = 0, start_addr = 0;
19d2e342	141	int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
29905a45	142	unsigned start = get_timer(0);
af62a557	143
56b34bc6 PM	144	/* Timeout unit - ms */
56b34bc6 PM	145	static unsigned int cmd_timeout = CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT;
af62a557 LW	146
	147	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
	148	mask = SDHCI_CMD_INHIBIT \| SDHCI_DATA_INHIBIT;
	149
	150	/* We shouldn't wait for data inihibit for stop commands, even
	151	though they might use busy signaling */
	152	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
	153	mask &= ~SDHCI_DATA_INHIBIT;
	154
	155	while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
56b34bc6	156	if (time >= cmd_timeout) {
30e6d979	157	printf("%s: MMC: %d busy ", __func__, mmc_dev);
56b34bc6 PM	158	if (2 * cmd_timeout <= CONFIG_SDHCI_CMD_MAX_TIMEOUT) {
	159	cmd_timeout += cmd_timeout;
	160	printf("timeout increasing to: %u ms.\n",
	161	cmd_timeout);
	162	} else {
	163	puts("timeout.\n");
	164	return COMM_ERR;
	165	}
af62a557	166	}
56b34bc6	167	time++;
af62a557 LW	168	udelay(1000);
	169	}
	170
	171	mask = SDHCI_INT_RESPONSE;
	172	if (!(cmd->resp_type & MMC_RSP_PRESENT))
	173	flags = SDHCI_CMD_RESP_NONE;
	174	else if (cmd->resp_type & MMC_RSP_136)
	175	flags = SDHCI_CMD_RESP_LONG;
	176	else if (cmd->resp_type & MMC_RSP_BUSY) {
	177	flags = SDHCI_CMD_RESP_SHORT_BUSY;
	178	mask \|= SDHCI_INT_DATA_END;
	179	} else
	180	flags = SDHCI_CMD_RESP_SHORT;
	181
	182	if (cmd->resp_type & MMC_RSP_CRC)
	183	flags \|= SDHCI_CMD_CRC;
	184	if (cmd->resp_type & MMC_RSP_OPCODE)
	185	flags \|= SDHCI_CMD_INDEX;
	186	if (data)
	187	flags \|= SDHCI_CMD_DATA;
	188
30e6d979	189	/* Set Transfer mode regarding to data flag */
af62a557 LW	190	if (data != 0) {
	191	sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
	192	mode = SDHCI_TRNS_BLK_CNT_EN;
	193	trans_bytes = data->blocks * data->blocksize;
	194	if (data->blocks > 1)
	195	mode \|= SDHCI_TRNS_MULTI;
	196
	197	if (data->flags == MMC_DATA_READ)
	198	mode \|= SDHCI_TRNS_READ;
	199
	200	#ifdef CONFIG_MMC_SDMA
	201	if (data->flags == MMC_DATA_READ)
3c1fcb77	202	start_addr = (unsigned long)data->dest;
af62a557	203	else
3c1fcb77	204	start_addr = (unsigned long)data->src;
af62a557 LW	205	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
	206	(start_addr & 0x7) != 0x0) {
	207	is_aligned = 0;
3c1fcb77	208	start_addr = (unsigned long)aligned_buffer;
af62a557 LW	209	if (data->flags != MMC_DATA_READ)
	210	memcpy(aligned_buffer, data->src, trans_bytes);
	211	}
	212
492d3223 SR	213	#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
	214	/*
	215	* Always use this bounce-buffer when
	216	* CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
	217	*/
	218	is_aligned = 0;
	219	start_addr = (unsigned long)aligned_buffer;
	220	if (data->flags != MMC_DATA_READ)
	221	memcpy(aligned_buffer, data->src, trans_bytes);
	222	#endif
	223
af62a557 LW	224	sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
	225	mode \|= SDHCI_TRNS_DMA;
	226	#endif
	227	sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
	228	data->blocksize),
	229	SDHCI_BLOCK_SIZE);
	230	sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
	231	sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
5e1c23cd KL	232	} else if (cmd->resp_type & MMC_RSP_BUSY) {
5e1c23cd KL	233	sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
af62a557 LW	234	}
	235
	236	sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
	237	#ifdef CONFIG_MMC_SDMA
2c2ec4c9	238	flush_cache(start_addr, trans_bytes);
af62a557 LW	239	#endif
af62a557 LW	240	sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
29905a45	241	start = get_timer(0);
af62a557 LW	242	do {
	243	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	244	if (stat & SDHCI_INT_ERROR)
	245	break;
29905a45	246	} while (((stat & mask) != mask) &&
d90bb439	247	(get_timer(start) < SDHCI_READ_STATUS_TIMEOUT));
af62a557	248
d90bb439	249	if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
3a638320 JC	250	if (host->quirks & SDHCI_QUIRK_BROKEN_R1B)
	251	return 0;
	252	else {
30e6d979	253	printf("%s: Timeout for status update!\n", __func__);
3a638320 JC	254	return TIMEOUT;
	255	}
	256	}
	257
af62a557 LW	258	if ((stat & (SDHCI_INT_ERROR \| mask)) == mask) {
	259	sdhci_cmd_done(host, cmd);
	260	sdhci_writel(host, mask, SDHCI_INT_STATUS);
	261	} else
	262	ret = -1;
	263
	264	if (!ret && data)
	265	ret = sdhci_transfer_data(host, data, start_addr);
	266
13243f2e TB	267	if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
	268	udelay(1000);
	269
af62a557 LW	270	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	271	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
	272	if (!ret) {
	273	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
	274	!is_aligned && (data->flags == MMC_DATA_READ))
	275	memcpy(data->dest, aligned_buffer, trans_bytes);
	276	return 0;
	277	}
	278
	279	sdhci_reset(host, SDHCI_RESET_CMD);
	280	sdhci_reset(host, SDHCI_RESET_DATA);
	281	if (stat & SDHCI_INT_TIMEOUT)
	282	return TIMEOUT;
	283	else
	284	return COMM_ERR;
	285	}
	286
	287	static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
	288	{
93bfd616	289	struct sdhci_host *host = mmc->priv;
79667b7b	290	unsigned int div, clk, timeout, reg;
af62a557	291
79667b7b WY	292	/* Wait max 20 ms */
	293	timeout = 200;
	294	while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
	295	(SDHCI_CMD_INHIBIT \| SDHCI_DATA_INHIBIT)) {
	296	if (timeout == 0) {
	297	printf("%s: Timeout to wait cmd & data inhibit\n",
	298	__func__);
	299	return -1;
	300	}
	301
	302	timeout--;
	303	udelay(100);
	304	}
	305
	306	reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
	307	reg &= ~SDHCI_CLOCK_CARD_EN;
	308	sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
af62a557 LW	309
	310	if (clock == 0)
	311	return 0;
	312
113e5dfc	313	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
af62a557	314	/* Version 3.00 divisors must be a multiple of 2. */
93bfd616	315	if (mmc->cfg->f_max <= clock)
af62a557 LW	316	div = 1;
	317	else {
	318	for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
93bfd616	319	if ((mmc->cfg->f_max / div) <= clock)
af62a557 LW	320	break;
	321	}
	322	}
	323	} else {
	324	/* Version 2.00 divisors must be a power of 2. */
	325	for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
93bfd616	326	if ((mmc->cfg->f_max / div) <= clock)
af62a557 LW	327	break;
	328	}
	329	}
	330	div >>= 1;
	331
b09ed6e4 JC	332	if (host->set_clock)
	333	host->set_clock(host->index, div);
	334
af62a557 LW	335	clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
	336	clk \|= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
	337	<< SDHCI_DIVIDER_HI_SHIFT;
	338	clk \|= SDHCI_CLOCK_INT_EN;
	339	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	340
	341	/* Wait max 20 ms */
	342	timeout = 20;
	343	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
	344	& SDHCI_CLOCK_INT_STABLE)) {
	345	if (timeout == 0) {
30e6d979 DR	346	printf("%s: Internal clock never stabilised.\n",
30e6d979 DR	347	__func__);
af62a557 LW	348	return -1;
	349	}
	350	timeout--;
	351	udelay(1000);
	352	}
	353
	354	clk \|= SDHCI_CLOCK_CARD_EN;
	355	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	356	return 0;
	357	}
	358
	359	static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
	360	{
	361	u8 pwr = 0;
	362
	363	if (power != (unsigned short)-1) {
	364	switch (1 << power) {
	365	case MMC_VDD_165_195:
	366	pwr = SDHCI_POWER_180;
	367	break;
	368	case MMC_VDD_29_30:
	369	case MMC_VDD_30_31:
	370	pwr = SDHCI_POWER_300;
	371	break;
	372	case MMC_VDD_32_33:
	373	case MMC_VDD_33_34:
	374	pwr = SDHCI_POWER_330;
	375	break;
	376	}
	377	}
	378
	379	if (pwr == 0) {
	380	sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
	381	return;
	382	}
	383
688c2d14 MC	384	if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
	385	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
	386
af62a557 LW	387	pwr \|= SDHCI_POWER_ON;
	388
	389	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
	390	}
	391
6588c78b	392	static void sdhci_set_ios(struct mmc *mmc)
af62a557 LW	393	{
af62a557 LW	394	u32 ctrl;
93bfd616	395	struct sdhci_host *host = mmc->priv;
af62a557	396
236bfecf JC	397	if (host->set_control_reg)
	398	host->set_control_reg(host);
	399
af62a557 LW	400	if (mmc->clock != host->clock)
	401	sdhci_set_clock(mmc, mmc->clock);
	402
	403	/* Set bus width */
	404	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	405	if (mmc->bus_width == 8) {
	406	ctrl &= ~SDHCI_CTRL_4BITBUS;
113e5dfc JC	407	if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) \|\|
113e5dfc JC	408	(host->quirks & SDHCI_QUIRK_USE_WIDE8))
af62a557 LW	409	ctrl \|= SDHCI_CTRL_8BITBUS;
af62a557 LW	410	} else {
f88a429f MR	411	if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) \|\|
f88a429f MR	412	(host->quirks & SDHCI_QUIRK_USE_WIDE8))
af62a557 LW	413	ctrl &= ~SDHCI_CTRL_8BITBUS;
	414	if (mmc->bus_width == 4)
	415	ctrl \|= SDHCI_CTRL_4BITBUS;
	416	else
	417	ctrl &= ~SDHCI_CTRL_4BITBUS;
	418	}
	419
	420	if (mmc->clock > 26000000)
	421	ctrl \|= SDHCI_CTRL_HISPD;
	422	else
	423	ctrl &= ~SDHCI_CTRL_HISPD;
	424
236bfecf JC	425	if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
	426	ctrl &= ~SDHCI_CTRL_HISPD;
	427
af62a557 LW	428	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
	429	}
	430
6588c78b	431	static int sdhci_init(struct mmc *mmc)
af62a557	432	{
93bfd616	433	struct sdhci_host *host = mmc->priv;
af62a557 LW	434
	435	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
	436	aligned_buffer = memalign(8, 512*1024);
	437	if (!aligned_buffer) {
30e6d979 DR	438	printf("%s: Aligned buffer alloc failed!!!\n",
30e6d979 DR	439	__func__);
af62a557 LW	440	return -1;
	441	}
	442	}
	443
93bfd616	444	sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
470dcc75 JH	445
470dcc75 JH	446	if (host->quirks & SDHCI_QUIRK_NO_CD) {
102142c9 AP	447	#if defined(CONFIG_PIC32_SDHCI)
	448	/* PIC32 SDHCI CD errata:
	449	* - set CD_TEST and clear CD_TEST_INS bit
	450	*/
	451	sdhci_writeb(host, SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL);
	452	#else
470dcc75 JH	453	unsigned int status;
470dcc75 JH	454
e113fe3c	455	sdhci_writeb(host, SDHCI_CTRL_CD_TEST_INS \| SDHCI_CTRL_CD_TEST,
470dcc75 JH	456	SDHCI_HOST_CONTROL);
	457
	458	status = sdhci_readl(host, SDHCI_PRESENT_STATE);
	459	while ((!(status & SDHCI_CARD_PRESENT)) \|\|
	460	(!(status & SDHCI_CARD_STATE_STABLE)) \|\|
	461	(!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
	462	status = sdhci_readl(host, SDHCI_PRESENT_STATE);
102142c9	463	#endif
470dcc75 JH	464	}
470dcc75 JH	465
ce0c1bc1	466	/* Enable only interrupts served by the SD controller */
30e6d979 DR	467	sdhci_writel(host, SDHCI_INT_DATA_MASK \| SDHCI_INT_CMD_MASK,
30e6d979 DR	468	SDHCI_INT_ENABLE);
ce0c1bc1 ŁM	469	/* Mask all sdhci interrupt sources */
ce0c1bc1 ŁM	470	sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
af62a557	471
af62a557 LW	472	return 0;
	473	}
	474
ab769f22 PA	475
	476	static const struct mmc_ops sdhci_ops = {
	477	.send_cmd = sdhci_send_command,
	478	.set_ios = sdhci_set_ios,
	479	.init = sdhci_init,
	480	};
	481
af62a557 LW	482	int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
af62a557 LW	483	{
af62a557 LW	484	unsigned int caps;
af62a557 LW	485
93bfd616 PA	486	host->cfg.name = host->name;
93bfd616 PA	487	host->cfg.ops = &sdhci_ops;
af62a557 LW	488
	489	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
	490	#ifdef CONFIG_MMC_SDMA
	491	if (!(caps & SDHCI_CAN_DO_SDMA)) {
30e6d979 DR	492	printf("%s: Your controller doesn't support SDMA!!\n",
30e6d979 DR	493	__func__);
af62a557 LW	494	return -1;
	495	}
	496	#endif
	497
	498	if (max_clk)
93bfd616	499	host->cfg.f_max = max_clk;
af62a557	500	else {
113e5dfc	501	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
93bfd616	502	host->cfg.f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
af62a557 LW	503	>> SDHCI_CLOCK_BASE_SHIFT;
af62a557 LW	504	else
93bfd616	505	host->cfg.f_max = (caps & SDHCI_CLOCK_BASE_MASK)
af62a557	506	>> SDHCI_CLOCK_BASE_SHIFT;
93bfd616	507	host->cfg.f_max *= 1000000;
af62a557	508	}
93bfd616	509	if (host->cfg.f_max == 0) {
30e6d979 DR	510	printf("%s: Hardware doesn't specify base clock frequency\n",
30e6d979 DR	511	__func__);
af62a557 LW	512	return -1;
	513	}
	514	if (min_clk)
93bfd616	515	host->cfg.f_min = min_clk;
af62a557	516	else {
113e5dfc	517	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
93bfd616 PA	518	host->cfg.f_min = host->cfg.f_max /
93bfd616 PA	519	SDHCI_MAX_DIV_SPEC_300;
af62a557	520	else
93bfd616 PA	521	host->cfg.f_min = host->cfg.f_max /
93bfd616 PA	522	SDHCI_MAX_DIV_SPEC_200;
af62a557 LW	523	}
af62a557 LW	524
93bfd616	525	host->cfg.voltages = 0;
af62a557	526	if (caps & SDHCI_CAN_VDD_330)
93bfd616	527	host->cfg.voltages \|= MMC_VDD_32_33 \| MMC_VDD_33_34;
af62a557	528	if (caps & SDHCI_CAN_VDD_300)
93bfd616	529	host->cfg.voltages \|= MMC_VDD_29_30 \| MMC_VDD_30_31;
af62a557	530	if (caps & SDHCI_CAN_VDD_180)
93bfd616	531	host->cfg.voltages \|= MMC_VDD_165_195;
236bfecf JC	532
236bfecf JC	533	if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
93bfd616	534	host->cfg.voltages \|= host->voltages;
236bfecf	535
93bfd616	536	host->cfg.host_caps = MMC_MODE_HS \| MMC_MODE_HS_52MHz \| MMC_MODE_4BIT;
113e5dfc	537	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
1695b29a	538	if (caps & SDHCI_CAN_DO_8BIT)
93bfd616	539	host->cfg.host_caps \|= MMC_MODE_8BIT;
1695b29a	540	}
42979002 SDPP	541
	542	if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
	543	host->cfg.host_caps &= ~(MMC_MODE_HS \| MMC_MODE_HS_52MHz);
	544
236bfecf	545	if (host->host_caps)
93bfd616 PA	546	host->cfg.host_caps \|= host->host_caps;
	547
	548	host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
af62a557 LW	549
af62a557 LW	550	sdhci_reset(host, SDHCI_RESET_ALL);
93bfd616 PA	551
	552	host->mmc = mmc_create(&host->cfg, host);
	553	if (host->mmc == NULL) {
	554	printf("%s: mmc create fail!\n", __func__);
	555	return -1;
	556	}
af62a557 LW	557
	558	return 0;
	559	}