[J-u-boot.git] / drivers / misc / mpc83xx_serdes.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2018
 * Mario Six, Guntermann & Drunck GmbH, [email protected]
 */

/**
 * enum srdscr0_mask - Bit masks for SRDSCR0 (SerDes Control Register 0)
 * @SRDSCR0_DPPA:       Bitmask for the DPPA (diff pk-pk swing for lane A)
 *			field of the SRCSCR0
 * @SRDSCR0_DPPE:       Bitmask for the DPPE (diff pk-pk swing for lane E)
 *			field of the SRCSCR0
 * @SRDSCR0_DPP_1V2:    Combined bitmask to set diff pk-pk swing for both lanes
 * @SRDSCR0_TXEQA_MASK: Bitmask for the TXEQA (transmit equalization for
 *			lane A) field of the SRCSCR0
 * @SRDSCR0_TXEQA_SATA: Bitmask to set the TXEQA to the value used for SATA
 * @SRDSCR0_TXEQE_MASK: Bitmask for the TXEQE (transmit equalization for
 *			lane E) field of the SRCSCR0
 * @SRDSCR0_TXEQE_SATA: Bitmask to set the TXEQE to the value used for SATA
 */
#include <linux/bitops.h>
enum srdscr0_mask {
	SRDSCR0_DPPA        = BIT(31 - 16),
	SRDSCR0_DPPE        = BIT(31 - 20),
	SRDSCR0_DPP_1V2    = SRDSCR0_DPPE | SRDSCR0_DPPA,

	SRDSCR0_TXEQA_MASK = 0x00007000,
	SRDSCR0_TXEQA_SATA = 0x00001000,
	SRDSCR0_TXEQE_MASK = 0x00000700,
	SRDSCR0_TXEQE_SATA = 0x00000100,
};

/**
 * enum srdscr1_mask - Bit masks for SRDSCR1 (SerDes Control Register 1)
 * @SRDSCR1_PLLBW: Bitmask for the PLLBW (PLL bandwidth) field of SRDSCR1
 */
enum srdscr1_mask {
	SRDSCR1_PLLBW = BIT(31 - 25),
};

/**
 * enum srdscr2_mask - Bit masks for SRDSCR2 (SerDes Control Register 2)
 * @SRDSCR2_VDD_1V2:     Bit mask to to set the VDD field of the SCRSCR2
 * @SRDSCR2_SEICA_MASK:  Bitmask for the SEICA (Receiver electrical idle
 *			 detection control for lane A) field of the SRCSCR2
 * @SRDSCR2_SEICE_MASK:  Bitmask for the SEICE (Receiver electrical idle
 *			 detection control for lane E) field of the SRCSCR2
 * @SRDSCR2_SEIC_MASK:   Combined bitmask to set the receiver electrical idle
 *			 detection control for both lanes
 * @SRDSCR2_SEICA_SATA:  Bitmask to set the SEICA field to the value used for
 *			 SATA
 * @SRDSCR2_SEICE_SATA:  Bitmask to set the SEICE field to the value used for
 *			 SATA
 * @SRDSCR2_SEIC_SATA:   Combined bitmask to set the value of both SEIC fields
 *			 to the value used for SATA
 * @SRDSCR2_SEICA_PEX:   Bitmask to set the SEICA field to the value used for
 *			 PCI Express
 * @SRDSCR2_SEICE_PEX:   Bitmask to set the SEICE field to the value used for
 *			 PCI Express
 * @SRDSCR2_SEIC_PEX:    Combined bitmask to set the value of both SEIC fields
 *			 to the value used for PCI Express
 * @SRDSCR2_SEICA_SGMII: Bitmask to set the SEICA field to the value used for
 *			 SGMII
 * @SRDSCR2_SEICE_SGMII: Bitmask to set the SEICE field to the value used for
 *			 SGMII
 * @SRDSCR2_SEIC_SGMII:  Combined bitmask to set the value of both SEIC fields
 *			 to the value used for SGMII
 */
enum srdscr2_mask {
	SRDSCR2_VDD_1V2     = 0x00800000,

	SRDSCR2_SEICA_MASK  = 0x00001c00,
	SRDSCR2_SEICE_MASK  = 0x0000001c,
	SRDSCR2_SEIC_MASK   = SRDSCR2_SEICA_MASK | SRDSCR2_SEICE_MASK,

	SRDSCR2_SEICA_SATA  = 0x00001400,
	SRDSCR2_SEICE_SATA  = 0x00000014,
	SRDSCR2_SEIC_SATA   = SRDSCR2_SEICA_SATA | SRDSCR2_SEICE_SATA,

	SRDSCR2_SEICA_PEX   = 0x00001000,
	SRDSCR2_SEICE_PEX   = 0x00000010,
	SRDSCR2_SEIC_PEX    = SRDSCR2_SEICA_PEX | SRDSCR2_SEICE_PEX,

	SRDSCR2_SEICA_SGMII = 0x00000100,
	SRDSCR2_SEICE_SGMII = 0x00000001,
	SRDSCR2_SEIC_SGMII  = SRDSCR2_SEICA_SGMII | SRDSCR2_SEICE_SGMII,
};

/**
 * enum srdscr3_mask - Bit masks for SRDSCR3 (SerDes Control Register 3)
 * @SRDSCR3_KFRA_SATA:      Bitmask to set the KFRA field of SRDSCR3 to the
 *			    value used by SATA
 * @SRDSCR3_KFRE_SATA:      Bitmask to set the KFRE field of SRDSCR3 to the
 *			    value used by SATA
 * @SRDSCR3_KFR_SATA:       Combined bitmask to set both KFR fields to the
 *			    value used by SATA
 * @SRDSCR3_KPHA_SATA:      Bitmask to set the KPHA field of SRDSCR3 to the
 *			    value used by SATA
 * @SRDSCR3_KPHE_SATA:      Bitmask to set the KPHE field of SRDSCR3 to the
 *			    value used by SATA
 * @SRDSCR3_KPH_SATA:       Combined bitmask to set both KPH fields to the
 *			    value used by SATA
 * @SRDSCR3_SDFMA_SATA_PEX: Bitmask to set the SDFMA field of SRDSCR3 to the
 *			    value used by SATA and PCI Express
 * @SRDSCR3_SDFME_SATA_PEX: Bitmask to set the SDFME field of SRDSCR3 to the
 *			    value used by SATA and PCI Express
 * @SRDSCR3_SDFM_SATA_PEX:  Combined bitmask to set both SDFM fields to the
 *			    value used by SATA and PCI Express
 * @SRDSCR3_SDTXLA_SATA:    Bitmask to set the SDTXLA field of SRDSCR3 to the
 *			    value used by SATA
 * @SRDSCR3_SDTXLE_SATA:    Bitmask to set the SDTXLE field of SRDSCR3 to the
 *			    value used by SATA
 * @SRDSCR3_SDTXL_SATA:     Combined bitmask to set both SDTXL fields to the
 *			    value used by SATA
 *
 * KFRA = 'Kfr' gain selection in the CDR for lane A
 * KFRE = 'Kfr' gain selection in the CDR for lane E
 * SDFMA = Bandwidth of digital filter for lane A
 * SDFME = Bandwidth of digital filter for lane E
 * SDTXLA = Lane A transmitter amplitude levels
 * SDTXLE = Lane E transmitter amplitude levels
 */
enum srdscr3_mask {
	SRDSCR3_KFRA_SATA      = 0x10000000,
	SRDSCR3_KFRE_SATA      = 0x00100000,
	SRDSCR3_KFR_SATA       = SRDSCR3_KFRA_SATA | SRDSCR3_KFRE_SATA,

	SRDSCR3_KPHA_SATA      = 0x04000000,
	SRDSCR3_KPHE_SATA      = 0x00040000,
	SRDSCR3_KPH_SATA       = SRDSCR3_KPHA_SATA | SRDSCR3_KPHE_SATA,

	SRDSCR3_SDFMA_SATA_PEX = 0x01000000,
	SRDSCR3_SDFME_SATA_PEX = 0x00010000,
	SRDSCR3_SDFM_SATA_PEX  = SRDSCR3_SDFMA_SATA_PEX | SRDSCR3_SDFME_SATA_PEX,

	SRDSCR3_SDTXLA_SATA    = 0x00000500,
	SRDSCR3_SDTXLE_SATA    = 0x00000005,
	SRDSCR3_SDTXL_SATA     = SRDSCR3_SDTXLA_SATA | SRDSCR3_SDTXLE_SATA,
};

/**
 * enum srdscr4_mask - Bit masks for SRDSCR4 (SerDes Control Register 4)
 * @SRDSCR4_PROTA_SATA:  Bitmask to set the PROTA field of SRDSCR4 to the
 *			 value used by SATA
 * @SRDSCR4_PROTE_SATA:  Bitmask to set the PROTE field of SRDSCR4 to the
 *			 value used by SATA
 * @SRDSCR4_PROT_SATA:   Combined bitmask to set both PROT fields to the
 *			 value used by SATA
 * @SRDSCR4_PROTA_PEX:   Bitmask to set the PROTA field of SRDSCR4 to the
 *			 value used by PCI Express
 * @SRDSCR4_PROTE_PEX:   Bitmask to set the PROTE field of SRDSCR4 to the
 *			 value used by PCI Express
 * @SRDSCR4_PROT_PEX:    Combined bitmask to set both PROT fields to the
 *			 value used by PCI Express
 * @SRDSCR4_PROTA_SGMII: Bitmask to set the PROTA field of SRDSCR4 to the
 *			 value used by SGMII
 * @SRDSCR4_PROTE_SGMII: Bitmask to set the PROTE field of SRDSCR4 to the
 *			 value used by SGMII
 * @SRDSCR4_PROT_SGMII:  Combined bitmask to set both PROT fields to the
 *			 value used by SGMII
 * @SRDSCR4_PLANE_X2:    Bitmask to set the PLANE field of SRDSCR4
 * @SRDSCR4_RFCKS_100:   Bitmask to set the RFCKS field of SRDSCR4 to the
 *			 value 100Mhz
 * @SRDSCR4_RFCKS_125:   Bitmask to set the RFCKS field of SRDSCR4 to the
 *			 value 125Mhz
 * @SRDSCR4_RFCKS_150:   Bitmask to set the RFCKS field of SRDSCR4 to the
 *			 value 150Mhz
 *
 * PROTA = Lane A protocol select
 * PROTE = Lane E protocol select
 * PLAME = Number of PCI Express lanes
 */
enum srdscr4_mask {
	SRDSCR4_PROTA_SATA  = 0x00000800,
	SRDSCR4_PROTE_SATA  = 0x00000008,
	SRDSCR4_PROT_SATA   = SRDSCR4_PROTA_SATA | SRDSCR4_PROTE_SATA,

	SRDSCR4_PROTA_PEX   = 0x00000100,
	SRDSCR4_PROTE_PEX   = 0x00000001,
	SRDSCR4_PROT_PEX    = SRDSCR4_PROTA_PEX | SRDSCR4_PROTE_PEX,

	SRDSCR4_PROTA_SGMII = 0x00000500,
	SRDSCR4_PROTE_SGMII = 0x00000005,
	SRDSCR4_PROT_SGMII  = SRDSCR4_PROTA_SGMII | SRDSCR4_PROTE_SGMII,

	SRDSCR4_PLANE_X2    = 0x01000000,

	SRDSCR4_RFCKS_100 = (0 << 28),
	SRDSCR4_RFCKS_125 = (1 << 28),
	SRDSCR4_RFCKS_150 = (3 << 28),
};

/**
 * enum srdsrstctl_mask - Bit masks for SRDSRSTCTL (SerDes Reset Control Register)
 * @SRDSRSTCTL_RST:        Bitmask for the RST (Software reset) field of the
 *			   SRDSRSTCTL
 * @SRDSRSTCTL_SATA_RESET: Bitmask for the SATA_RESET (SATA reset) field of the
 *			   SRDSRSTCTL
 */
enum srdsrstctl_mask {
	SRDSRSTCTL_RST        = 0x80000000,
	SRDSRSTCTL_SATA_RESET = 0xf,
};

/**
 * struct mpc83xx_serdes_regs - Register map of the SerDes controller
 * @srdscr0:    SerDes Control Register 0
 * @srdscr1:    SerDes Control Register 1
 * @srdscr2:    SerDes Control Register 2
 * @srdscr3:    SerDes Control Register 3
 * @srdscr4:    SerDes Control Register 4
 * @fill0:      Reserved space in the register map
 * @srdsrstctl: SerDes Reset Control Register
 */
struct mpc83xx_serdes_regs {
	u32 srdscr0;
	u32 srdscr1;
	u32 srdscr2;
	u32 srdscr3;
	u32 srdscr4;
	u8 fill0[12];
	u32 srdsrstctl;
};

/**
 * enum pex_type - Types of PCI Express
 * @PEX_X1: PCI Express in x1 mode
 * @PEX_X2: PCI Express in x2 mode
 */
enum pex_type {
	PEX_X1,
	PEX_X2,
};
Commit	Line	Data
d2166319 MS	1	/* SPDX-License-Identifier: GPL-2.0+ */
	2	/*
	3	* (C) Copyright 2018
	4	* Mario Six, Guntermann & Drunck GmbH, [email protected]
	5	*/
	6
	7	/**
	8	* enum srdscr0_mask - Bit masks for SRDSCR0 (SerDes Control Register 0)
	9	* @SRDSCR0_DPPA: Bitmask for the DPPA (diff pk-pk swing for lane A)
	10	* field of the SRCSCR0
	11	* @SRDSCR0_DPPE: Bitmask for the DPPE (diff pk-pk swing for lane E)
	12	* field of the SRCSCR0
	13	* @SRDSCR0_DPP_1V2: Combined bitmask to set diff pk-pk swing for both lanes
	14	* @SRDSCR0_TXEQA_MASK: Bitmask for the TXEQA (transmit equalization for
	15	* lane A) field of the SRCSCR0
	16	* @SRDSCR0_TXEQA_SATA: Bitmask to set the TXEQA to the value used for SATA
	17	* @SRDSCR0_TXEQE_MASK: Bitmask for the TXEQE (transmit equalization for
	18	* lane E) field of the SRCSCR0
	19	* @SRDSCR0_TXEQE_SATA: Bitmask to set the TXEQE to the value used for SATA
	20	*/
cd93d625	21	#include <linux/bitops.h>
d2166319 MS	22	enum srdscr0_mask {
	23	SRDSCR0_DPPA = BIT(31 - 16),
	24	SRDSCR0_DPPE = BIT(31 - 20),
	25	SRDSCR0_DPP_1V2 = SRDSCR0_DPPE \| SRDSCR0_DPPA,
	26
	27	SRDSCR0_TXEQA_MASK = 0x00007000,
	28	SRDSCR0_TXEQA_SATA = 0x00001000,
	29	SRDSCR0_TXEQE_MASK = 0x00000700,
	30	SRDSCR0_TXEQE_SATA = 0x00000100,
	31	};
	32
	33	/**
	34	* enum srdscr1_mask - Bit masks for SRDSCR1 (SerDes Control Register 1)
	35	* @SRDSCR1_PLLBW: Bitmask for the PLLBW (PLL bandwidth) field of SRDSCR1
	36	*/
	37	enum srdscr1_mask {
	38	SRDSCR1_PLLBW = BIT(31 - 25),
	39	};
	40
	41	/**
	42	* enum srdscr2_mask - Bit masks for SRDSCR2 (SerDes Control Register 2)
	43	* @SRDSCR2_VDD_1V2: Bit mask to to set the VDD field of the SCRSCR2
	44	* @SRDSCR2_SEICA_MASK: Bitmask for the SEICA (Receiver electrical idle
	45	* detection control for lane A) field of the SRCSCR2
	46	* @SRDSCR2_SEICE_MASK: Bitmask for the SEICE (Receiver electrical idle
	47	* detection control for lane E) field of the SRCSCR2
	48	* @SRDSCR2_SEIC_MASK: Combined bitmask to set the receiver electrical idle
	49	* detection control for both lanes
	50	* @SRDSCR2_SEICA_SATA: Bitmask to set the SEICA field to the value used for
	51	* SATA
	52	* @SRDSCR2_SEICE_SATA: Bitmask to set the SEICE field to the value used for
	53	* SATA
	54	* @SRDSCR2_SEIC_SATA: Combined bitmask to set the value of both SEIC fields
	55	* to the value used for SATA
	56	* @SRDSCR2_SEICA_PEX: Bitmask to set the SEICA field to the value used for
	57	* PCI Express
	58	* @SRDSCR2_SEICE_PEX: Bitmask to set the SEICE field to the value used for
	59	* PCI Express
	60	* @SRDSCR2_SEIC_PEX: Combined bitmask to set the value of both SEIC fields
	61	* to the value used for PCI Express
	62	* @SRDSCR2_SEICA_SGMII: Bitmask to set the SEICA field to the value used for
	63	* SGMII
	64	* @SRDSCR2_SEICE_SGMII: Bitmask to set the SEICE field to the value used for
	65	* SGMII
	66	* @SRDSCR2_SEIC_SGMII: Combined bitmask to set the value of both SEIC fields
	67	* to the value used for SGMII
	68	*/
	69	enum srdscr2_mask {
	70	SRDSCR2_VDD_1V2 = 0x00800000,
	71
	72	SRDSCR2_SEICA_MASK = 0x00001c00,
	73	SRDSCR2_SEICE_MASK = 0x0000001c,
	74	SRDSCR2_SEIC_MASK = SRDSCR2_SEICA_MASK \| SRDSCR2_SEICE_MASK,
	75
	76	SRDSCR2_SEICA_SATA = 0x00001400,
	77	SRDSCR2_SEICE_SATA = 0x00000014,
	78	SRDSCR2_SEIC_SATA = SRDSCR2_SEICA_SATA \| SRDSCR2_SEICE_SATA,
	79
	80	SRDSCR2_SEICA_PEX = 0x00001000,
	81	SRDSCR2_SEICE_PEX = 0x00000010,
	82	SRDSCR2_SEIC_PEX = SRDSCR2_SEICA_PEX \| SRDSCR2_SEICE_PEX,
	83
	84	SRDSCR2_SEICA_SGMII = 0x00000100,
	85	SRDSCR2_SEICE_SGMII = 0x00000001,
86	SRDSCR2_SEIC_SGMII = SRDSCR2_SEICA_SGMII \| SRDSCR2_SEICE_SGMII,
87	};
88
89	/**
90	* enum srdscr3_mask - Bit masks for SRDSCR3 (SerDes Control Register 3)
91	* @SRDSCR3_KFRA_SATA: Bitmask to set the KFRA field of SRDSCR3 to the
92	* value used by SATA
93	* @SRDSCR3_KFRE_SATA: Bitmask to set the KFRE field of SRDSCR3 to the
94	* value used by SATA
95	* @SRDSCR3_KFR_SATA: Combined bitmask to set both KFR fields to the
96	* value used by SATA
97	* @SRDSCR3_KPHA_SATA: Bitmask to set the KPHA field of SRDSCR3 to the
98	* value used by SATA
99	* @SRDSCR3_KPHE_SATA: Bitmask to set the KPHE field of SRDSCR3 to the
100	* value used by SATA
101	* @SRDSCR3_KPH_SATA: Combined bitmask to set both KPH fields to the
102	* value used by SATA
103	* @SRDSCR3_SDFMA_SATA_PEX: Bitmask to set the SDFMA field of SRDSCR3 to the
104	* value used by SATA and PCI Express
105	* @SRDSCR3_SDFME_SATA_PEX: Bitmask to set the SDFME field of SRDSCR3 to the
106	* value used by SATA and PCI Express
107	* @SRDSCR3_SDFM_SATA_PEX: Combined bitmask to set both SDFM fields to the
108	* value used by SATA and PCI Express
109	* @SRDSCR3_SDTXLA_SATA: Bitmask to set the SDTXLA field of SRDSCR3 to the
110	* value used by SATA
111	* @SRDSCR3_SDTXLE_SATA: Bitmask to set the SDTXLE field of SRDSCR3 to the
112	* value used by SATA
113	* @SRDSCR3_SDTXL_SATA: Combined bitmask to set both SDTXL fields to the
114	* value used by SATA
115	*
116	* KFRA = 'Kfr' gain selection in the CDR for lane A
117	* KFRE = 'Kfr' gain selection in the CDR for lane E
118	* SDFMA = Bandwidth of digital filter for lane A
119	* SDFME = Bandwidth of digital filter for lane E
120	* SDTXLA = Lane A transmitter amplitude levels
121	* SDTXLE = Lane E transmitter amplitude levels
122	*/
123	enum srdscr3_mask {
124	SRDSCR3_KFRA_SATA = 0x10000000,
125	SRDSCR3_KFRE_SATA = 0x00100000,
126	SRDSCR3_KFR_SATA = SRDSCR3_KFRA_SATA \| SRDSCR3_KFRE_SATA,
127
128	SRDSCR3_KPHA_SATA = 0x04000000,
129	SRDSCR3_KPHE_SATA = 0x00040000,
130	SRDSCR3_KPH_SATA = SRDSCR3_KPHA_SATA \| SRDSCR3_KPHE_SATA,
131
132	SRDSCR3_SDFMA_SATA_PEX = 0x01000000,
133	SRDSCR3_SDFME_SATA_PEX = 0x00010000,
134	SRDSCR3_SDFM_SATA_PEX = SRDSCR3_SDFMA_SATA_PEX \| SRDSCR3_SDFME_SATA_PEX,
135
136	SRDSCR3_SDTXLA_SATA = 0x00000500,
137	SRDSCR3_SDTXLE_SATA = 0x00000005,
138	SRDSCR3_SDTXL_SATA = SRDSCR3_SDTXLA_SATA \| SRDSCR3_SDTXLE_SATA,
139	};
140
141	/**
142	* enum srdscr4_mask - Bit masks for SRDSCR4 (SerDes Control Register 4)
143	* @SRDSCR4_PROTA_SATA: Bitmask to set the PROTA field of SRDSCR4 to the
144	* value used by SATA
145	* @SRDSCR4_PROTE_SATA: Bitmask to set the PROTE field of SRDSCR4 to the
146	* value used by SATA
147	* @SRDSCR4_PROT_SATA: Combined bitmask to set both PROT fields to the
148	* value used by SATA
149	* @SRDSCR4_PROTA_PEX: Bitmask to set the PROTA field of SRDSCR4 to the
150	* value used by PCI Express
151	* @SRDSCR4_PROTE_PEX: Bitmask to set the PROTE field of SRDSCR4 to the
152	* value used by PCI Express
153	* @SRDSCR4_PROT_PEX: Combined bitmask to set both PROT fields to the
154	* value used by PCI Express
155	* @SRDSCR4_PROTA_SGMII: Bitmask to set the PROTA field of SRDSCR4 to the
156	* value used by SGMII
157	* @SRDSCR4_PROTE_SGMII: Bitmask to set the PROTE field of SRDSCR4 to the
158	* value used by SGMII
159	* @SRDSCR4_PROT_SGMII: Combined bitmask to set both PROT fields to the
160	* value used by SGMII
161	* @SRDSCR4_PLANE_X2: Bitmask to set the PLANE field of SRDSCR4
162	* @SRDSCR4_RFCKS_100: Bitmask to set the RFCKS field of SRDSCR4 to the
163	* value 100Mhz
164	* @SRDSCR4_RFCKS_125: Bitmask to set the RFCKS field of SRDSCR4 to the
165	* value 125Mhz
166	* @SRDSCR4_RFCKS_150: Bitmask to set the RFCKS field of SRDSCR4 to the
167	* value 150Mhz
168	*
169	* PROTA = Lane A protocol select
170	* PROTE = Lane E protocol select
171	* PLAME = Number of PCI Express lanes
172	*/
173	enum srdscr4_mask {
174	SRDSCR4_PROTA_SATA = 0x00000800,
175	SRDSCR4_PROTE_SATA = 0x00000008,
176	SRDSCR4_PROT_SATA = SRDSCR4_PROTA_SATA \| SRDSCR4_PROTE_SATA,
177
178	SRDSCR4_PROTA_PEX = 0x00000100,
179	SRDSCR4_PROTE_PEX = 0x00000001,
180	SRDSCR4_PROT_PEX = SRDSCR4_PROTA_PEX \| SRDSCR4_PROTE_PEX,
181
182	SRDSCR4_PROTA_SGMII = 0x00000500,
183	SRDSCR4_PROTE_SGMII = 0x00000005,
184	SRDSCR4_PROT_SGMII = SRDSCR4_PROTA_SGMII \| SRDSCR4_PROTE_SGMII,
185
186	SRDSCR4_PLANE_X2 = 0x01000000,
187
188	SRDSCR4_RFCKS_100 = (0 << 28),
189	SRDSCR4_RFCKS_125 = (1 << 28),
190	SRDSCR4_RFCKS_150 = (3 << 28),
191	};
192
193	/**
194	* enum srdsrstctl_mask - Bit masks for SRDSRSTCTL (SerDes Reset Control Register)
195	* @SRDSRSTCTL_RST: Bitmask for the RST (Software reset) field of the
196	* SRDSRSTCTL
197	* @SRDSRSTCTL_SATA_RESET: Bitmask for the SATA_RESET (SATA reset) field of the
198	* SRDSRSTCTL
199	*/
200	enum srdsrstctl_mask {
201	SRDSRSTCTL_RST = 0x80000000,
202	SRDSRSTCTL_SATA_RESET = 0xf,
203	};
204
205	/**
206	* struct mpc83xx_serdes_regs - Register map of the SerDes controller
207	* @srdscr0: SerDes Control Register 0
208	* @srdscr1: SerDes Control Register 1
209	* @srdscr2: SerDes Control Register 2
210	* @srdscr3: SerDes Control Register 3
211	* @srdscr4: SerDes Control Register 4
212	* @fill0: Reserved space in the register map
213	* @srdsrstctl: SerDes Reset Control Register
214	*/
215	struct mpc83xx_serdes_regs {
216	u32 srdscr0;
217	u32 srdscr1;
218	u32 srdscr2;
219	u32 srdscr3;
220	u32 srdscr4;
221	u8 fill0[12];
222	u32 srdsrstctl;
223	};
224
225	/**
226	* enum pex_type - Types of PCI Express
227	* @PEX_X1: PCI Express in x1 mode
228	* @PEX_X2: PCI Express in x2 mode
229	*/
230	enum pex_type {
231	PEX_X1,
232	PEX_X2,
233	};