[J-u-boot.git] / drivers / gpio / sh_pfc.c

/*
 * Pinmuxed GPIO support for SuperH.
 * Copy from linux kernel driver/sh/pfc.c
 *
 * Copyright (C) 2008 Magnus Damm
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <log.h>
#include <malloc.h>
#include <asm/bitops.h>
#include <asm/io.h>
#include <sh_pfc.h>
#include <linux/bitops.h>
#include <linux/bug.h>

static struct pinmux_info *gpioc;

#define pfc_phys_to_virt(p, a) ((void *)a)

static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
{
	if (enum_id < r->begin)
		return 0;

	if (enum_id > r->end)
		return 0;

	return 1;
}

static unsigned long gpio_read_raw_reg(void *mapped_reg,
				       unsigned long reg_width)
{
	switch (reg_width) {

	case 8:
		return readb(mapped_reg);
	case 16:
		return readw(mapped_reg);
	case 32:
		return readl(mapped_reg);
	}

	BUG();
	return 0;
}

static void gpio_write_raw_reg(void *mapped_reg,
			       unsigned long reg_width,
			       unsigned long data)
{
	switch (reg_width) {
	case 8:
		writeb(data, mapped_reg);
		return;
	case 16:
		writew(data, mapped_reg);
		return;
	case 32:
		writel(data, mapped_reg);
		return;
	}

	BUG();
}

static int gpio_read_bit(struct pinmux_data_reg *dr,
			 unsigned long offset,
			 unsigned long in_pos)
{
	unsigned long pos;

	pos = dr->reg_width - (in_pos + 1);

	debug("read_bit: addr = %lx, pos = %ld, r_width = %ld\n",
	      dr->reg + offset, pos, dr->reg_width);

	return (gpio_read_raw_reg(dr->mapped_reg + offset,
				  dr->reg_width) >> pos) & 1;
}

static void gpio_write_bit(struct pinmux_data_reg *dr,
			   unsigned long in_pos, unsigned long value)
{
	unsigned long pos;

	pos = dr->reg_width - (in_pos + 1);

	debug("write_bit addr = %lx, value = %d, pos = %ld, "
		 "r_width = %ld\n",
		 dr->reg, !!value, pos, dr->reg_width);

	if (value)
		__set_bit(pos, &dr->reg_shadow);
	else
		__clear_bit(pos, &dr->reg_shadow);

	gpio_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
}

static void config_reg_helper(struct pinmux_info *gpioc,
			      struct pinmux_cfg_reg *crp,
			      unsigned long in_pos,
#if 0
			      void __iomem **mapped_regp,
#else
			      void **mapped_regp,
#endif
			      unsigned long *maskp,
			      unsigned long *posp)
{
	int k;

	*mapped_regp = pfc_phys_to_virt(gpioc, crp->reg);

	if (crp->field_width) {
		*maskp = (1 << crp->field_width) - 1;
		*posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
	} else {
		*maskp = (1 << crp->var_field_width[in_pos]) - 1;
		*posp = crp->reg_width;
		for (k = 0; k <= in_pos; k++)
			*posp -= abs(crp->var_field_width[k]);
	}
}

static int read_config_reg(struct pinmux_info *gpioc,
			   struct pinmux_cfg_reg *crp,
			   unsigned long field)
{
	void *mapped_reg;

	unsigned long mask, pos;

	config_reg_helper(gpioc, crp, field, &mapped_reg, &mask, &pos);

	debug("read_reg: addr = %lx, field = %ld, "
		 "r_width = %ld, f_width = %ld\n",
		 crp->reg, field, crp->reg_width, crp->field_width);

	return (gpio_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
}

static void write_config_reg(struct pinmux_info *gpioc,
			     struct pinmux_cfg_reg *crp,
			     unsigned long field, unsigned long value)
{
	void *mapped_reg;
	unsigned long mask, pos, data;

	config_reg_helper(gpioc, crp, field, &mapped_reg, &mask, &pos);

	debug("write_reg addr = %lx, value = %ld, field = %ld, "
		 "r_width = %ld, f_width = %ld\n",
		 crp->reg, value, field, crp->reg_width, crp->field_width);

	mask = ~(mask << pos);
	value = value << pos;

	data = gpio_read_raw_reg(mapped_reg, crp->reg_width);
	data &= mask;
	data |= value;

	if (gpioc->unlock_reg)
		gpio_write_raw_reg(pfc_phys_to_virt(gpioc, gpioc->unlock_reg),
				   32, ~data);

	gpio_write_raw_reg(mapped_reg, crp->reg_width, data);
}

static int setup_data_reg(struct pinmux_info *gpioc, unsigned gpio)
{
	struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
	struct pinmux_data_reg *data_reg;
	int k, n;

	if (!enum_in_range(gpiop->enum_id, &gpioc->data))
		return -1;

	k = 0;
	while (1) {
		data_reg = gpioc->data_regs + k;

		if (!data_reg->reg_width)
			break;

		data_reg->mapped_reg = pfc_phys_to_virt(gpioc, data_reg->reg);

		for (n = 0; n < data_reg->reg_width; n++) {
			if (data_reg->enum_ids[n] == gpiop->enum_id) {
				gpiop->flags &= ~PINMUX_FLAG_DREG;
				gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
				gpiop->flags &= ~PINMUX_FLAG_DBIT;
				gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
				return 0;
			}
		}
		k++;
	}

	BUG();

	return -1;
}

static void setup_data_regs(struct pinmux_info *gpioc)
{
	struct pinmux_data_reg *drp;
	int k;

	for (k = gpioc->first_gpio; k <= gpioc->last_gpio; k++)
		setup_data_reg(gpioc, k);

	k = 0;
	while (1) {
		drp = gpioc->data_regs + k;

		if (!drp->reg_width)
			break;

		drp->reg_shadow = gpio_read_raw_reg(drp->mapped_reg,
						    drp->reg_width);
		k++;
	}
}

static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
			struct pinmux_data_reg **drp, int *bitp)
{
	struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
	int k, n;

	if (!enum_in_range(gpiop->enum_id, &gpioc->data))
		return -1;

	k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
	n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
	*drp = gpioc->data_regs + k;
	*bitp = n;
	return 0;
}

static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
			  struct pinmux_cfg_reg **crp,
			  int *fieldp, int *valuep,
			  unsigned long **cntp)
{
	struct pinmux_cfg_reg *config_reg;
	unsigned long r_width, f_width, curr_width, ncomb;
	int k, m, n, pos, bit_pos;

	k = 0;
	while (1) {
		config_reg = gpioc->cfg_regs + k;

		r_width = config_reg->reg_width;
		f_width = config_reg->field_width;

		if (!r_width)
			break;

		pos = 0;
		m = 0;
		for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
			if (f_width)
				curr_width = f_width;
			else
				curr_width = config_reg->var_field_width[m];

			ncomb = 1 << curr_width;
			for (n = 0; n < ncomb; n++) {
				if (config_reg->enum_ids[pos + n] == enum_id) {
					*crp = config_reg;
					*fieldp = m;
					*valuep = n;
					*cntp = &config_reg->cnt[m];
					return 0;
				}
			}
			pos += ncomb;
			m++;
		}
		k++;
	}

	return -1;
}

static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio,
			    int pos, pinmux_enum_t *enum_idp)
{
	pinmux_enum_t enum_id = gpioc->gpios[gpio].enum_id;
	pinmux_enum_t *data = gpioc->gpio_data;
	int k;

	if (!enum_in_range(enum_id, &gpioc->data)) {
		if (!enum_in_range(enum_id, &gpioc->mark)) {
			debug("non data/mark enum_id for gpio %d\n", gpio);
			return -1;
		}
	}

	if (pos) {
		*enum_idp = data[pos + 1];
		return pos + 1;
	}

	for (k = 0; k < gpioc->gpio_data_size; k++) {
		if (data[k] == enum_id) {
			*enum_idp = data[k + 1];
			return k + 1;
		}
	}

	debug("cannot locate data/mark enum_id for gpio %d\n", gpio);
	return -1;
}

enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };

static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
			      int pinmux_type, int cfg_mode)
{
	struct pinmux_cfg_reg *cr = NULL;
	pinmux_enum_t enum_id;
	struct pinmux_range *range;
	int in_range, pos, field, value;
	unsigned long *cntp;

	switch (pinmux_type) {

	case PINMUX_TYPE_FUNCTION:
		range = NULL;
		break;

	case PINMUX_TYPE_OUTPUT:
		range = &gpioc->output;
		break;

	case PINMUX_TYPE_INPUT:
		range = &gpioc->input;
		break;

	case PINMUX_TYPE_INPUT_PULLUP:
		range = &gpioc->input_pu;
		break;

	case PINMUX_TYPE_INPUT_PULLDOWN:
		range = &gpioc->input_pd;
		break;

	default:
		goto out_err;
	}

	pos = 0;
	enum_id = 0;
	field = 0;
	value = 0;
	while (1) {
		pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id);
		if (pos <= 0)
			goto out_err;

		if (!enum_id)
			break;

		/* first check if this is a function enum */
		in_range = enum_in_range(enum_id, &gpioc->function);
		if (!in_range) {
			/* not a function enum */
			if (range) {
				/*
				 * other range exists, so this pin is
				 * a regular GPIO pin that now is being
				 * bound to a specific direction.
				 *
				 * for this case we only allow function enums
				 * and the enums that match the other range.
				 */
				in_range = enum_in_range(enum_id, range);

				/*
				 * special case pass through for fixed
				 * input-only or output-only pins without
				 * function enum register association.
				 */
				if (in_range && enum_id == range->force)
					continue;
			} else {
				/*
				 * no other range exists, so this pin
				 * must then be of the function type.
				 *
				 * allow function type pins to select
				 * any combination of function/in/out
				 * in their MARK lists.
				 */
				in_range = 1;
			}
		}

		if (!in_range)
			continue;

		if (get_config_reg(gpioc, enum_id, &cr,
				   &field, &value, &cntp) != 0)
			goto out_err;

		switch (cfg_mode) {
		case GPIO_CFG_DRYRUN:
			if (!*cntp ||
			    (read_config_reg(gpioc, cr, field) != value))
				continue;
			break;

		case GPIO_CFG_REQ:
			write_config_reg(gpioc, cr, field, value);
			*cntp = *cntp + 1;
			break;

		case GPIO_CFG_FREE:
			*cntp = *cntp - 1;
			break;
		}
	}

	return 0;
 out_err:
	return -1;
}

#if 0
static DEFINE_SPINLOCK(gpio_lock);
static struct pinmux_info *chip_to_pinmux(struct gpio_chip *chip)
{
	return container_of(chip, struct pinmux_info, chip);
}
#endif

static int sh_gpio_request(unsigned offset)
{
	struct pinmux_data_reg *dummy;
	int i, ret, pinmux_type;

	ret = -1;

	if (!gpioc)
		goto err_out;

	if ((gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE) != PINMUX_TYPE_NONE)
		goto err_out;

	/* setup pin function here if no data is associated with pin */

	if (get_data_reg(gpioc, offset, &dummy, &i) != 0)
		pinmux_type = PINMUX_TYPE_FUNCTION;
	else
		pinmux_type = PINMUX_TYPE_GPIO;

	if (pinmux_type == PINMUX_TYPE_FUNCTION) {
		if (pinmux_config_gpio(gpioc, offset,
				       pinmux_type,
				       GPIO_CFG_DRYRUN) != 0)
			goto err_out;

		if (pinmux_config_gpio(gpioc, offset,
				       pinmux_type,
				       GPIO_CFG_REQ) != 0)
			BUG();
	}

	gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
	gpioc->gpios[offset].flags |= pinmux_type;

	ret = 0;
err_out:
	return ret;
}

static void sh_gpio_free(unsigned offset)
{
	int pinmux_type;

	if (!gpioc)
		return;

	pinmux_type = gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE;
	pinmux_config_gpio(gpioc, offset, pinmux_type, GPIO_CFG_FREE);
	gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
	gpioc->gpios[offset].flags |= PINMUX_TYPE_NONE;
}

static int pinmux_direction(struct pinmux_info *gpioc,
			    unsigned gpio, int new_pinmux_type)
{
	int pinmux_type;
	int ret = -1;

	if (!gpioc)
		goto err_out;

	pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;

	switch (pinmux_type) {
	case PINMUX_TYPE_GPIO:
		break;
	case PINMUX_TYPE_OUTPUT:
	case PINMUX_TYPE_INPUT:
	case PINMUX_TYPE_INPUT_PULLUP:
	case PINMUX_TYPE_INPUT_PULLDOWN:
		pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE);
		break;
	default:
		goto err_out;
	}

	if (pinmux_config_gpio(gpioc, gpio,
			       new_pinmux_type,
			       GPIO_CFG_DRYRUN) != 0)
		goto err_out;

	if (pinmux_config_gpio(gpioc, gpio,
			       new_pinmux_type,
			       GPIO_CFG_REQ) != 0)
		BUG();

	gpioc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
	gpioc->gpios[gpio].flags |= new_pinmux_type;

	ret = 0;
 err_out:
	return ret;
}

static int sh_gpio_direction_input(unsigned offset)
{
	return pinmux_direction(gpioc, offset, PINMUX_TYPE_INPUT);
}

static void sh_gpio_set_value(struct pinmux_info *gpioc,
			     unsigned gpio, int value)
{
	struct pinmux_data_reg *dr = NULL;
	int bit = 0;

	if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
		BUG();
	else
		gpio_write_bit(dr, bit, value);
}

static int sh_gpio_direction_output(unsigned offset, int value)
{
	sh_gpio_set_value(gpioc, offset, value);
	return pinmux_direction(gpioc, offset, PINMUX_TYPE_OUTPUT);
}

static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio)
{
	struct pinmux_data_reg *dr = NULL;
	int bit = 0, offset = 0;

	if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
		return -1;

	if (IS_ENABLED(CONFIG_RCAR_64) &&
	    ((gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_INPUT))
		offset += 4;

	return gpio_read_bit(dr, offset, bit);
}

static int sh_gpio_get(unsigned offset)
{
	return sh_gpio_get_value(gpioc, offset);
}

static void sh_gpio_set(unsigned offset, int value)
{
	sh_gpio_set_value(gpioc, offset, value);
}

int register_pinmux(struct pinmux_info *pip)
{
	if (pip != NULL) {
		gpioc = pip;
		debug("%s deregistering\n", pip->name);
		setup_data_regs(gpioc);
	}
	return 0;
}

int unregister_pinmux(struct pinmux_info *pip)
{
	debug("%s deregistering\n", pip->name);
	if (gpioc != pip)
		return -1;

	gpioc = NULL;
	return 0;
}

int gpio_request(unsigned gpio, const char *label)
{
	sh_gpio_request(gpio);
	return 0;
}

int gpio_free(unsigned gpio)
{
	sh_gpio_free(gpio);
	return 0;
}

int gpio_direction_input(unsigned gpio)
{
	return sh_gpio_direction_input(gpio);
}

int gpio_direction_output(unsigned gpio, int value)
{
	return sh_gpio_direction_output(gpio, value);
}

void gpio_set_value(unsigned gpio, int value)
{
	sh_gpio_set(gpio, value);
}

int gpio_get_value(unsigned gpio)
{
	return sh_gpio_get(gpio);
}
Commit	Line	Data
d764c504 NI	1	/*
	2	* Pinmuxed GPIO support for SuperH.
	3	* Copy from linux kernel driver/sh/pfc.c
	4	*
	5	* Copyright (C) 2008 Magnus Damm
	6	*
	7	* This file is subject to the terms and conditions of the GNU General Public
	8	* License. See the file "COPYING" in the main directory of this archive
	9	* for more details.
	10	*/
	11
f7ae49fc	12	#include <log.h>
336d4615	13	#include <malloc.h>
d764c504 NI	14	#include <asm/bitops.h>
	15	#include <asm/io.h>
	16	#include <sh_pfc.h>
cd93d625	17	#include <linux/bitops.h>
eb41d8a1	18	#include <linux/bug.h>
d764c504 NI	19
	20	static struct pinmux_info *gpioc;
	21
	22	#define pfc_phys_to_virt(p, a) ((void *)a)
	23
	24	static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
	25	{
	26	if (enum_id < r->begin)
	27	return 0;
	28
	29	if (enum_id > r->end)
	30	return 0;
	31
	32	return 1;
	33	}
	34
	35	static unsigned long gpio_read_raw_reg(void *mapped_reg,
	36	unsigned long reg_width)
	37	{
	38	switch (reg_width) {
	39
	40	case 8:
	41	return readb(mapped_reg);
	42	case 16:
	43	return readw(mapped_reg);
	44	case 32:
	45	return readl(mapped_reg);
	46	}
	47
	48	BUG();
	49	return 0;
	50	}
	51
	52	static void gpio_write_raw_reg(void *mapped_reg,
	53	unsigned long reg_width,
	54	unsigned long data)
	55	{
	56	switch (reg_width) {
	57	case 8:
	58	writeb(data, mapped_reg);
	59	return;
	60	case 16:
	61	writew(data, mapped_reg);
	62	return;
	63	case 32:
	64	writel(data, mapped_reg);
	65	return;
	66	}
	67
	68	BUG();
	69	}
	70
	71	static int gpio_read_bit(struct pinmux_data_reg *dr,
1815c297	72	unsigned long offset,
d764c504 NI	73	unsigned long in_pos)
	74	{
	75	unsigned long pos;
	76
	77	pos = dr->reg_width - (in_pos + 1);
	78
1815c297 KA	79	debug("read_bit: addr = %lx, pos = %ld, r_width = %ld\n",
1815c297 KA	80	dr->reg + offset, pos, dr->reg_width);
d764c504	81
1815c297 KA	82	return (gpio_read_raw_reg(dr->mapped_reg + offset,
1815c297 KA	83	dr->reg_width) >> pos) & 1;
d764c504 NI	84	}
	85
	86	static void gpio_write_bit(struct pinmux_data_reg *dr,
	87	unsigned long in_pos, unsigned long value)
	88	{
	89	unsigned long pos;
	90
	91	pos = dr->reg_width - (in_pos + 1);
	92
	93	debug("write_bit addr = %lx, value = %d, pos = %ld, "
	94	"r_width = %ld\n",
	95	dr->reg, !!value, pos, dr->reg_width);
	96
	97	if (value)
	98	__set_bit(pos, &dr->reg_shadow);
	99	else
	100	__clear_bit(pos, &dr->reg_shadow);
	101
	102	gpio_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
	103	}
	104
	105	static void config_reg_helper(struct pinmux_info *gpioc,
	106	struct pinmux_cfg_reg *crp,
	107	unsigned long in_pos,
	108	#if 0
	109	void __iomem **mapped_regp,
	110	#else
	111	void **mapped_regp,
	112	#endif
	113	unsigned long *maskp,
	114	unsigned long *posp)
	115	{
	116	int k;
	117
	118	*mapped_regp = pfc_phys_to_virt(gpioc, crp->reg);
	119
	120	if (crp->field_width) {
	121	*maskp = (1 << crp->field_width) - 1;
	122	posp = crp->reg_width - ((in_pos + 1) crp->field_width);
	123	} else {
	124	*maskp = (1 << crp->var_field_width[in_pos]) - 1;
	125	*posp = crp->reg_width;
	126	for (k = 0; k <= in_pos; k++)
3e812421	127	*posp -= abs(crp->var_field_width[k]);
d764c504 NI	128	}
	129	}
	130
	131	static int read_config_reg(struct pinmux_info *gpioc,
	132	struct pinmux_cfg_reg *crp,
	133	unsigned long field)
	134	{
	135	void *mapped_reg;
	136
	137	unsigned long mask, pos;
	138
	139	config_reg_helper(gpioc, crp, field, &mapped_reg, &mask, &pos);
	140
	141	debug("read_reg: addr = %lx, field = %ld, "
	142	"r_width = %ld, f_width = %ld\n",
	143	crp->reg, field, crp->reg_width, crp->field_width);
	144
	145	return (gpio_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
	146	}
	147
	148	static void write_config_reg(struct pinmux_info *gpioc,
	149	struct pinmux_cfg_reg *crp,
	150	unsigned long field, unsigned long value)
	151	{
	152	void *mapped_reg;
	153	unsigned long mask, pos, data;
	154
	155	config_reg_helper(gpioc, crp, field, &mapped_reg, &mask, &pos);
	156
	157	debug("write_reg addr = %lx, value = %ld, field = %ld, "
	158	"r_width = %ld, f_width = %ld\n",
	159	crp->reg, value, field, crp->reg_width, crp->field_width);
	160
	161	mask = ~(mask << pos);
	162	value = value << pos;
	163
	164	data = gpio_read_raw_reg(mapped_reg, crp->reg_width);
	165	data &= mask;
	166	data \|= value;
	167
	168	if (gpioc->unlock_reg)
	169	gpio_write_raw_reg(pfc_phys_to_virt(gpioc, gpioc->unlock_reg),
	170	32, ~data);
	171
	172	gpio_write_raw_reg(mapped_reg, crp->reg_width, data);
	173	}
	174
	175	static int setup_data_reg(struct pinmux_info *gpioc, unsigned gpio)
	176	{
	177	struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
	178	struct pinmux_data_reg *data_reg;
	179	int k, n;
	180
	181	if (!enum_in_range(gpiop->enum_id, &gpioc->data))
	182	return -1;
	183
	184	k = 0;
	185	while (1) {
	186	data_reg = gpioc->data_regs + k;
	187
	188	if (!data_reg->reg_width)
	189	break;
	190
	191	data_reg->mapped_reg = pfc_phys_to_virt(gpioc, data_reg->reg);
192
193	for (n = 0; n < data_reg->reg_width; n++) {
194	if (data_reg->enum_ids[n] == gpiop->enum_id) {
195	gpiop->flags &= ~PINMUX_FLAG_DREG;
196	gpiop->flags \|= (k << PINMUX_FLAG_DREG_SHIFT);
197	gpiop->flags &= ~PINMUX_FLAG_DBIT;
198	gpiop->flags \|= (n << PINMUX_FLAG_DBIT_SHIFT);
199	return 0;
200	}
201	}
202	k++;
203	}
204
205	BUG();
206
207	return -1;
208	}
209
210	static void setup_data_regs(struct pinmux_info *gpioc)
211	{
212	struct pinmux_data_reg *drp;
213	int k;
214
215	for (k = gpioc->first_gpio; k <= gpioc->last_gpio; k++)
216	setup_data_reg(gpioc, k);
217
218	k = 0;
219	while (1) {
220	drp = gpioc->data_regs + k;
221
222	if (!drp->reg_width)
223	break;
224
225	drp->reg_shadow = gpio_read_raw_reg(drp->mapped_reg,
226	drp->reg_width);
227	k++;
228	}
229	}
230
231	static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
232	struct pinmux_data_reg *drp, int bitp)
233	{
234	struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
235	int k, n;
236
237	if (!enum_in_range(gpiop->enum_id, &gpioc->data))
238	return -1;
239
240	k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
241	n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
242	*drp = gpioc->data_regs + k;
243	*bitp = n;
244	return 0;
245	}
246
247	static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
248	struct pinmux_cfg_reg **crp,
249	int fieldp, int valuep,
250	unsigned long **cntp)
251	{
252	struct pinmux_cfg_reg *config_reg;
253	unsigned long r_width, f_width, curr_width, ncomb;
254	int k, m, n, pos, bit_pos;
255
256	k = 0;
257	while (1) {
258	config_reg = gpioc->cfg_regs + k;
259
260	r_width = config_reg->reg_width;
261	f_width = config_reg->field_width;
262
263	if (!r_width)
264	break;
265
266	pos = 0;
267	m = 0;
268	for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
269	if (f_width)
270	curr_width = f_width;
271	else
272	curr_width = config_reg->var_field_width[m];
273
274	ncomb = 1 << curr_width;
275	for (n = 0; n < ncomb; n++) {
276	if (config_reg->enum_ids[pos + n] == enum_id) {
277	*crp = config_reg;
278	*fieldp = m;
279	*valuep = n;
280	*cntp = &config_reg->cnt[m];
281	return 0;
282	}
283	}
284	pos += ncomb;
285	m++;
286	}
287	k++;
288	}
289
290	return -1;
291	}
292
293	static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio,
294	int pos, pinmux_enum_t *enum_idp)
295	{
296	pinmux_enum_t enum_id = gpioc->gpios[gpio].enum_id;
297	pinmux_enum_t *data = gpioc->gpio_data;
298	int k;
299
300	if (!enum_in_range(enum_id, &gpioc->data)) {
301	if (!enum_in_range(enum_id, &gpioc->mark)) {
302	debug("non data/mark enum_id for gpio %d\n", gpio);
303	return -1;
304	}
305	}
306
307	if (pos) {
308	*enum_idp = data[pos + 1];
309	return pos + 1;
310	}
311
312	for (k = 0; k < gpioc->gpio_data_size; k++) {
313	if (data[k] == enum_id) {
314	*enum_idp = data[k + 1];
315	return k + 1;
316	}
317	}
318
319	debug("cannot locate data/mark enum_id for gpio %d\n", gpio);
320	return -1;
321	}
322
323	enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
324
325	static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
326	int pinmux_type, int cfg_mode)
327	{
328	struct pinmux_cfg_reg *cr = NULL;
329	pinmux_enum_t enum_id;
330	struct pinmux_range *range;
331	int in_range, pos, field, value;
332	unsigned long *cntp;
333
334	switch (pinmux_type) {
335
336	case PINMUX_TYPE_FUNCTION:
337	range = NULL;
338	break;
339
340	case PINMUX_TYPE_OUTPUT:
341	range = &gpioc->output;
342	break;
343
344	case PINMUX_TYPE_INPUT:
345	range = &gpioc->input;
346	break;
347
348	case PINMUX_TYPE_INPUT_PULLUP:
349	range = &gpioc->input_pu;
350	break;
351
352	case PINMUX_TYPE_INPUT_PULLDOWN:
353	range = &gpioc->input_pd;
354	break;
355
356	default:
357	goto out_err;
358	}
359
360	pos = 0;
361	enum_id = 0;
362	field = 0;
363	value = 0;
364	while (1) {
365	pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id);
366	if (pos <= 0)
367	goto out_err;
368
369	if (!enum_id)
370	break;
371
372	/* first check if this is a function enum */
373	in_range = enum_in_range(enum_id, &gpioc->function);
374	if (!in_range) {
375	/* not a function enum */
376	if (range) {
377	/*
378	* other range exists, so this pin is
379	* a regular GPIO pin that now is being
380	* bound to a specific direction.
381	*
382	* for this case we only allow function enums
383	* and the enums that match the other range.
384	*/
385	in_range = enum_in_range(enum_id, range);
386
387	/*
388	* special case pass through for fixed
389	* input-only or output-only pins without
390	* function enum register association.
391	*/
392	if (in_range && enum_id == range->force)
393	continue;
394	} else {
395	/*
396	* no other range exists, so this pin
397	* must then be of the function type.
398	*
399	* allow function type pins to select
400	* any combination of function/in/out
401	* in their MARK lists.
402	*/
403	in_range = 1;
404	}
405	}
406
407	if (!in_range)
408	continue;
409
410	if (get_config_reg(gpioc, enum_id, &cr,
411	&field, &value, &cntp) != 0)
412	goto out_err;
413
414	switch (cfg_mode) {
415	case GPIO_CFG_DRYRUN:
416	if (!*cntp \|\|
417	(read_config_reg(gpioc, cr, field) != value))
418	continue;
419	break;
420
421	case GPIO_CFG_REQ:
422	write_config_reg(gpioc, cr, field, value);
423	cntp = cntp + 1;
424	break;
425
426	case GPIO_CFG_FREE:
427	cntp = cntp - 1;
428	break;
429	}
430	}
431
432	return 0;
433	out_err:
434	return -1;
435	}
436
437	#if 0
438	static DEFINE_SPINLOCK(gpio_lock);
439	static struct pinmux_info chip_to_pinmux(struct gpio_chip chip)
440	{
441	return container_of(chip, struct pinmux_info, chip);
442	}
443	#endif
444
445	static int sh_gpio_request(unsigned offset)
446	{
447	struct pinmux_data_reg *dummy;
448	int i, ret, pinmux_type;
449
450	ret = -1;
451
452	if (!gpioc)
453	goto err_out;
454
455	if ((gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE) != PINMUX_TYPE_NONE)
456	goto err_out;
457
458	/* setup pin function here if no data is associated with pin */
459
460	if (get_data_reg(gpioc, offset, &dummy, &i) != 0)
461	pinmux_type = PINMUX_TYPE_FUNCTION;
462	else
463	pinmux_type = PINMUX_TYPE_GPIO;
464
465	if (pinmux_type == PINMUX_TYPE_FUNCTION) {
466	if (pinmux_config_gpio(gpioc, offset,
467	pinmux_type,
468	GPIO_CFG_DRYRUN) != 0)
469	goto err_out;
470
471	if (pinmux_config_gpio(gpioc, offset,
472	pinmux_type,
473	GPIO_CFG_REQ) != 0)
474	BUG();
475	}
476
477	gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
478	gpioc->gpios[offset].flags \|= pinmux_type;
479
480	ret = 0;
481	err_out:
482	return ret;
483	}
484
485	static void sh_gpio_free(unsigned offset)
486	{
487	int pinmux_type;
488
489	if (!gpioc)
490	return;
491
492	pinmux_type = gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE;
493	pinmux_config_gpio(gpioc, offset, pinmux_type, GPIO_CFG_FREE);
494	gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
495	gpioc->gpios[offset].flags \|= PINMUX_TYPE_NONE;
496	}
497
498	static int pinmux_direction(struct pinmux_info *gpioc,
499	unsigned gpio, int new_pinmux_type)
500	{
501	int pinmux_type;
502	int ret = -1;
503
504	if (!gpioc)
505	goto err_out;
506
507	pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;
508
509	switch (pinmux_type) {
510	case PINMUX_TYPE_GPIO:
511	break;
512	case PINMUX_TYPE_OUTPUT:
513	case PINMUX_TYPE_INPUT:
514	case PINMUX_TYPE_INPUT_PULLUP:
515	case PINMUX_TYPE_INPUT_PULLDOWN:
516	pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE);
517	break;
518	default:
519	goto err_out;
520	}
521
522	if (pinmux_config_gpio(gpioc, gpio,
523	new_pinmux_type,
524	GPIO_CFG_DRYRUN) != 0)
525	goto err_out;
526
527	if (pinmux_config_gpio(gpioc, gpio,
528	new_pinmux_type,
529	GPIO_CFG_REQ) != 0)
530	BUG();
531
532	gpioc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
533	gpioc->gpios[gpio].flags \|= new_pinmux_type;
534
535	ret = 0;
536	err_out:
537	return ret;
538	}
539
540	static int sh_gpio_direction_input(unsigned offset)
541	{
542	return pinmux_direction(gpioc, offset, PINMUX_TYPE_INPUT);
543	}
544
545	static void sh_gpio_set_value(struct pinmux_info *gpioc,
546	unsigned gpio, int value)
547	{
548	struct pinmux_data_reg *dr = NULL;
549	int bit = 0;
550
551	if (!gpioc \|\| get_data_reg(gpioc, gpio, &dr, &bit) != 0)
552	BUG();
553	else
554	gpio_write_bit(dr, bit, value);
555	}
556
557	static int sh_gpio_direction_output(unsigned offset, int value)
558	{
559	sh_gpio_set_value(gpioc, offset, value);
560	return pinmux_direction(gpioc, offset, PINMUX_TYPE_OUTPUT);
561	}
562
563	static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio)
564	{
565	struct pinmux_data_reg *dr = NULL;
1815c297	566	int bit = 0, offset = 0;
d764c504 NI	567
	568	if (!gpioc \|\| get_data_reg(gpioc, gpio, &dr, &bit) != 0)
	569	return -1;
517f8e8a	570
1b1834c0	571	if (IS_ENABLED(CONFIG_RCAR_64) &&
517f8e8a	572	((gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_INPUT))
1815c297	573	offset += 4;
d764c504	574
1815c297	575	return gpio_read_bit(dr, offset, bit);
d764c504 NI	576	}
	577
	578	static int sh_gpio_get(unsigned offset)
	579	{
	580	return sh_gpio_get_value(gpioc, offset);
	581	}
	582
	583	static void sh_gpio_set(unsigned offset, int value)
	584	{
	585	sh_gpio_set_value(gpioc, offset, value);
	586	}
	587
	588	int register_pinmux(struct pinmux_info *pip)
	589	{
	590	if (pip != NULL) {
	591	gpioc = pip;
	592	debug("%s deregistering\n", pip->name);
	593	setup_data_regs(gpioc);
	594	}
	595	return 0;
	596	}
	597
	598	int unregister_pinmux(struct pinmux_info *pip)
	599	{
	600	debug("%s deregistering\n", pip->name);
	601	if (gpioc != pip)
	602	return -1;
	603
	604	gpioc = NULL;
	605	return 0;
	606	}
	607
	608	int gpio_request(unsigned gpio, const char *label)
	609	{
	610	sh_gpio_request(gpio);
	611	return 0;
	612	}
	613
	614	int gpio_free(unsigned gpio)
	615	{
	616	sh_gpio_free(gpio);
	617	return 0;
	618	}
	619
	620	int gpio_direction_input(unsigned gpio)
	621	{
	622	return sh_gpio_direction_input(gpio);
	623	}
	624
	625	int gpio_direction_output(unsigned gpio, int value)
	626	{
	627	return sh_gpio_direction_output(gpio, value);
	628	}
	629
	630	void gpio_set_value(unsigned gpio, int value)
	631	{
	632	sh_gpio_set(gpio, value);
	633	}
	634
	635	int gpio_get_value(unsigned gpio)
	636	{
	637	return sh_gpio_get(gpio);
	638	}