[J-u-boot.git] / include / configs / ge_bx50v3.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2015 Timesys Corporation
 * Copyright (C) 2015 General Electric Company
 * Copyright (C) 2014 Advantech
 * Copyright (C) 2012 Freescale Semiconductor, Inc.
 *
 * Configuration settings for the GE MX6Q Bx50v3 boards.
 */

#ifndef __GE_BX50V3_CONFIG_H
#define __GE_BX50V3_CONFIG_H

#include <asm/arch/imx-regs.h>
#include <asm/mach-imx/gpio.h>

#define CONFIG_BOARD_NAME	"General Electric Bx50v3"

#define CONFIG_MXC_UART_BASE	UART3_BASE
#define CONSOLE_DEV	"ttymxc2"

#define CONFIG_SUPPORT_EMMC_BOOT


#include "mx6_common.h"
#include <linux/sizes.h>

#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SYS_MALLOC_LEN		(10 * SZ_1M)

#define CONFIG_HW_WATCHDOG
#define CONFIG_IMX_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 6000

#define CONFIG_MXC_UART

#define CONFIG_MXC_OCOTP

/* SATA Configs */
#ifdef CONFIG_CMD_SATA
#define CONFIG_SYS_SATA_MAX_DEVICE	1
#define CONFIG_DWC_AHSATA_PORT_ID	0
#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
#endif

/* MMC Configs */
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR      0

/* USB Configs */
#ifdef CONFIG_USB
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS	0

#define CONFIG_USBD_HS
#define CONFIG_USB_GADGET_MASS_STORAGE
#endif

/* Networking Configs */
#ifdef CONFIG_NET
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE			ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE		RGMII
#define CONFIG_ETHPRIME		"FEC"
#define CONFIG_FEC_MXC_PHYADDR		4
#define CONFIG_PHY_ATHEROS
#endif

/* Serial Flash */
#ifdef CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_BUS		0
#define CONFIG_SF_DEFAULT_CS		0
#define CONFIG_SF_DEFAULT_SPEED	20000000
#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
#endif

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_LOADADDR	0x12000000

#define CONFIG_EXTRA_ENV_SETTINGS \
	"bootcause=POR\0" \
	"bootlimit=10\0" \
	"image=/boot/fitImage\0" \
	"fdt_high=0xffffffff\0" \
	"dev=mmc\0" \
	"devnum=1\0" \
	"rootdev=mmcblk0p\0" \
	"quiet=quiet loglevel=0\0" \
	"console=" CONSOLE_DEV "\0" \
	"setargs=setenv bootargs root=/dev/${rootdev}${partnum} " \
		"ro rootwait cma=128M " \
		"bootcause=${bootcause} " \
		"${quiet} console=${console} ${rtc_status} " \
		"${videoargs}" "\0" \
	"doquiet=" \
		"if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \
			"then setenv quiet; fi\0" \
	"hasfirstboot=" \
		"ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \
		"/boot/bootcause/firstboot\0" \
	"swappartitions=" \
		"setexpr partnum 3 - ${partnum}\0" \
	"failbootcmd=" \
		"bx50_backlight_enable; " \
		"msg=\"Monitor failed to start.  Try again, or contact GE Service for support.\"; " \
		"echo $msg; " \
		"setenv stdout vga; " \
		"echo \"\n\n\n\n    \" $msg; " \
		"setenv stdout serial; " \
		"mw.b 0x7000A000 0xbc; " \
		"mw.b 0x7000A001 0x00; " \
		"ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \
	"altbootcmd=" \
		"run doquiet; " \
		"setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
		"run hasfirstboot || setenv partnum 0; " \
		"if test ${partnum} != 0; then " \
			"setenv bootcause REVERT; " \
			"run swappartitions loadimage doboot; " \
		"fi; " \
		"run failbootcmd\0" \
	"loadimage=" \
		"ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
	"doboot=" \
		"echo Booting from ${dev}:${devnum}:${partnum} ...; " \
		"run setargs; " \
		"bootm ${loadaddr}#conf@${confidx}\0" \
	"tryboot=" \
		"setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
		"run loadimage || run swappartitions && run loadimage || " \
		"setenv partnum 0 && echo MISSING IMAGE;" \
		"run doboot; " \
		"run failbootcmd\0" \

#define CONFIG_MMCBOOTCOMMAND \
	"if mmc dev ${devnum}; then " \
		"run doquiet; " \
		"run tryboot; " \
	"fi; " \

#define CONFIG_USBBOOTCOMMAND \
	"echo Unsupported; " \

#ifdef CONFIG_CMD_USB
#define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND
#else
#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
#endif

#define CONFIG_ARP_TIMEOUT     200UL

/* Miscellaneous configurable options */

#define CONFIG_SYS_MEMTEST_START       0x10000000
#define CONFIG_SYS_MEMTEST_END         0x10010000
#define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000

#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR

/* Physical Memory Map */
#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR

#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

/* environment organization */
#define CONFIG_ENV_SIZE		(8 * 1024)
#define CONFIG_ENV_OFFSET		(768 * 1024)
#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
#define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
#define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
#define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED

#define CONFIG_SYS_FSL_USDHC_NUM	3

/* Framebuffer */
#define CONFIG_VIDEO
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SYS_CONSOLE_FG_COL 0xFF
#define CONFIG_SYS_CONSOLE_BG_COL 0x00
#define CONFIG_HIDE_LOGO_VERSION
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
#define CONFIG_CMD_BMP
#endif

#define CONFIG_PWM_IMX
#define CONFIG_IMX6_PWM_PER_CLK	66000000

#define CONFIG_PCI
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_PCIE_IMX
#define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(7, 12)
#define CONFIG_PCIE_IMX_POWER_GPIO	IMX_GPIO_NR(1, 5)

#define CONFIG_RTC_RX8010SJ
#define CONFIG_SYS_RTC_BUS_NUM 2
#define CONFIG_SYS_I2C_RTC_ADDR	0x32

/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_SPEED		  100000
#define CONFIG_SYS_I2C_MXC_I2C1
#define CONFIG_SYS_I2C_MXC_I2C2
#define CONFIG_SYS_I2C_MXC_I2C3

#define CONFIG_SYS_NUM_I2C_BUSES        11
#define CONFIG_SYS_I2C_MAX_HOPS         1
#define CONFIG_SYS_I2C_BUSES	{	{0, {I2C_NULL_HOP} }, \
					{1, {I2C_NULL_HOP} }, \
					{2, {I2C_NULL_HOP} }, \
					{0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \
					{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
					{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
					{0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
					{0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
					{0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
					{0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \
					{0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \
				}

#define CONFIG_BCH

#endif	/* __GE_BX50V3_CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
f9162b15 AB	2	/*
	3	* Copyright (C) 2015 Timesys Corporation
	4	* Copyright (C) 2015 General Electric Company
	5	* Copyright (C) 2014 Advantech
	6	* Copyright (C) 2012 Freescale Semiconductor, Inc.
	7	*
	8	* Configuration settings for the GE MX6Q Bx50v3 boards.
f9162b15 AB	9	*/
	10
	11	#ifndef __GE_BX50V3_CONFIG_H
	12	#define __GE_BX50V3_CONFIG_H
	13
	14	#include <asm/arch/imx-regs.h>
552a848e	15	#include <asm/mach-imx/gpio.h>
f9162b15	16
51a42bea	17	#define CONFIG_BOARD_NAME "General Electric Bx50v3"
f9162b15 AB	18
f9162b15 AB	19	#define CONFIG_MXC_UART_BASE UART3_BASE
12ca05a3	20	#define CONSOLE_DEV "ttymxc2"
f9162b15	21
f9162b15 AB	22	#define CONFIG_SUPPORT_EMMC_BOOT
f9162b15 AB	23
f9162b15 AB	24
	25	#include "mx6_common.h"
	26	#include <linux/sizes.h>
	27
f9162b15 AB	28	#define CONFIG_CMDLINE_TAG
	29	#define CONFIG_SETUP_MEMORY_TAGS
	30	#define CONFIG_INITRD_TAG
	31	#define CONFIG_REVISION_TAG
	32	#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
	33
6d656495 MW	34	#define CONFIG_HW_WATCHDOG
	35	#define CONFIG_IMX_WATCHDOG
	36	#define CONFIG_WATCHDOG_TIMEOUT_MSECS 6000
	37
f9162b15 AB	38	#define CONFIG_MXC_UART
f9162b15 AB	39
f9162b15 AB	40	#define CONFIG_MXC_OCOTP
	41
	42	/* SATA Configs */
aacc10c5	43	#ifdef CONFIG_CMD_SATA
f9162b15 AB	44	#define CONFIG_SYS_SATA_MAX_DEVICE 1
	45	#define CONFIG_DWC_AHSATA_PORT_ID 0
	46	#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
	47	#define CONFIG_LBA48
aacc10c5	48	#endif
f9162b15 AB	49
f9162b15 AB	50	/* MMC Configs */
f9162b15 AB	51	#define CONFIG_FSL_USDHC
f9162b15 AB	52	#define CONFIG_SYS_FSL_ESDHC_ADDR 0
f9162b15 AB	53
f9162b15 AB	54	/* USB Configs */
fc44902a	55	#ifdef CONFIG_USB
f9162b15 AB	56	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
	57	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
	58	#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI \| PORT_PTS_PTW)
	59	#define CONFIG_MXC_USB_FLAGS 0
f9162b15	60
f9162b15	61	#define CONFIG_USBD_HS
f9162b15	62	#define CONFIG_USB_GADGET_MASS_STORAGE
fc44902a	63	#endif
f9162b15 AB	64
f9162b15 AB	65	/* Networking Configs */
c26ffd9b	66	#ifdef CONFIG_NET
f9162b15	67	#define CONFIG_FEC_MXC
f9162b15 AB	68	#define IMX_FEC_BASE ENET_BASE_ADDR
	69	#define CONFIG_FEC_XCV_TYPE RGMII
	70	#define CONFIG_ETHPRIME "FEC"
	71	#define CONFIG_FEC_MXC_PHYADDR 4
f9162b15	72	#define CONFIG_PHY_ATHEROS
c26ffd9b	73	#endif
f9162b15 AB	74
f9162b15 AB	75	/* Serial Flash */
f9162b15	76	#ifdef CONFIG_CMD_SF
f9162b15 AB	77	#define CONFIG_SF_DEFAULT_BUS 0
	78	#define CONFIG_SF_DEFAULT_CS 0
	79	#define CONFIG_SF_DEFAULT_SPEED 20000000
	80	#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
	81	#endif
	82
	83	/* allow to overwrite serial and ethaddr */
	84	#define CONFIG_ENV_OVERWRITE
f9162b15	85
f9162b15	86	#define CONFIG_LOADADDR 0x12000000
f9162b15 AB	87
f9162b15 AB	88	#define CONFIG_EXTRA_ENV_SETTINGS \
9e41b54a	89	"bootcause=POR\0" \
44395c85	90	"bootlimit=10\0" \
f07b3148	91	"image=/boot/fitImage\0" \
9e41b54a IR	92	"fdt_high=0xffffffff\0" \
	93	"dev=mmc\0" \
	94	"devnum=1\0" \
	95	"rootdev=mmcblk0p\0" \
	96	"quiet=quiet loglevel=0\0" \
12ca05a3	97	"console=" CONSOLE_DEV "\0" \
9e41b54a IR	98	"setargs=setenv bootargs root=/dev/${rootdev}${partnum} " \
	99	"ro rootwait cma=128M " \
	100	"bootcause=${bootcause} " \
886678fc	101	"${quiet} console=${console} ${rtc_status} " \
06a3e438	102	"${videoargs}" "\0" \
9e41b54a IR	103	"doquiet=" \
	104	"if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \
	105	"then setenv quiet; fi\0" \
	106	"hasfirstboot=" \
	107	"ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \
	108	"/boot/bootcause/firstboot\0" \
	109	"swappartitions=" \
	110	"setexpr partnum 3 - ${partnum}\0" \
	111	"failbootcmd=" \
6c0e6b45	112	"bx50_backlight_enable; " \
9e41b54a IR	113	"msg=\"Monitor failed to start. Try again, or contact GE Service for support.\"; " \
	114	"echo $msg; " \
	115	"setenv stdout vga; " \
	116	"echo \"\n\n\n\n \" $msg; " \
	117	"setenv stdout serial; " \
	118	"mw.b 0x7000A000 0xbc; " \
	119	"mw.b 0x7000A001 0x00; " \
	120	"ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \
	121	"altbootcmd=" \
	122	"run doquiet; " \
	123	"setenv partnum 1; run hasfirstboot \|\| setenv partnum 2; " \
	124	"run hasfirstboot \|\| setenv partnum 0; " \
	125	"if test ${partnum} != 0; then " \
	126	"setenv bootcause REVERT; " \
	127	"run swappartitions loadimage doboot; " \
	128	"fi; " \
	129	"run failbootcmd\0" \
f9162b15 AB	130	"loadimage=" \
f9162b15 AB	131	"ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
9e41b54a IR	132	"doboot=" \
9e41b54a IR	133	"echo Booting from ${dev}:${devnum}:${partnum} ...; " \
f9162b15	134	"run setargs; " \
9e41b54a IR	135	"bootm ${loadaddr}#conf@${confidx}\0" \
	136	"tryboot=" \
	137	"setenv partnum 1; run hasfirstboot \|\| setenv partnum 2; " \
	138	"run loadimage \|\| run swappartitions && run loadimage \|\| " \
	139	"setenv partnum 0 && echo MISSING IMAGE;" \
	140	"run doboot; " \
	141	"run failbootcmd\0" \
f9162b15	142
fc44902a	143	#define CONFIG_MMCBOOTCOMMAND \
f9162b15	144	"if mmc dev ${devnum}; then " \
9e41b54a	145	"run doquiet; " \
f9162b15 AB	146	"run tryboot; " \
f9162b15 AB	147	"fi; " \
fc44902a AS	148
fc44902a AS	149	#define CONFIG_USBBOOTCOMMAND \
f07b3148	150	"echo Unsupported; " \
f9162b15	151
fc44902a AS	152	#ifdef CONFIG_CMD_USB
	153	#define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND
	154	#else
	155	#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
	156	#endif
	157
f9162b15 AB	158	#define CONFIG_ARP_TIMEOUT 200UL
	159
	160	/* Miscellaneous configurable options */
f9162b15	161
f9162b15 AB	162	#define CONFIG_SYS_MEMTEST_START 0x10000000
	163	#define CONFIG_SYS_MEMTEST_END 0x10010000
	164	#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
	165
	166	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
	167
f9162b15	168	/* Physical Memory Map */
f9162b15 AB	169	#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
	170
	171	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
	172	#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
	173	#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
	174
	175	#define CONFIG_SYS_INIT_SP_OFFSET \
	176	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	177	#define CONFIG_SYS_INIT_SP_ADDR \
	178	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	179
e856bdcf	180	/* environment organization */
f9162b15 AB	181	#define CONFIG_ENV_SIZE (8 * 1024)
	182	#define CONFIG_ENV_OFFSET (768 * 1024)
	183	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
	184	#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
	185	#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
	186	#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
	187	#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
	188
f9162b15 AB	189	#define CONFIG_SYS_FSL_USDHC_NUM 3
	190
	191	/* Framebuffer */
9e41b54a	192	#define CONFIG_VIDEO
07aa030a	193	#ifdef CONFIG_VIDEO
f9162b15	194	#define CONFIG_VIDEO_IPUV3
9e41b54a IR	195	#define CONFIG_CFB_CONSOLE
	196	#define CONFIG_VGA_AS_SINGLE_DEVICE
	197	#define CONFIG_SYS_CONSOLE_FG_COL 0xFF
	198	#define CONFIG_SYS_CONSOLE_BG_COL 0x00
	199	#define CONFIG_HIDE_LOGO_VERSION
f9162b15 AB	200	#define CONFIG_IMX_HDMI
f9162b15 AB	201	#define CONFIG_IMX_VIDEO_SKIP
9e41b54a	202	#define CONFIG_CMD_BMP
07aa030a	203	#endif
f9162b15	204
54971ac6 AB	205	#define CONFIG_PWM_IMX
	206	#define CONFIG_IMX6_PWM_PER_CLK 66000000
	207
3414913c IR	208	#define CONFIG_PCI
3414913c IR	209	#define CONFIG_PCI_PNP
f9162b15 AB	210	#define CONFIG_PCI_SCAN_SHOW
	211	#define CONFIG_PCIE_IMX
	212	#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
	213	#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5)
f9162b15	214
886678fc NH	215	#define CONFIG_RTC_RX8010SJ
	216	#define CONFIG_SYS_RTC_BUS_NUM 2
	217	#define CONFIG_SYS_I2C_RTC_ADDR 0x32
	218
f9162b15	219	/* I2C Configs */
f9162b15 AB	220	#define CONFIG_SYS_I2C
	221	#define CONFIG_SYS_I2C_MXC
	222	#define CONFIG_SYS_I2C_SPEED 100000
	223	#define CONFIG_SYS_I2C_MXC_I2C1
	224	#define CONFIG_SYS_I2C_MXC_I2C2
	225	#define CONFIG_SYS_I2C_MXC_I2C3
	226
87da89e8	227	#define CONFIG_SYS_NUM_I2C_BUSES 11
be2808c3 IR	228	#define CONFIG_SYS_I2C_MAX_HOPS 1
be2808c3 IR	229	#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
87da89e8 MW	230	{1, {I2C_NULL_HOP} }, \
87da89e8 MW	231	{2, {I2C_NULL_HOP} }, \
be2808c3 IR	232	{0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \
	233	{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
	234	{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
	235	{0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
	236	{0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
	237	{0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
	238	{0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \
	239	{0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \
	240	}
	241
	242	#define CONFIG_BCH
	243
f9162b15	244	#endif /* __GE_BX50V3_CONFIG_H */