[J-u-boot.git] / board / genesi / mx51_efikamx / efikamx.c

/*
 * Copyright (C) 2009 Freescale Semiconductor, Inc.
 * Copyright (C) 2010 Marek Vasut <[email protected]>
 * Copyright (C) 2009-2012 Genesi USA, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/iomux-mx51.h>
#include <asm/gpio.h>
#include <asm/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <power/pmic.h>
#include <fsl_pmic.h>
#include <mc13892.h>

DECLARE_GLOBAL_DATA_PTR;

/*
 * Compile-time error checking
 */
#ifndef	CONFIG_MXC_SPI
#error "CONFIG_MXC_SPI not set, this is essential for board's operation!"
#endif

/*
 * Board revisions
 *
 * Note that we get these revisions here for convenience, but we only set
 * up for the production model Smarttop (1.3) and Smartbook (2.0).
 *
 */
#define	EFIKAMX_BOARD_REV_11	0x1
#define	EFIKAMX_BOARD_REV_12	0x2
#define	EFIKAMX_BOARD_REV_13	0x3
#define	EFIKAMX_BOARD_REV_14	0x4

#define	EFIKASB_BOARD_REV_13	0x1
#define	EFIKASB_BOARD_REV_20	0x2

/*
 * Board identification
 */
static u32 get_mx_rev(void)
{
	u32 rev = 0;
	/*
	 * Retrieve board ID:
	 *
	 *  gpio: 16 17 11
	 *  ==============
	 *	r1.1:  1+ 1  1
	 *	r1.2:  1  1  0
	 *	r1.3:  1  0  1
	 *	r1.4:  1  0  0
	 *
	 * + note: r1.1 does not strap this pin properly so it needs to
	 *         be hacked or ignored.
	 */

	/* set to 1 in order to get correct value on board rev 1.1 */
	gpio_direction_output(IMX_GPIO_NR(3, 16), 1);
	gpio_direction_input(IMX_GPIO_NR(3, 11));
	gpio_direction_input(IMX_GPIO_NR(3, 16));
	gpio_direction_input(IMX_GPIO_NR(3, 17));

	rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 16))) << 0;
	rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 17))) << 1;
	rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 11))) << 2;

	return (~rev & 0x7) + 1;
}

static iomux_v3_cfg_t const efikasb_revision_pads[] = {
	MX51_PAD_EIM_CS3__GPIO2_28,
	MX51_PAD_EIM_CS4__GPIO2_29,
};

static inline u32 get_sb_rev(void)
{
	u32 rev = 0;

	imx_iomux_v3_setup_multiple_pads(efikasb_revision_pads,
				ARRAY_SIZE(efikasb_revision_pads));
	gpio_direction_input(IMX_GPIO_NR(2, 28));
	gpio_direction_input(IMX_GPIO_NR(2, 29));

	rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 28))) << 0;
	rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 29))) << 1;

	return rev;
}

inline uint32_t get_efikamx_rev(void)
{
	if (machine_is_efikamx())
		return get_mx_rev();
	else if (machine_is_efikasb())
		return get_sb_rev();
}

u32 get_board_rev(void)
{
	return get_cpu_rev() | (get_efikamx_rev() << 8);
}

/*
 * DRAM initialization
 */
int dram_init(void)
{
	/* dram_init must store complete ramsize in gd->ram_size */
	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
						PHYS_SDRAM_1_SIZE);
	return 0;
}

/*
 * UART configuration
 */
static iomux_v3_cfg_t const efikamx_uart_pads[] = {
	MX51_PAD_UART1_RXD__UART1_RXD,
	MX51_PAD_UART1_TXD__UART1_TXD,
	MX51_PAD_UART1_RTS__UART1_RTS,
	MX51_PAD_UART1_CTS__UART1_CTS,
};

/*
 * SPI configuration
 */
static iomux_v3_cfg_t const efikamx_spi_pads[] = {
	MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
	MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
	MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
	MX51_PAD_CSPI1_SS0__GPIO4_24,
	MX51_PAD_CSPI1_SS1__GPIO4_25,
	MX51_PAD_GPIO1_6__GPIO1_6,
};

#define EFIKAMX_SPI_SS0		IMX_GPIO_NR(4, 24)
#define EFIKAMX_SPI_SS1		IMX_GPIO_NR(4, 25)
#define EFIKAMX_PMIC_IRQ	IMX_GPIO_NR(1, 6)

/*
 * PMIC configuration
 */
#ifdef CONFIG_MXC_SPI
static void power_init(void)
{
	unsigned int val;
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
	struct pmic *p;
	int ret;

	ret = pmic_init(CONFIG_FSL_PMIC_BUS);
	if (ret)
		return;

	p = pmic_get("FSL_PMIC");
	if (!p)
		return;

	/* Write needed to Power Gate 2 register */
	pmic_reg_read(p, REG_POWER_MISC, &val);
	val &= ~PWGT2SPIEN;
	pmic_reg_write(p, REG_POWER_MISC, val);

	/* Externally powered */
	pmic_reg_read(p, REG_CHARGE, &val);
	val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
	pmic_reg_write(p, REG_CHARGE, val);

	/* power up the system first */
	pmic_reg_write(p, REG_POWER_MISC, PWUP);

	/* Set core voltage to 1.1V */
	pmic_reg_read(p, REG_SW_0, &val);
	val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
	pmic_reg_write(p, REG_SW_0, val);

	/* Setup VCC (SW2) to 1.25 */
	pmic_reg_read(p, REG_SW_1, &val);
	val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
	pmic_reg_write(p, REG_SW_1, val);

	/* Setup 1V2_DIG1 (SW3) to 1.25 */
	pmic_reg_read(p, REG_SW_2, &val);
	val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
	pmic_reg_write(p, REG_SW_2, val);
	udelay(50);

	/* Raise the core frequency to 800MHz */
	writel(0x0, &mxc_ccm->cacrr);

	/* Set switchers in Auto in NORMAL mode & STANDBY mode */
	/* Setup the switcher mode for SW1 & SW2*/
	pmic_reg_read(p, REG_SW_4, &val);
	val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
		(SWMODE_MASK << SWMODE2_SHIFT)));
	val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
		(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
	pmic_reg_write(p, REG_SW_4, val);

	/* Setup the switcher mode for SW3 & SW4 */
	pmic_reg_read(p, REG_SW_5, &val);
	val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
		(SWMODE_MASK << SWMODE4_SHIFT)));
	val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
		(SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
	pmic_reg_write(p, REG_SW_5, val);

	/* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */
	pmic_reg_read(p, REG_SETTING_0, &val);
	val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
	val |= VDIG_1_8 | VGEN3_1_8 | VCAM_2_6;
	pmic_reg_write(p, REG_SETTING_0, val);

	/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
	pmic_reg_read(p, REG_SETTING_1, &val);
	val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
	val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775 | VGEN1_1_2 | VGEN2_3_15;
	pmic_reg_write(p, REG_SETTING_1, val);

	/* Enable VGEN1, VGEN2, VDIG, VPLL */
	pmic_reg_read(p, REG_MODE_0, &val);
	val |= VGEN1EN | VDIGEN | VGEN2EN | VPLLEN;
	pmic_reg_write(p, REG_MODE_0, val);

	/* Configure VGEN3 and VCAM regulators to use external PNP */
	val = VGEN3CONFIG | VCAMCONFIG;
	pmic_reg_write(p, REG_MODE_1, val);
	udelay(200);

	/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
	val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
		VVIDEOEN | VAUDIOEN | VSDEN;
	pmic_reg_write(p, REG_MODE_1, val);

	pmic_reg_read(p, REG_POWER_CTL2, &val);
	val |= WDIRESET;
	pmic_reg_write(p, REG_POWER_CTL2, val);

	udelay(2500);
}
#else
static inline void power_init(void) { }
#endif

/*
 * MMC configuration
 */
#ifdef CONFIG_FSL_ESDHC

struct fsl_esdhc_cfg esdhc_cfg[2] = {
	{MMC_SDHC1_BASE_ADDR},
	{MMC_SDHC2_BASE_ADDR},
};

static iomux_v3_cfg_t const efikamx_sdhc1_pads[] = {
	MX51_PAD_SD1_CMD__SD1_CMD,
	MX51_PAD_SD1_CLK__SD1_CLK,
	MX51_PAD_SD1_DATA0__SD1_DATA0,
	MX51_PAD_SD1_DATA1__SD1_DATA1,
	MX51_PAD_SD1_DATA2__SD1_DATA2,
	MX51_PAD_SD1_DATA3__SD1_DATA3,
	MX51_PAD_GPIO1_1__SD1_WP,
};

#define EFIKAMX_SDHC1_WP	IMX_GPIO_NR(1, 1)

static iomux_v3_cfg_t const efikamx_sdhc1_cd_pads[] = {
	MX51_PAD_GPIO1_0__SD1_CD,
	NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, MX51_ESDHC_PAD_CTRL),
};

#define EFIKAMX_SDHC1_CD	IMX_GPIO_NR(1, 0)
#define EFIKASB_SDHC1_CD	IMX_GPIO_NR(2, 27)

static iomux_v3_cfg_t const efikasb_sdhc2_pads[] = {
	MX51_PAD_SD2_CMD__SD2_CMD,
	MX51_PAD_SD2_CLK__SD2_CLK,
	MX51_PAD_SD2_DATA0__SD2_DATA0,
	MX51_PAD_SD2_DATA1__SD2_DATA1,
	MX51_PAD_SD2_DATA2__SD2_DATA2,
	MX51_PAD_SD2_DATA3__SD2_DATA3,
	MX51_PAD_GPIO1_7__SD2_WP,
	MX51_PAD_GPIO1_8__SD2_CD,
};

#define EFIKASB_SDHC2_CD	IMX_GPIO_NR(1, 8)
#define EFIKASB_SDHC2_WP	IMX_GPIO_NR(1, 7)

static inline uint32_t efikamx_mmc_getcd(u32 base)
{
	if (base == MMC_SDHC1_BASE_ADDR)
		if (machine_is_efikamx())
			return EFIKAMX_SDHC1_CD;
		else
			return EFIKASB_SDHC1_CD;
	else
		return EFIKASB_SDHC2_CD;
}

int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	uint32_t cd = efikamx_mmc_getcd(cfg->esdhc_base);
	int ret = !gpio_get_value(cd);

	return ret;
}

int board_mmc_init(bd_t *bis)
{
	int ret;

	/*
	 * All Efika MX boards use eSDHC1 with a common write-protect GPIO
	 */
	imx_iomux_v3_setup_multiple_pads(efikamx_sdhc1_pads,
					ARRAY_SIZE(efikamx_sdhc1_pads));
	gpio_direction_input(EFIKAMX_SDHC1_WP);

	/*
	 * Smartbook and Smarttop differ on the location of eSDHC1
	 * carrier-detect GPIO
	 */
	if (machine_is_efikamx()) {
		imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[0]);
		gpio_direction_input(EFIKAMX_SDHC1_CD);
	} else if (machine_is_efikasb()) {
		imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[1]);
		gpio_direction_input(EFIKASB_SDHC1_CD);
	}

	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);

	ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);

	if (machine_is_efikasb()) {

		imx_iomux_v3_setup_multiple_pads(efikasb_sdhc2_pads,
						ARRAY_SIZE(efikasb_sdhc2_pads));
		gpio_direction_input(EFIKASB_SDHC2_CD);
		gpio_direction_input(EFIKASB_SDHC2_WP);
		if (!ret)
			ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
	}

	return ret;
}
#endif

/*
 * PATA
 */
static iomux_v3_cfg_t const efikamx_pata_pads[] = {
	MX51_PAD_NANDF_WE_B__PATA_DIOW,
	MX51_PAD_NANDF_RE_B__PATA_DIOR,
	MX51_PAD_NANDF_ALE__PATA_BUFFER_EN,
	MX51_PAD_NANDF_CLE__PATA_RESET_B,
	MX51_PAD_NANDF_WP_B__PATA_DMACK,
	MX51_PAD_NANDF_RB0__PATA_DMARQ,
	MX51_PAD_NANDF_RB1__PATA_IORDY,
	MX51_PAD_GPIO_NAND__PATA_INTRQ,
	MX51_PAD_NANDF_CS2__PATA_CS_0,
	MX51_PAD_NANDF_CS3__PATA_CS_1,
	MX51_PAD_NANDF_CS4__PATA_DA_0,
	MX51_PAD_NANDF_CS5__PATA_DA_1,
	MX51_PAD_NANDF_CS6__PATA_DA_2,
	MX51_PAD_NANDF_D15__PATA_DATA15,
	MX51_PAD_NANDF_D14__PATA_DATA14,
	MX51_PAD_NANDF_D13__PATA_DATA13,
	MX51_PAD_NANDF_D12__PATA_DATA12,
	MX51_PAD_NANDF_D11__PATA_DATA11,
	MX51_PAD_NANDF_D10__PATA_DATA10,
	MX51_PAD_NANDF_D9__PATA_DATA9,
	MX51_PAD_NANDF_D8__PATA_DATA8,
	MX51_PAD_NANDF_D7__PATA_DATA7,
	MX51_PAD_NANDF_D6__PATA_DATA6,
	MX51_PAD_NANDF_D5__PATA_DATA5,
	MX51_PAD_NANDF_D4__PATA_DATA4,
	MX51_PAD_NANDF_D3__PATA_DATA3,
	MX51_PAD_NANDF_D2__PATA_DATA2,
	MX51_PAD_NANDF_D1__PATA_DATA1,
	MX51_PAD_NANDF_D0__PATA_DATA0,
};

/*
 * EHCI USB
 */
#ifdef	CONFIG_CMD_USB
extern void setup_iomux_usb(void);
#else
static inline void setup_iomux_usb(void) { }
#endif

/*
 * LED configuration
 *
 * Smarttop LED pad config is done in the DCD
 *
 */
#define EFIKAMX_LED_BLUE	IMX_GPIO_NR(3, 13)
#define EFIKAMX_LED_GREEN	IMX_GPIO_NR(3, 14)
#define EFIKAMX_LED_RED		IMX_GPIO_NR(3, 15)

static iomux_v3_cfg_t const efikasb_led_pads[] = {
	MX51_PAD_GPIO1_3__GPIO1_3,
	MX51_PAD_EIM_CS0__GPIO2_25,
};

#define EFIKASB_CAPSLOCK_LED	IMX_GPIO_NR(2, 25)
#define EFIKASB_MESSAGE_LED	IMX_GPIO_NR(1, 3) /* Note: active low */

/*
 * Board initialization
 */
int board_early_init_f(void)
{
	if (machine_is_efikasb()) {
		imx_iomux_v3_setup_multiple_pads(efikasb_led_pads,
						ARRAY_SIZE(efikasb_led_pads));
		gpio_direction_output(EFIKASB_CAPSLOCK_LED, 0);
		gpio_direction_output(EFIKASB_MESSAGE_LED, 1);
	} else if (machine_is_efikamx()) {
		/*
		 * Set up GPIO directions for LEDs.
		 * IOMUX has been done in the DCD already.
		 * Turn the red LED on for pre-relocation code.
		 */
		gpio_direction_output(EFIKAMX_LED_BLUE, 0);
		gpio_direction_output(EFIKAMX_LED_GREEN, 0);
		gpio_direction_output(EFIKAMX_LED_RED, 1);
	}

	/*
	 * Both these pad configurations for UART and SPI are kind of redundant
	 * since they are the Power-On Defaults for the i.MX51. But, it seems we
	 * should make absolutely sure that they are set up correctly.
	 */
	imx_iomux_v3_setup_multiple_pads(efikamx_uart_pads,
					ARRAY_SIZE(efikamx_uart_pads));
	imx_iomux_v3_setup_multiple_pads(efikamx_spi_pads,
					ARRAY_SIZE(efikamx_spi_pads));

	/* not technically required for U-Boot operation but do it anyway. */
	gpio_direction_input(EFIKAMX_PMIC_IRQ);
	/* Deselect both CS for now, otherwise NOR doesn't probe properly. */
	gpio_direction_output(EFIKAMX_SPI_SS0, 0);
	gpio_direction_output(EFIKAMX_SPI_SS1, 1);

	return 0;
}

int board_init(void)
{
	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;

	return 0;
}

int board_late_init(void)
{
	if (machine_is_efikamx()) {
		/*
		 * Set up Blue LED for "In U-Boot" status.
		 * We're all relocated and ready to U-Boot!
		 */
		gpio_set_value(EFIKAMX_LED_RED, 0);
		gpio_set_value(EFIKAMX_LED_GREEN, 0);
		gpio_set_value(EFIKAMX_LED_BLUE, 1);
	}

	power_init();

	imx_iomux_v3_setup_multiple_pads(efikamx_pata_pads,
					ARRAY_SIZE(efikamx_pata_pads));
	setup_iomux_usb();

	return 0;
}

int checkboard(void)
{
	u32 rev = get_efikamx_rev();

	printf("Board: Genesi Efika MX ");
	if (machine_is_efikamx())
		printf("Smarttop (1.%i)\n", rev & 0xf);
	else if (machine_is_efikasb())
		printf("Smartbook\n");

	return 0;
}
Commit	Line	Data
d5914017	1	/*
fdd63c93	2	* Copyright (C) 2009 Freescale Semiconductor, Inc.
d5914017	3	* Copyright (C) 2010 Marek Vasut <[email protected]>
fdd63c93	4	* Copyright (C) 2009-2012 Genesi USA, Inc.
d5914017	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
d5914017 MV	7	*/
	8
	9	#include <common.h>
	10	#include <asm/io.h>
fdd63c93	11	#include <asm/arch/iomux-mx51.h>
e70a1060	12	#include <asm/gpio.h>
d5914017 MV	13	#include <asm/errno.h>
	14	#include <asm/arch/sys_proto.h>
	15	#include <asm/arch/crm_regs.h>
a2ac1b3a	16	#include <asm/arch/clock.h>
d5914017 MV	17	#include <i2c.h>
	18	#include <mmc.h>
	19	#include <fsl_esdhc.h>
c7336815	20	#include <power/pmic.h>
d5914017 MV	21	#include <fsl_pmic.h>
	22	#include <mc13892.h>
	23
	24	DECLARE_GLOBAL_DATA_PTR;
	25
	26	/*
	27	* Compile-time error checking
	28	*/
	29	#ifndef CONFIG_MXC_SPI
	30	#error "CONFIG_MXC_SPI not set, this is essential for board's operation!"
	31	#endif
	32
	33	/*
fdd63c93 MS	34	* Board revisions
	35	*
	36	* Note that we get these revisions here for convenience, but we only set
	37	* up for the production model Smarttop (1.3) and Smartbook (2.0).
	38	*
d5914017	39	*/
d5914017 MV	40	#define EFIKAMX_BOARD_REV_11 0x1
	41	#define EFIKAMX_BOARD_REV_12 0x2
	42	#define EFIKAMX_BOARD_REV_13 0x3
	43	#define EFIKAMX_BOARD_REV_14 0x4
	44
af708cba MV	45	#define EFIKASB_BOARD_REV_13 0x1
	46	#define EFIKASB_BOARD_REV_20 0x2
	47
d5914017 MV	48	/*
	49	* Board identification
	50	*/
fdd63c93	51	static u32 get_mx_rev(void)
d5914017 MV	52	{
	53	u32 rev = 0;
	54	/*
	55	* Retrieve board ID:
fdd63c93 MS	56	*
	57	* gpio: 16 17 11
	58	* ==============
	59	* r1.1: 1+ 1 1
	60	* r1.2: 1 1 0
	61	* r1.3: 1 0 1
	62	* r1.4: 1 0 0
	63	*
	64	* + note: r1.1 does not strap this pin properly so it needs to
	65	* be hacked or ignored.
d5914017	66	*/
d5914017	67
fdd63c93	68	/* set to 1 in order to get correct value on board rev 1.1 */
ac966aac SB	69	gpio_direction_output(IMX_GPIO_NR(3, 16), 1);
	70	gpio_direction_input(IMX_GPIO_NR(3, 11));
	71	gpio_direction_input(IMX_GPIO_NR(3, 16));
	72	gpio_direction_input(IMX_GPIO_NR(3, 17));
d5914017	73
ac966aac SB	74	rev \|= (!!gpio_get_value(IMX_GPIO_NR(3, 16))) << 0;
	75	rev \|= (!!gpio_get_value(IMX_GPIO_NR(3, 17))) << 1;
	76	rev \|= (!!gpio_get_value(IMX_GPIO_NR(3, 11))) << 2;
d5914017 MV	77
	78	return (~rev & 0x7) + 1;
	79	}
	80
6e142320	81	static iomux_v3_cfg_t const efikasb_revision_pads[] = {
fdd63c93 MS	82	MX51_PAD_EIM_CS3__GPIO2_28,
	83	MX51_PAD_EIM_CS4__GPIO2_29,
	84	};
	85
	86	static inline u32 get_sb_rev(void)
af708cba MV	87	{
	88	u32 rev = 0;
	89
fdd63c93 MS	90	imx_iomux_v3_setup_multiple_pads(efikasb_revision_pads,
fdd63c93 MS	91	ARRAY_SIZE(efikasb_revision_pads));
ac966aac SB	92	gpio_direction_input(IMX_GPIO_NR(2, 28));
ac966aac SB	93	gpio_direction_input(IMX_GPIO_NR(2, 29));
af708cba	94
ac966aac SB	95	rev \|= (!!gpio_get_value(IMX_GPIO_NR(2, 28))) << 0;
ac966aac SB	96	rev \|= (!!gpio_get_value(IMX_GPIO_NR(2, 29))) << 1;
af708cba MV	97
	98	return rev;
	99	}
	100
fdd63c93	101	inline uint32_t get_efikamx_rev(void)
af708cba MV	102	{
af708cba MV	103	if (machine_is_efikamx())
fdd63c93 MS	104	return get_mx_rev();
	105	else if (machine_is_efikasb())
	106	return get_sb_rev();
af708cba MV	107	}
af708cba MV	108
d5914017 MV	109	u32 get_board_rev(void)
d5914017 MV	110	{
fdd63c93	111	return get_cpu_rev() \| (get_efikamx_rev() << 8);
d5914017 MV	112	}
	113
	114	/*
	115	* DRAM initialization
	116	*/
	117	int dram_init(void)
	118	{
	119	/* dram_init must store complete ramsize in gd->ram_size */
a55d23cc	120	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
fdd63c93	121	PHYS_SDRAM_1_SIZE);
d5914017 MV	122	return 0;
	123	}
	124
	125	/*
	126	* UART configuration
	127	*/
6e142320	128	static iomux_v3_cfg_t const efikamx_uart_pads[] = {
fdd63c93 MS	129	MX51_PAD_UART1_RXD__UART1_RXD,
	130	MX51_PAD_UART1_TXD__UART1_TXD,
	131	MX51_PAD_UART1_RTS__UART1_RTS,
	132	MX51_PAD_UART1_CTS__UART1_CTS,
	133	};
d5914017 MV	134
	135	/*
	136	* SPI configuration
	137	*/
6e142320	138	static iomux_v3_cfg_t const efikamx_spi_pads[] = {
fdd63c93 MS	139	MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
	140	MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
	141	MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
	142	MX51_PAD_CSPI1_SS0__GPIO4_24,
	143	MX51_PAD_CSPI1_SS1__GPIO4_25,
	144	MX51_PAD_GPIO1_6__GPIO1_6,
	145	};
	146
ac966aac SB	147	#define EFIKAMX_SPI_SS0 IMX_GPIO_NR(4, 24)
	148	#define EFIKAMX_SPI_SS1 IMX_GPIO_NR(4, 25)
	149	#define EFIKAMX_PMIC_IRQ IMX_GPIO_NR(1, 6)
d5914017 MV	150
	151	/*
	152	* PMIC configuration
	153	*/
	154	#ifdef CONFIG_MXC_SPI
	155	static void power_init(void)
	156	{
	157	unsigned int val;
	158	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )MXC_CCM_BASE;
9c38f7df	159	struct pmic *p;
c7336815	160	int ret;
9c38f7df	161
d74b331f	162	ret = pmic_init(CONFIG_FSL_PMIC_BUS);
c7336815 ŁM	163	if (ret)
	164	return;
	165
	166	p = pmic_get("FSL_PMIC");
	167	if (!p)
	168	return;
d5914017 MV	169
d5914017 MV	170	/* Write needed to Power Gate 2 register */
9c38f7df	171	pmic_reg_read(p, REG_POWER_MISC, &val);
d5914017	172	val &= ~PWGT2SPIEN;
9c38f7df	173	pmic_reg_write(p, REG_POWER_MISC, val);
d5914017 MV	174
d5914017 MV	175	/* Externally powered */
9c38f7df	176	pmic_reg_read(p, REG_CHARGE, &val);
d5914017	177	val \|= ICHRG0 \| ICHRG1 \| ICHRG2 \| ICHRG3 \| CHGAUTOB;
9c38f7df	178	pmic_reg_write(p, REG_CHARGE, val);
d5914017 MV	179
d5914017 MV	180	/* power up the system first */
9c38f7df	181	pmic_reg_write(p, REG_POWER_MISC, PWUP);
d5914017 MV	182
d5914017 MV	183	/* Set core voltage to 1.1V */
9c38f7df	184	pmic_reg_read(p, REG_SW_0, &val);
fdd63c93	185	val = (val & ~SWx_VOLT_MASK) \| SWx_1_100V;
9c38f7df	186	pmic_reg_write(p, REG_SW_0, val);
d5914017 MV	187
d5914017 MV	188	/* Setup VCC (SW2) to 1.25 */
9c38f7df	189	pmic_reg_read(p, REG_SW_1, &val);
d5914017	190	val = (val & ~SWx_VOLT_MASK) \| SWx_1_250V;
9c38f7df	191	pmic_reg_write(p, REG_SW_1, val);
d5914017 MV	192
d5914017 MV	193	/* Setup 1V2_DIG1 (SW3) to 1.25 */
9c38f7df	194	pmic_reg_read(p, REG_SW_2, &val);
d5914017	195	val = (val & ~SWx_VOLT_MASK) \| SWx_1_250V;
9c38f7df	196	pmic_reg_write(p, REG_SW_2, val);
d5914017 MV	197	udelay(50);
	198
	199	/* Raise the core frequency to 800MHz */
	200	writel(0x0, &mxc_ccm->cacrr);
	201
	202	/* Set switchers in Auto in NORMAL mode & STANDBY mode */
	203	/* Setup the switcher mode for SW1 & SW2*/
9c38f7df	204	pmic_reg_read(p, REG_SW_4, &val);
d5914017 MV	205	val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) \|
	206	(SWMODE_MASK << SWMODE2_SHIFT)));
	207	val \|= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) \|
	208	(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
9c38f7df	209	pmic_reg_write(p, REG_SW_4, val);
d5914017 MV	210
d5914017 MV	211	/* Setup the switcher mode for SW3 & SW4 */
9c38f7df	212	pmic_reg_read(p, REG_SW_5, &val);
d5914017 MV	213	val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) \|
	214	(SWMODE_MASK << SWMODE4_SHIFT)));
	215	val \|= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) \|
	216	(SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
9c38f7df	217	pmic_reg_write(p, REG_SW_5, val);
d5914017	218
55723954	219	/* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */
9c38f7df	220	pmic_reg_read(p, REG_SETTING_0, &val);
d5914017	221	val &= ~(VCAM_MASK \| VGEN3_MASK \| VDIG_MASK);
55723954	222	val \|= VDIG_1_8 \| VGEN3_1_8 \| VCAM_2_6;
9c38f7df	223	pmic_reg_write(p, REG_SETTING_0, val);
d5914017 MV	224
d5914017 MV	225	/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
9c38f7df	226	pmic_reg_read(p, REG_SETTING_1, &val);
d5914017	227	val &= ~(VVIDEO_MASK \| VSD_MASK \| VAUDIO_MASK);
55723954	228	val \|= VSD_3_15 \| VAUDIO_3_0 \| VVIDEO_2_775 \| VGEN1_1_2 \| VGEN2_3_15;
9c38f7df	229	pmic_reg_write(p, REG_SETTING_1, val);
d5914017	230
55723954 MV	231	/* Enable VGEN1, VGEN2, VDIG, VPLL */
	232	pmic_reg_read(p, REG_MODE_0, &val);
	233	val \|= VGEN1EN \| VDIGEN \| VGEN2EN \| VPLLEN;
	234	pmic_reg_write(p, REG_MODE_0, val);
	235
d5914017 MV	236	/* Configure VGEN3 and VCAM regulators to use external PNP */
d5914017 MV	237	val = VGEN3CONFIG \| VCAMCONFIG;
9c38f7df	238	pmic_reg_write(p, REG_MODE_1, val);
d5914017 MV	239	udelay(200);
	240
	241	/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
	242	val = VGEN3EN \| VGEN3CONFIG \| VCAMEN \| VCAMCONFIG \|
55723954	243	VVIDEOEN \| VAUDIOEN \| VSDEN;
9c38f7df	244	pmic_reg_write(p, REG_MODE_1, val);
d5914017	245
9c38f7df	246	pmic_reg_read(p, REG_POWER_CTL2, &val);
d5914017	247	val \|= WDIRESET;
9c38f7df	248	pmic_reg_write(p, REG_POWER_CTL2, val);
d5914017 MV	249
	250	udelay(2500);
	251	}
	252	#else
	253	static inline void power_init(void) { }
	254	#endif
	255
	256	/*
	257	* MMC configuration
	258	*/
	259	#ifdef CONFIG_FSL_ESDHC
fdd63c93	260
d5914017	261	struct fsl_esdhc_cfg esdhc_cfg[2] = {
16e43f35 BT	262	{MMC_SDHC1_BASE_ADDR},
16e43f35 BT	263	{MMC_SDHC2_BASE_ADDR},
d5914017 MV	264	};
d5914017 MV	265
6e142320	266	static iomux_v3_cfg_t const efikamx_sdhc1_pads[] = {
fdd63c93 MS	267	MX51_PAD_SD1_CMD__SD1_CMD,
	268	MX51_PAD_SD1_CLK__SD1_CLK,
	269	MX51_PAD_SD1_DATA0__SD1_DATA0,
	270	MX51_PAD_SD1_DATA1__SD1_DATA1,
	271	MX51_PAD_SD1_DATA2__SD1_DATA2,
	272	MX51_PAD_SD1_DATA3__SD1_DATA3,
	273	MX51_PAD_GPIO1_1__SD1_WP,
	274	};
	275
ac966aac	276	#define EFIKAMX_SDHC1_WP IMX_GPIO_NR(1, 1)
fdd63c93	277
6e142320	278	static iomux_v3_cfg_t const efikamx_sdhc1_cd_pads[] = {
fdd63c93	279	MX51_PAD_GPIO1_0__SD1_CD,
f49d92a3	280	NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, MX51_ESDHC_PAD_CTRL),
fdd63c93 MS	281	};
fdd63c93 MS	282
ac966aac SB	283	#define EFIKAMX_SDHC1_CD IMX_GPIO_NR(1, 0)
ac966aac SB	284	#define EFIKASB_SDHC1_CD IMX_GPIO_NR(2, 27)
fdd63c93	285
6e142320	286	static iomux_v3_cfg_t const efikasb_sdhc2_pads[] = {
fdd63c93 MS	287	MX51_PAD_SD2_CMD__SD2_CMD,
	288	MX51_PAD_SD2_CLK__SD2_CLK,
	289	MX51_PAD_SD2_DATA0__SD2_DATA0,
	290	MX51_PAD_SD2_DATA1__SD2_DATA1,
	291	MX51_PAD_SD2_DATA2__SD2_DATA2,
	292	MX51_PAD_SD2_DATA3__SD2_DATA3,
	293	MX51_PAD_GPIO1_7__SD2_WP,
	294	MX51_PAD_GPIO1_8__SD2_CD,
	295	};
	296
ac966aac SB	297	#define EFIKASB_SDHC2_CD IMX_GPIO_NR(1, 8)
ac966aac SB	298	#define EFIKASB_SDHC2_WP IMX_GPIO_NR(1, 7)
fdd63c93 MS	299
fdd63c93 MS	300	static inline uint32_t efikamx_mmc_getcd(u32 base)
af708cba	301	{
fdd63c93 MS	302	if (base == MMC_SDHC1_BASE_ADDR)
	303	if (machine_is_efikamx())
	304	return EFIKAMX_SDHC1_CD;
	305	else
	306	return EFIKASB_SDHC1_CD;
af708cba	307	else
fdd63c93	308	return EFIKASB_SDHC2_CD;
af708cba MV	309	}
af708cba MV	310
314284b1	311	int board_mmc_getcd(struct mmc *mmc)
d5914017 MV	312	{
d5914017 MV	313	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
fdd63c93 MS	314	uint32_t cd = efikamx_mmc_getcd(cfg->esdhc_base);
fdd63c93 MS	315	int ret = !gpio_get_value(cd);
d5914017	316
314284b1	317	return ret;
d5914017	318	}
af708cba	319
d5914017 MV	320	int board_mmc_init(bd_t *bis)
	321	{
	322	int ret;
fdd63c93 MS	323
	324	/*
	325	* All Efika MX boards use eSDHC1 with a common write-protect GPIO
	326	*/
	327	imx_iomux_v3_setup_multiple_pads(efikamx_sdhc1_pads,
	328	ARRAY_SIZE(efikamx_sdhc1_pads));
	329	gpio_direction_input(EFIKAMX_SDHC1_WP);
	330
	331	/*
	332	* Smartbook and Smarttop differ on the location of eSDHC1
	333	* carrier-detect GPIO
	334	*/
	335	if (machine_is_efikamx()) {
	336	imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[0]);
	337	gpio_direction_input(EFIKAMX_SDHC1_CD);
	338	} else if (machine_is_efikasb()) {
	339	imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[1]);
	340	gpio_direction_input(EFIKASB_SDHC1_CD);
	341	}
	342
a2ac1b3a BT	343	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
	344	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
	345
fdd63c93 MS	346	ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
	347
	348	if (machine_is_efikasb()) {
	349
	350	imx_iomux_v3_setup_multiple_pads(efikasb_sdhc2_pads,
	351	ARRAY_SIZE(efikasb_sdhc2_pads));
	352	gpio_direction_input(EFIKASB_SDHC2_CD);
	353	gpio_direction_input(EFIKASB_SDHC2_WP);
d5914017 MV	354	if (!ret)
d5914017 MV	355	ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
d5914017	356	}
af708cba	357
d5914017 MV	358	return ret;
	359	}
	360	#endif
	361
	362	/*
fdd63c93	363	* PATA
d5914017	364	*/
6e142320	365	static iomux_v3_cfg_t const efikamx_pata_pads[] = {
fdd63c93 MS	366	MX51_PAD_NANDF_WE_B__PATA_DIOW,
	367	MX51_PAD_NANDF_RE_B__PATA_DIOR,
	368	MX51_PAD_NANDF_ALE__PATA_BUFFER_EN,
	369	MX51_PAD_NANDF_CLE__PATA_RESET_B,
	370	MX51_PAD_NANDF_WP_B__PATA_DMACK,
	371	MX51_PAD_NANDF_RB0__PATA_DMARQ,
	372	MX51_PAD_NANDF_RB1__PATA_IORDY,
	373	MX51_PAD_GPIO_NAND__PATA_INTRQ,
	374	MX51_PAD_NANDF_CS2__PATA_CS_0,
	375	MX51_PAD_NANDF_CS3__PATA_CS_1,
	376	MX51_PAD_NANDF_CS4__PATA_DA_0,
	377	MX51_PAD_NANDF_CS5__PATA_DA_1,
	378	MX51_PAD_NANDF_CS6__PATA_DA_2,
	379	MX51_PAD_NANDF_D15__PATA_DATA15,
	380	MX51_PAD_NANDF_D14__PATA_DATA14,
	381	MX51_PAD_NANDF_D13__PATA_DATA13,
	382	MX51_PAD_NANDF_D12__PATA_DATA12,
	383	MX51_PAD_NANDF_D11__PATA_DATA11,
	384	MX51_PAD_NANDF_D10__PATA_DATA10,
	385	MX51_PAD_NANDF_D9__PATA_DATA9,
	386	MX51_PAD_NANDF_D8__PATA_DATA8,
	387	MX51_PAD_NANDF_D7__PATA_DATA7,
	388	MX51_PAD_NANDF_D6__PATA_DATA6,
	389	MX51_PAD_NANDF_D5__PATA_DATA5,
	390	MX51_PAD_NANDF_D4__PATA_DATA4,
	391	MX51_PAD_NANDF_D3__PATA_DATA3,
	392	MX51_PAD_NANDF_D2__PATA_DATA2,
	393	MX51_PAD_NANDF_D1__PATA_DATA1,
	394	MX51_PAD_NANDF_D0__PATA_DATA0,
	395	};
d5914017	396
d98d8bc1 MV	397	/*
	398	* EHCI USB
	399	*/
	400	#ifdef CONFIG_CMD_USB
	401	extern void setup_iomux_usb(void);
	402	#else
	403	static inline void setup_iomux_usb(void) { }
	404	#endif
	405
d5914017 MV	406	/*
d5914017 MV	407	* LED configuration
fdd63c93 MS	408	*
	409	* Smarttop LED pad config is done in the DCD
	410	*
d5914017	411	*/
ac966aac SB	412	#define EFIKAMX_LED_BLUE IMX_GPIO_NR(3, 13)
	413	#define EFIKAMX_LED_GREEN IMX_GPIO_NR(3, 14)
	414	#define EFIKAMX_LED_RED IMX_GPIO_NR(3, 15)
d5914017	415
6e142320	416	static iomux_v3_cfg_t const efikasb_led_pads[] = {
fdd63c93 MS	417	MX51_PAD_GPIO1_3__GPIO1_3,
	418	MX51_PAD_EIM_CS0__GPIO2_25,
	419	};
	420
ac966aac SB	421	#define EFIKASB_CAPSLOCK_LED IMX_GPIO_NR(2, 25)
ac966aac SB	422	#define EFIKASB_MESSAGE_LED IMX_GPIO_NR(1, 3) /* Note: active low */
d5914017 MV	423
	424	/*
	425	* Board initialization
	426	*/
d5914017 MV	427	int board_early_init_f(void)
d5914017 MV	428	{
fdd63c93 MS	429	if (machine_is_efikasb()) {
	430	imx_iomux_v3_setup_multiple_pads(efikasb_led_pads,
	431	ARRAY_SIZE(efikasb_led_pads));
	432	gpio_direction_output(EFIKASB_CAPSLOCK_LED, 0);
	433	gpio_direction_output(EFIKASB_MESSAGE_LED, 1);
	434	} else if (machine_is_efikamx()) {
	435	/*
	436	* Set up GPIO directions for LEDs.
	437	* IOMUX has been done in the DCD already.
	438	* Turn the red LED on for pre-relocation code.
	439	*/
	440	gpio_direction_output(EFIKAMX_LED_BLUE, 0);
	441	gpio_direction_output(EFIKAMX_LED_GREEN, 0);
	442	gpio_direction_output(EFIKAMX_LED_RED, 1);
	443	}
	444
	445	/*
	446	* Both these pad configurations for UART and SPI are kind of redundant
	447	* since they are the Power-On Defaults for the i.MX51. But, it seems we
	448	* should make absolutely sure that they are set up correctly.
	449	*/
	450	imx_iomux_v3_setup_multiple_pads(efikamx_uart_pads,
	451	ARRAY_SIZE(efikamx_uart_pads));
	452	imx_iomux_v3_setup_multiple_pads(efikamx_spi_pads,
	453	ARRAY_SIZE(efikamx_spi_pads));
	454
	455	/* not technically required for U-Boot operation but do it anyway. */
	456	gpio_direction_input(EFIKAMX_PMIC_IRQ);
	457	/* Deselect both CS for now, otherwise NOR doesn't probe properly. */
	458	gpio_direction_output(EFIKAMX_SPI_SS0, 0);
	459	gpio_direction_output(EFIKAMX_SPI_SS1, 1);
d5914017 MV	460
	461	return 0;
	462	}
	463
	464	int board_init(void)
	465	{
d5914017 MV	466	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
	467
	468	return 0;
	469	}
	470
	471	int board_late_init(void)
	472	{
fdd63c93 MS	473	if (machine_is_efikamx()) {
	474	/*
	475	* Set up Blue LED for "In U-Boot" status.
	476	* We're all relocated and ready to U-Boot!
	477	*/
	478	gpio_set_value(EFIKAMX_LED_RED, 0);
	479	gpio_set_value(EFIKAMX_LED_GREEN, 0);
	480	gpio_set_value(EFIKAMX_LED_BLUE, 1);
	481	}
d5914017 MV	482
	483	power_init();
	484
fdd63c93 MS	485	imx_iomux_v3_setup_multiple_pads(efikamx_pata_pads,
fdd63c93 MS	486	ARRAY_SIZE(efikamx_pata_pads));
d98d8bc1 MV	487	setup_iomux_usb();
d98d8bc1 MV	488
d5914017 MV	489	return 0;
	490	}
	491
	492	int checkboard(void)
	493	{
fdd63c93	494	u32 rev = get_efikamx_rev();
af708cba	495
fdd63c93 MS	496	printf("Board: Genesi Efika MX ");
	497	if (machine_is_efikamx())
	498	printf("Smarttop (1.%i)\n", rev & 0xf);
	499	else if (machine_is_efikasb())
	500	printf("Smartbook\n");
d5914017 MV	501
	502	return 0;
	503	}