[J-u-boot.git] / include / configs / omap3_zoom1.h

/*
 * (C) Copyright 2006-2008
 * Texas Instruments.
 * Richard Woodruff <[email protected]>
 * Syed Mohammed Khasim <[email protected]>
 * Nishanth Menon <[email protected]>
 *
 * Configuration settings for the TI OMAP3430 Zoom MDK board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_OMAP		1	/* in a TI OMAP core */
#define CONFIG_OMAP34XX		1	/* which is a 34XX */
#define CONFIG_OMAP3430		1	/* which is in a 3430 */
#define CONFIG_OMAP3_ZOOM1	1	/* working with Zoom MDK Rev1 */

#define CONFIG_SDRC	/* The chip has SDRC controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap3.h>

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO		1
#define CONFIG_DISPLAY_BOARDINFO	1

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#undef CONFIG_USE_IRQ				/* no support for IRQs */
#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1
#define CONFIG_REVISION_TAG		1

#define CONFIG_OF_LIBFDT		1

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
						/* Sector */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3	/* UART3 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}
#define CONFIG_GENERIC_MMC		1
#define CONFIG_MMC			1
#define CONFIG_OMAP_HSMMC		1
#define CONFIG_DOS_PARTITION		1

/* DDR - I use Micron DDR */
#define CONFIG_OMAP3_MICRON_DDR		1

/* USB */
#define CONFIG_MUSB_UDC			1
#define CONFIG_USB_OMAP3		1
#define CONFIG_TWL4030_USB		1

/* USB device configuration */
#define CONFIG_USB_DEVICE		1
#define CONFIG_USB_TTY			1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
/* Change these to suit your needs */
#define CONFIG_USBD_VENDORID		0x0451
#define CONFIG_USBD_PRODUCTID		0x5678
#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
#define CONFIG_USBD_PRODUCT_NAME	"Zoom1"

/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/

#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
#define CONFIG_CMD_MMC		/* MMC support			*/
#define CONFIG_CMD_NAND		/* NAND support			*/
#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */

#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
#undef CONFIG_CMD_IMI		/* iminfo			*/
#undef CONFIG_CMD_IMLS		/* List all found images	*/
#undef CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
#undef CONFIG_CMD_NFS		/* NFS support			*/

#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C			1
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		1
#define CONFIG_SYS_I2C_BUS		0
#define CONFIG_SYS_I2C_BUS_SELECT	1
#define CONFIG_DRIVER_OMAP34XX_I2C	1

/*
 * TWL4030
 */
#define CONFIG_TWL4030_POWER		1
#define CONFIG_TWL4030_LED		1

/*
 * Board NAND Info.
 */
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand at */
							/* CS0 */
#define GPMC_NAND_ECC_LP_x16_LAYOUT	1

#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
							/* devices */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV		"nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET	0x680000
#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
							/* partition */

/* Environment information */
#define CONFIG_BOOTDELAY		10

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"usbtty=cdc_acm\0" \
	"console=ttyS2,115200n8\0" \
	"mmcdev=0\0" \
	"videomode=1024x768@60,vxres=1024,vyres=768\0" \
	"videospec=omapfb:vram:2M,vram:4M\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"video=${videospec},mode:${videomode} " \
		"root=/dev/mmcblk0p2 rw " \
		"rootfstype=ext3 rootwait\0" \
	"nandargs=setenv bootargs console=${console} " \
		"video=${videospec},mode:${videomode} " \
		"root=/dev/mtdblock4 rw " \
		"rootfstype=jffs2\0" \
	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 280000 400000; " \
		"bootm ${loadaddr}\0" \

#define CONFIG_BOOTCOMMAND \
	"if mmc rescan ${mmcdev}; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loaduimage; then " \
				"run mmcboot; " \
			"else run nandboot; " \
			"fi; " \
		"fi; " \
	"else run nandboot; fi"

#define CONFIG_AUTO_COMPLETE		1
/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_SYS_PROMPT		"OMAP3 Zoom1 # "
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
								/* works on */
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
							/* load address */

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)
/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ			1000

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
#endif

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/* SDRAM Bank Allocation method */
#define SDRC_R_B_C		1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */

/* Configure the PISMO */
#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
#endif

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP

#define CONFIG_ENV_IS_IN_NAND		1
#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */

#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

#endif				/* __CONFIG_H */
Commit	Line	Data
7379f45a DB	1	/*
	2	* (C) Copyright 2006-2008
	3	* Texas Instruments.
	4	* Richard Woodruff <[email protected]>
	5	* Syed Mohammed Khasim <[email protected]>
	6	* Nishanth Menon <[email protected]>
	7	*
	8	* Configuration settings for the TI OMAP3430 Zoom MDK board.
	9	*
	10	* See file CREDITS for list of people who contributed to this
	11	* project.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28
	29	#ifndef __CONFIG_H
	30	#define __CONFIG_H
7379f45a DB	31
	32	/*
	33	* High Level Configuration Options
	34	*/
7379f45a DB	35	#define CONFIG_OMAP 1 /* in a TI OMAP core */
	36	#define CONFIG_OMAP34XX 1 /* which is a 34XX */
	37	#define CONFIG_OMAP3430 1 /* which is in a 3430 */
	38	#define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */
	39
cae377b5 VH	40	#define CONFIG_SDRC /* The chip has SDRC controller */
cae377b5 VH	41
7379f45a DB	42	#include <asm/arch/cpu.h> /* get chip and board defs */
	43	#include <asm/arch/omap3.h>
	44
6a6b62e3 SP	45	/*
	46	* Display CPU and Board information
	47	*/
	48	#define CONFIG_DISPLAY_CPUINFO 1
	49	#define CONFIG_DISPLAY_BOARDINFO 1
	50
7379f45a DB	51	/* Clock Defines */
	52	#define V_OSCK 26000000 /* Clock output from T2 */
	53	#define V_SCLK (V_OSCK >> 1)
	54
	55	#undef CONFIG_USE_IRQ /* no support for IRQs */
	56	#define CONFIG_MISC_INIT_R
	57
	58	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	59	#define CONFIG_SETUP_MEMORY_TAGS 1
	60	#define CONFIG_INITRD_TAG 1
	61	#define CONFIG_REVISION_TAG 1
	62
2fa8ca98 GL	63	#define CONFIG_OF_LIBFDT 1
2fa8ca98 GL	64
7379f45a DB	65	/*
	66	* Size of malloc() pool
	67	*/
9c44ddcc	68	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
7379f45a	69	/* Sector */
9c44ddcc	70	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
7379f45a DB	71
	72	/*
	73	* Hardware drivers
	74	*/
	75
	76	/*
	77	* NS16550 Configuration
	78	*/
	79	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	80
	81	#define CONFIG_SYS_NS16550
	82	#define CONFIG_SYS_NS16550_SERIAL
	83	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	84	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	85
	86	/*
	87	* select serial console configuration
	88	*/
	89	#define CONFIG_CONS_INDEX 3
	90	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	91	#define CONFIG_SERIAL3 3 /* UART3 */
	92
	93	/* allow to overwrite serial and ethaddr */
	94	#define CONFIG_ENV_OVERWRITE
	95	#define CONFIG_BAUDRATE 115200
	96	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	97	115200}
d6906cb8	98	#define CONFIG_GENERIC_MMC 1
7379f45a	99	#define CONFIG_MMC 1
d6906cb8	100	#define CONFIG_OMAP_HSMMC 1
7379f45a DB	101	#define CONFIG_DOS_PARTITION 1
7379f45a DB	102
30563a04 NM	103	/* DDR - I use Micron DDR */
	104	#define CONFIG_OMAP3_MICRON_DDR 1
	105
05be5a60 TR	106	/* USB */
	107	#define CONFIG_MUSB_UDC 1
	108	#define CONFIG_USB_OMAP3 1
	109	#define CONFIG_TWL4030_USB 1
	110
	111	/* USB device configuration */
	112	#define CONFIG_USB_DEVICE 1
	113	#define CONFIG_USB_TTY 1
	114	#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
	115	/* Change these to suit your needs */
	116	#define CONFIG_USBD_VENDORID 0x0451
	117	#define CONFIG_USBD_PRODUCTID 0x5678
	118	#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
	119	#define CONFIG_USBD_PRODUCT_NAME "Zoom1"
	120
7379f45a DB	121	/* commands to include */
	122	#include <config_cmd_default.h>
	123
	124	#define CONFIG_CMD_EXT2 /* EXT2 Support */
	125	#define CONFIG_CMD_FAT /* FAT support */
	126	#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
	127
	128	#define CONFIG_CMD_I2C /* I2C serial bus support */
	129	#define CONFIG_CMD_MMC /* MMC support */
	130	#define CONFIG_CMD_NAND /* NAND support */
e7deec1b	131	#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
7379f45a DB	132
	133	#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
	134	#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
	135	#undef CONFIG_CMD_IMI /* iminfo */
	136	#undef CONFIG_CMD_IMLS /* List all found images */
	137	#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
	138	#undef CONFIG_CMD_NFS /* NFS support */
	139
	140	#define CONFIG_SYS_NO_FLASH
0297ec7e	141	#define CONFIG_HARD_I2C 1
7379f45a DB	142	#define CONFIG_SYS_I2C_SPEED 100000
	143	#define CONFIG_SYS_I2C_SLAVE 1
	144	#define CONFIG_SYS_I2C_BUS 0
	145	#define CONFIG_SYS_I2C_BUS_SELECT 1
	146	#define CONFIG_DRIVER_OMAP34XX_I2C 1
	147
cd782635 TR	148	/*
	149	* TWL4030
	150	*/
	151	#define CONFIG_TWL4030_POWER 1
2c155130	152	#define CONFIG_TWL4030_LED 1
cd782635	153
7379f45a DB	154	/*
	155	* Board NAND Info.
	156	*/
	157	#define CONFIG_NAND_OMAP_GPMC
	158	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	159	/* to access nand */
	160	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	161	/* to access nand at */
	162	/* CS0 */
	163	#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
	164
	165	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
	166	/* devices */
7379f45a DB	167	#define CONFIG_JFFS2_NAND
	168	/* nand device jffs2 lives on */
	169	#define CONFIG_JFFS2_DEV "nand0"
	170	/* start of jffs2 partition */
	171	#define CONFIG_JFFS2_PART_OFFSET 0x680000
	172	#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
	173	/* partition */
	174
	175	/* Environment information */
	176	#define CONFIG_BOOTDELAY 10
	177
	178	#define CONFIG_EXTRA_ENV_SETTINGS \
	179	"loadaddr=0x82000000\0" \
05be5a60	180	"usbtty=cdc_acm\0" \
7379f45a	181	"console=ttyS2,115200n8\0" \
d6906cb8	182	"mmcdev=0\0" \
7379f45a DB	183	"videomode=1024x768@60,vxres=1024,vyres=768\0" \
	184	"videospec=omapfb:vram:2M,vram:4M\0" \
	185	"mmcargs=setenv bootargs console=${console} " \
	186	"video=${videospec},mode:${videomode} " \
	187	"root=/dev/mmcblk0p2 rw " \
	188	"rootfstype=ext3 rootwait\0" \
	189	"nandargs=setenv bootargs console=${console} " \
	190	"video=${videospec},mode:${videomode} " \
	191	"root=/dev/mtdblock4 rw " \
	192	"rootfstype=jffs2\0" \
d6906cb8	193	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
7379f45a	194	"bootscript=echo Running bootscript from mmc ...; " \
74de7aef	195	"source ${loadaddr}\0" \
d6906cb8	196	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
7379f45a DB	197	"mmcboot=echo Booting from mmc ...; " \
	198	"run mmcargs; " \
	199	"bootm ${loadaddr}\0" \
	200	"nandboot=echo Booting from nand ...; " \
	201	"run nandargs; " \
	202	"nand read ${loadaddr} 280000 400000; " \
	203	"bootm ${loadaddr}\0" \
	204
	205	#define CONFIG_BOOTCOMMAND \
d6906cb8	206	"if mmc rescan ${mmcdev}; then " \
7379f45a DB	207	"if run loadbootscript; then " \
	208	"run bootscript; " \
	209	"else " \
	210	"if run loaduimage; then " \
	211	"run mmcboot; " \
	212	"else run nandboot; " \
	213	"fi; " \
	214	"fi; " \
	215	"else run nandboot; fi"
	216
	217	#define CONFIG_AUTO_COMPLETE 1
	218	/*
	219	* Miscellaneous configurable options
	220	*/
7379f45a DB	221	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	222	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
	223	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
1270ec13	224	#define CONFIG_SYS_PROMPT "OMAP3 Zoom1 # "
f62b1257	225	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
7379f45a DB	226	/* Print Buffer Size */
	227	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	228	sizeof(CONFIG_SYS_PROMPT) + 16)
	229	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	230	/* Boot Argument Buffer Size */
	231	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	232
	233	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
	234	/* works on */
	235	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	236	0x01F00000) /* 31MB */
	237
7379f45a DB	238	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
	239	/* load address */
	240
25435c6c DB	241	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	242	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	243	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	244	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	245	CONFIG_SYS_INIT_RAM_SIZE - \
	246	GENERATED_GBL_DATA_SIZE)
7379f45a	247	/*
d3a513c2 MP	248	* OMAP3 has 12 GP timers, they can be driven by the system clock
	249	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	250	* This rate is divided by a local divisor.
7379f45a	251	*/
d3a513c2 MP	252	#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
	253	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
	254	#define CONFIG_SYS_HZ 1000
7379f45a DB	255
	256	/*-----------------------------------------------------------------------
	257	* Stack sizes
	258	*
	259	* The stack sizes are set up in start.S using the settings below
	260	*/
9c44ddcc	261	#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
7379f45a	262	#ifdef CONFIG_USE_IRQ
9c44ddcc SP	263	#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
9c44ddcc SP	264	#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
7379f45a DB	265	#endif
	266
	267	/*-----------------------------------------------------------------------
	268	* Physical Memory Map
	269	*/
	270	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	271	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
9c44ddcc	272	#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
7379f45a DB	273	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
	274
	275	/* SDRAM Bank Allocation method */
	276	#define SDRC_R_B_C 1
	277
	278	/*-----------------------------------------------------------------------
	279	* FLASH and environment organization
	280	*/
	281
	282	/* ** PISMO SUPPORT * */
	283
	284	/* Configure the PISMO */
	285	#define PISMO1_NAND_SIZE GPMC_SIZE_128M
	286	#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
	287
9c44ddcc	288	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
7379f45a	289
6cbec7b3 LC	290	#if defined(CONFIG_CMD_NAND)
	291	#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
	292	#endif
7379f45a DB	293
	294	/* Monitor at start of flash */
	295	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	296	#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
	297
	298	#define CONFIG_ENV_IS_IN_NAND 1
	299	#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
	300	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
	301
6cbec7b3 LC	302	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
6cbec7b3 LC	303	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
7379f45a DB	304	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
7379f45a DB	305
7379f45a	306	#endif /* __CONFIG_H */