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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
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2 | /* |
3 | * (C) Copyright 2002 | |
4 | * Wolfgang Denk, DENX Software Engineering, [email protected]. | |
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5 | */ |
6 | ||
d678a59d | 7 | #include <common.h> |
36bf446b | 8 | #include <irq_func.h> |
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9 | |
10 | /* | |
11 | * CPU test | |
12 | * Integer compare instructions: cmpwi, cmplwi | |
13 | * | |
14 | * To verify these instructions the test runs them with | |
15 | * different combinations of operands, reads the condition | |
16 | * register value and compares it with the expected one. | |
17 | * The test contains a pre-built table | |
18 | * containing the description of each test case: the instruction, | |
19 | * the values of the operands, the condition field to save | |
20 | * the result in and the expected result. | |
21 | */ | |
22 | ||
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23 | #include <post.h> |
24 | #include "cpu_asm.h" | |
25 | ||
1e019503 | 26 | #if CFG_POST & CFG_SYS_POST_CPU |
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27 | |
28 | extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); | |
29 | ||
30 | static struct cpu_post_cmpi_s | |
31 | { | |
32 | ulong cmd; | |
33 | ulong op1; | |
34 | ushort op2; | |
35 | ulong cr; | |
36 | ulong res; | |
37 | } cpu_post_cmpi_table[] = | |
38 | { | |
39 | { | |
40 | OP_CMPWI, | |
41 | 123, | |
42 | 123, | |
43 | 2, | |
44 | 0x02 | |
45 | }, | |
46 | { | |
47 | OP_CMPWI, | |
48 | 123, | |
49 | 133, | |
50 | 3, | |
51 | 0x08 | |
52 | }, | |
53 | { | |
54 | OP_CMPWI, | |
55 | 123, | |
56 | -133, | |
57 | 4, | |
58 | 0x04 | |
59 | }, | |
60 | { | |
61 | OP_CMPLWI, | |
62 | 123, | |
63 | 123, | |
64 | 2, | |
65 | 0x02 | |
66 | }, | |
67 | { | |
68 | OP_CMPLWI, | |
69 | 123, | |
70 | -133, | |
71 | 3, | |
72 | 0x08 | |
73 | }, | |
74 | { | |
75 | OP_CMPLWI, | |
76 | 123, | |
77 | 113, | |
78 | 4, | |
79 | 0x04 | |
80 | }, | |
81 | }; | |
d2397817 | 82 | static unsigned int cpu_post_cmpi_size = ARRAY_SIZE(cpu_post_cmpi_table); |
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83 | |
84 | int cpu_post_test_cmpi (void) | |
85 | { | |
86 | int ret = 0; | |
87 | unsigned int i; | |
f2302d44 | 88 | int flag = disable_interrupts(); |
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89 | |
90 | for (i = 0; i < cpu_post_cmpi_size && ret == 0; i++) | |
91 | { | |
92 | struct cpu_post_cmpi_s *test = cpu_post_cmpi_table + i; | |
53677ef1 | 93 | unsigned long code[] = |
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94 | { |
95 | ASM_1IC(test->cmd, test->cr, 3, test->op2), | |
96 | ASM_MFCR(3), | |
97 | ASM_BLR | |
98 | }; | |
99 | ulong res; | |
100 | ||
101 | cpu_post_exec_11 (code, & res, test->op1); | |
102 | ||
103 | ret = ((res >> (28 - 4 * test->cr)) & 0xe) == test->res ? 0 : -1; | |
104 | ||
105 | if (ret != 0) | |
106 | { | |
107 | post_log ("Error at cmpi test %d !\n", i); | |
108 | } | |
109 | } | |
110 | ||
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111 | if (flag) |
112 | enable_interrupts(); | |
113 | ||
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114 | return ret; |
115 | } | |
116 | ||
117 | #endif |