[J-u-boot.git] / drivers / pinctrl / exynos / pinctrl-exynos78x0.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Exynos78x0 pinctrl driver.
 *
 * Copyright (c) 2020 Dzmitry Sankouski ([email protected])
 *
 * based on drivers/pinctrl/exynos/pinctrl-exynos7420.c :
 * Copyright (C) 2016 Samsung Electronics
 * Thomas Abraham <[email protected]>
 */

#include <common.h>
#include <dm.h>
#include <errno.h>
#include <asm/io.h>
#include <dm/pinctrl.h>
#include <dm/root.h>
#include <fdtdec.h>
#include <asm/arch/pinmux.h>
#include "pinctrl-exynos.h"

static const struct pinctrl_ops exynos78x0_pinctrl_ops = {
	.set_state	= exynos_pinctrl_set_state
};

/* pin banks of exynos78x0 pin-controller 0 (ALIVE) */
static const struct samsung_pin_bank_data exynos78x0_pin_banks0[] = {
	EXYNOS_PIN_BANK(6, 0x000, "etc0"),
	EXYNOS_PIN_BANK(3, 0x020, "etc1"),
	EXYNOS_PIN_BANK(8, 0x040, "gpa0"),
	EXYNOS_PIN_BANK(8, 0x060, "gpa1"),
	EXYNOS_PIN_BANK(8, 0x080, "gpa2"),
	EXYNOS_PIN_BANK(5, 0x0a0, "gpa3"),
	EXYNOS_PIN_BANK(2, 0x0c0, "gpq0"),
};

/* pin banks of exynos78x0 pin-controller 1 (CCORE) */
static const struct samsung_pin_bank_data exynos78x0_pin_banks1[] = {
	EXYNOS_PIN_BANK(2, 0x000, "gpm0"),
};

/* pin banks of exynos78x0 pin-controller 2 (DISPAUD) */
static const struct samsung_pin_bank_data exynos78x0_pin_banks2[] = {
	EXYNOS_PIN_BANK(4, 0x000, "gpz0"),
	EXYNOS_PIN_BANK(6, 0x020, "gpz1"),
	EXYNOS_PIN_BANK(4, 0x040, "gpz2"),
};

/* pin banks of exynos78x0 pin-controller 4 (FSYS) */
static const struct samsung_pin_bank_data exynos78x0_pin_banks4[] = {
	EXYNOS_PIN_BANK(3, 0x000, "gpr0"),
	EXYNOS_PIN_BANK(8, 0x020, "gpr1"),
	EXYNOS_PIN_BANK(2, 0x040, "gpr2"),
	EXYNOS_PIN_BANK(4, 0x060, "gpr3"),
	EXYNOS_PIN_BANK(6, 0x080, "gpr4"),
};

/* pin banks of exynos78x0 pin-controller 6 (TOP) */
static const struct samsung_pin_bank_data exynos78x0_pin_banks6[] = {
	EXYNOS_PIN_BANK(4, 0x000, "gpb0"),
	EXYNOS_PIN_BANK(3, 0x020, "gpc0"),
	EXYNOS_PIN_BANK(4, 0x040, "gpc1"),
	EXYNOS_PIN_BANK(4, 0x060, "gpc4"),
	EXYNOS_PIN_BANK(2, 0x080, "gpc5"),
	EXYNOS_PIN_BANK(4, 0x0a0, "gpc6"),
	EXYNOS_PIN_BANK(2, 0x0c0, "gpc8"),
	EXYNOS_PIN_BANK(2, 0x0e0, "gpc9"),
	EXYNOS_PIN_BANK(7, 0x100, "gpd1"),
	EXYNOS_PIN_BANK(6, 0x120, "gpd2"),
	EXYNOS_PIN_BANK(8, 0x140, "gpd3"),
	EXYNOS_PIN_BANK(7, 0x160, "gpd4"),
	EXYNOS_PIN_BANK(5, 0x180, "gpd5"),
	EXYNOS_PIN_BANK(3, 0x1a0, "gpe0"),
	EXYNOS_PIN_BANK(4, 0x1c0, "gpf0"),
	EXYNOS_PIN_BANK(2, 0x1e0, "gpf1"),
	EXYNOS_PIN_BANK(2, 0x200, "gpf2"),
	EXYNOS_PIN_BANK(4, 0x220, "gpf3"),
	EXYNOS_PIN_BANK(5, 0x240, "gpf4"),
};

const struct samsung_pin_ctrl exynos78x0_pin_ctrl[] = {
	{
		/* pin-controller instance 0 Alive data */
		.pin_banks	= exynos78x0_pin_banks0,
		.nr_banks	= ARRAY_SIZE(exynos78x0_pin_banks0),
	}, {
		/* pin-controller instance 1 CCORE data */
		.pin_banks	= exynos78x0_pin_banks1,
		.nr_banks	= ARRAY_SIZE(exynos78x0_pin_banks1),
	}, {
		/* pin-controller instance 2 DISPAUD data */
		.pin_banks	= exynos78x0_pin_banks2,
		.nr_banks	= ARRAY_SIZE(exynos78x0_pin_banks2),
	}, {
		/* pin-controller instance 4 FSYS data */
		.pin_banks	= exynos78x0_pin_banks4,
		.nr_banks	= ARRAY_SIZE(exynos78x0_pin_banks4),
	}, {
		/* pin-controller instance 6 TOP data */
		.pin_banks	= exynos78x0_pin_banks6,
		.nr_banks	= ARRAY_SIZE(exynos78x0_pin_banks6),
	},
	{/* list terminator */}
};

static const struct udevice_id exynos78x0_pinctrl_ids[] = {
	{ .compatible = "samsung,exynos78x0-pinctrl",
		.data = (ulong)exynos78x0_pin_ctrl },
	{ }
};

U_BOOT_DRIVER(pinctrl_exynos78x0) = {
	.name		= "pinctrl_exynos78x0",
	.id		= UCLASS_PINCTRL,
	.of_match	= exynos78x0_pinctrl_ids,
	.priv_auto = sizeof(struct exynos_pinctrl_priv),
	.ops		= &exynos78x0_pinctrl_ops,
	.probe		= exynos_pinctrl_probe,
};
Commit	Line	Data
69bde041 DS	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Exynos78x0 pinctrl driver.
	4	*
	5	* Copyright (c) 2020 Dzmitry Sankouski ([email protected])
	6	*
	7	* based on drivers/pinctrl/exynos/pinctrl-exynos7420.c :
	8	* Copyright (C) 2016 Samsung Electronics
	9	* Thomas Abraham <[email protected]>
	10	*/
	11
d678a59d	12	#include <common.h>
69bde041 DS	13	#include <dm.h>
	14	#include <errno.h>
	15	#include <asm/io.h>
	16	#include <dm/pinctrl.h>
	17	#include <dm/root.h>
	18	#include <fdtdec.h>
	19	#include <asm/arch/pinmux.h>
	20	#include "pinctrl-exynos.h"
	21
2b77d9a3	22	static const struct pinctrl_ops exynos78x0_pinctrl_ops = {
69bde041 DS	23	.set_state = exynos_pinctrl_set_state
	24	};
	25
	26	/* pin banks of exynos78x0 pin-controller 0 (ALIVE) */
2b77d9a3	27	static const struct samsung_pin_bank_data exynos78x0_pin_banks0[] = {
69bde041 DS	28	EXYNOS_PIN_BANK(6, 0x000, "etc0"),
	29	EXYNOS_PIN_BANK(3, 0x020, "etc1"),
	30	EXYNOS_PIN_BANK(8, 0x040, "gpa0"),
	31	EXYNOS_PIN_BANK(8, 0x060, "gpa1"),
	32	EXYNOS_PIN_BANK(8, 0x080, "gpa2"),
	33	EXYNOS_PIN_BANK(5, 0x0a0, "gpa3"),
	34	EXYNOS_PIN_BANK(2, 0x0c0, "gpq0"),
	35	};
	36
	37	/* pin banks of exynos78x0 pin-controller 1 (CCORE) */
2b77d9a3	38	static const struct samsung_pin_bank_data exynos78x0_pin_banks1[] = {
69bde041 DS	39	EXYNOS_PIN_BANK(2, 0x000, "gpm0"),
	40	};
	41
	42	/* pin banks of exynos78x0 pin-controller 2 (DISPAUD) */
2b77d9a3	43	static const struct samsung_pin_bank_data exynos78x0_pin_banks2[] = {
69bde041 DS	44	EXYNOS_PIN_BANK(4, 0x000, "gpz0"),
	45	EXYNOS_PIN_BANK(6, 0x020, "gpz1"),
	46	EXYNOS_PIN_BANK(4, 0x040, "gpz2"),
	47	};
	48
	49	/* pin banks of exynos78x0 pin-controller 4 (FSYS) */
2b77d9a3	50	static const struct samsung_pin_bank_data exynos78x0_pin_banks4[] = {
69bde041 DS	51	EXYNOS_PIN_BANK(3, 0x000, "gpr0"),
	52	EXYNOS_PIN_BANK(8, 0x020, "gpr1"),
	53	EXYNOS_PIN_BANK(2, 0x040, "gpr2"),
	54	EXYNOS_PIN_BANK(4, 0x060, "gpr3"),
	55	EXYNOS_PIN_BANK(6, 0x080, "gpr4"),
	56	};
	57
	58	/* pin banks of exynos78x0 pin-controller 6 (TOP) */
2b77d9a3	59	static const struct samsung_pin_bank_data exynos78x0_pin_banks6[] = {
69bde041 DS	60	EXYNOS_PIN_BANK(4, 0x000, "gpb0"),
	61	EXYNOS_PIN_BANK(3, 0x020, "gpc0"),
	62	EXYNOS_PIN_BANK(4, 0x040, "gpc1"),
	63	EXYNOS_PIN_BANK(4, 0x060, "gpc4"),
	64	EXYNOS_PIN_BANK(2, 0x080, "gpc5"),
	65	EXYNOS_PIN_BANK(4, 0x0a0, "gpc6"),
	66	EXYNOS_PIN_BANK(2, 0x0c0, "gpc8"),
	67	EXYNOS_PIN_BANK(2, 0x0e0, "gpc9"),
	68	EXYNOS_PIN_BANK(7, 0x100, "gpd1"),
	69	EXYNOS_PIN_BANK(6, 0x120, "gpd2"),
	70	EXYNOS_PIN_BANK(8, 0x140, "gpd3"),
	71	EXYNOS_PIN_BANK(7, 0x160, "gpd4"),
	72	EXYNOS_PIN_BANK(5, 0x180, "gpd5"),
	73	EXYNOS_PIN_BANK(3, 0x1a0, "gpe0"),
	74	EXYNOS_PIN_BANK(4, 0x1c0, "gpf0"),
	75	EXYNOS_PIN_BANK(2, 0x1e0, "gpf1"),
	76	EXYNOS_PIN_BANK(2, 0x200, "gpf2"),
	77	EXYNOS_PIN_BANK(4, 0x220, "gpf3"),
	78	EXYNOS_PIN_BANK(5, 0x240, "gpf4"),
	79	};
	80
2b77d9a3	81	const struct samsung_pin_ctrl exynos78x0_pin_ctrl[] = {
69bde041 DS	82	{
	83	/* pin-controller instance 0 Alive data */
	84	.pin_banks = exynos78x0_pin_banks0,
	85	.nr_banks = ARRAY_SIZE(exynos78x0_pin_banks0),
	86	}, {
	87	/* pin-controller instance 1 CCORE data */
	88	.pin_banks = exynos78x0_pin_banks1,
	89	.nr_banks = ARRAY_SIZE(exynos78x0_pin_banks1),
	90	}, {
	91	/* pin-controller instance 2 DISPAUD data */
	92	.pin_banks = exynos78x0_pin_banks2,
	93	.nr_banks = ARRAY_SIZE(exynos78x0_pin_banks2),
	94	}, {
	95	/* pin-controller instance 4 FSYS data */
	96	.pin_banks = exynos78x0_pin_banks4,
	97	.nr_banks = ARRAY_SIZE(exynos78x0_pin_banks4),
	98	}, {
	99	/* pin-controller instance 6 TOP data */
	100	.pin_banks = exynos78x0_pin_banks6,
	101	.nr_banks = ARRAY_SIZE(exynos78x0_pin_banks6),
	102	},
	103	{/* list terminator */}
	104	};
	105
	106	static const struct udevice_id exynos78x0_pinctrl_ids[] = {
	107	{ .compatible = "samsung,exynos78x0-pinctrl",
	108	.data = (ulong)exynos78x0_pin_ctrl },
	109	{ }
	110	};
	111
	112	U_BOOT_DRIVER(pinctrl_exynos78x0) = {
	113	.name = "pinctrl_exynos78x0",
	114	.id = UCLASS_PINCTRL,
	115	.of_match = exynos78x0_pinctrl_ids,
	116	.priv_auto = sizeof(struct exynos_pinctrl_priv),
	117	.ops = &exynos78x0_pinctrl_ops,
	118	.probe = exynos_pinctrl_probe,
	119	};