[J-u-boot.git] / drivers / net / dwc_eth_qos_starfive.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2023 StarFive Technology Co., Ltd.
 * Author: Yanhong Wang<[email protected]>
 */

#include <common.h>
#include <asm/cache.h>
#include <asm/gpio.h>
#include <clk.h>
#include <dm.h>
#include <eth_phy.h>
#include <net.h>
#include <regmap.h>
#include <reset.h>
#include <syscon.h>

#include "dwc_eth_qos.h"

#define STARFIVE_DWMAC_PHY_INFT_RGMII	0x1
#define STARFIVE_DWMAC_PHY_INFT_RMII	0x4
#define STARFIVE_DWMAC_PHY_INFT_FIELD	0x7U

struct starfive_platform_data {
	struct regmap *regmap;
	struct reset_ctl_bulk resets;
	struct clk_bulk clks;
	phy_interface_t interface;
	u32 offset;
	u32 shift;
	bool tx_use_rgmii_clk;
};

static int eqos_interface_init_jh7110(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct starfive_platform_data *data = pdata->priv_pdata;
	struct ofnode_phandle_args args;
	unsigned int mode;
	int ret;

	switch (data->interface) {
	case PHY_INTERFACE_MODE_RMII:
		mode = STARFIVE_DWMAC_PHY_INFT_RMII;
		break;

	case PHY_INTERFACE_MODE_RGMII:
	case PHY_INTERFACE_MODE_RGMII_ID:
		mode = STARFIVE_DWMAC_PHY_INFT_RGMII;
		break;

	default:
		return -EINVAL;
	}

	ret = dev_read_phandle_with_args(dev, "starfive,syscon", NULL,
					 2, 0, &args);
	if (ret)
		return ret;

	if (args.args_count != 2)
		return -EINVAL;

	data->offset = args.args[0];
	data->shift = args.args[1];
	data->regmap = syscon_regmap_lookup_by_phandle(dev, "starfive,syscon");
	if (IS_ERR(data->regmap)) {
		ret = PTR_ERR(data->regmap);
		pr_err("Failed to get regmap: %d\n", ret);
		return ret;
	}

	return regmap_update_bits(data->regmap, data->offset,
				  STARFIVE_DWMAC_PHY_INFT_FIELD << data->shift,
				  mode << data->shift);
}

static int eqos_set_tx_clk_speed_jh7110(struct udevice *dev)
{
	struct eqos_priv *eqos = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct starfive_platform_data *data = pdata->priv_pdata;
	struct clk *pclk, *c;
	ulong rate;
	int ret;

	/* Generally, the rgmii_tx clock is provided by the internal clock,
	 * which needs to match the corresponding clock frequency according
	 * to different speeds. If the rgmii_tx clock is provided by the
	 * external rgmii_rxin, there is no need to configure the clock
	 * internally, because rgmii_rxin will be adaptively adjusted.
	 */
	if (data->tx_use_rgmii_clk)
		return 0;

	switch (eqos->phy->speed) {
	case SPEED_1000:
		rate = 125 * 1000 * 1000;
		break;
	case SPEED_100:
		rate = 25 * 1000 * 1000;
		break;
	case SPEED_10:
		rate = 2.5 * 1000 * 1000;
		break;
	default:
		pr_err("invalid speed %d", eqos->phy->speed);
		return -EINVAL;
	}

	/* eqos->clk_tx clock has no set rate operation, so just set the parent
	 * clock rate directly
	 */
	ret = clk_get_by_id(eqos->clk_tx.id, &c);
	if (ret)
		return ret;

	pclk = clk_get_parent(c);
	if (pclk) {
		ret = clk_set_rate(pclk, rate);
		if (ret < 0) {
			pr_err("jh7110 (clk_tx, %lu) failed: %d", rate, ret);
			return ret;
		}
	}

	return 0;
}

static ulong eqos_get_tick_clk_rate_jh7110(struct udevice *dev)
{
	struct eqos_priv *eqos = dev_get_priv(dev);

	return clk_get_rate(&eqos->clk_tx);
}

static int eqos_start_clks_jh7110(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct starfive_platform_data *data = pdata->priv_pdata;

	return clk_enable_bulk(&data->clks);
}

static int eqos_stop_clks_jh7110(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct starfive_platform_data *data = pdata->priv_pdata;

	return clk_disable_bulk(&data->clks);
}

static int eqos_start_resets_jh7110(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct starfive_platform_data *data = pdata->priv_pdata;

	return reset_deassert_bulk(&data->resets);
}

static int eqos_stop_resets_jh7110(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct starfive_platform_data *data = pdata->priv_pdata;

	return reset_assert_bulk(&data->resets);
}

static int eqos_remove_resources_jh7110(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct starfive_platform_data *data = pdata->priv_pdata;

	reset_assert_bulk(&data->resets);
	clk_disable_bulk(&data->clks);

	return 0;
}

static int eqos_probe_resources_jh7110(struct udevice *dev)
{
	struct eqos_priv *eqos = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct starfive_platform_data *data;
	int ret;

	data = calloc(1, sizeof(struct starfive_platform_data));
	if (!data)
		return -ENOMEM;

	pdata->priv_pdata = data;
	data->interface = eqos->config->interface(dev);
	if (data->interface == PHY_INTERFACE_MODE_NA) {
		pr_err("Invalid PHY interface\n");
		return -EINVAL;
	}

	ret = reset_get_bulk(dev, &data->resets);
	if (ret < 0)
		return ret;

	ret = clk_get_bulk(dev, &data->clks);
	if (ret < 0)
		return ret;

	ret = clk_get_by_name(dev, "gtx", &eqos->clk_tx);
	if (ret)
		return ret;

	data->tx_use_rgmii_clk = dev_read_bool(dev, "starfive,tx-use-rgmii-clk");

	return eqos_interface_init_jh7110(dev);
}

static struct eqos_ops eqos_jh7110_ops = {
	.eqos_inval_desc = eqos_inval_desc_generic,
	.eqos_flush_desc = eqos_flush_desc_generic,
	.eqos_inval_buffer = eqos_inval_buffer_generic,
	.eqos_flush_buffer = eqos_flush_buffer_generic,
	.eqos_probe_resources = eqos_probe_resources_jh7110,
	.eqos_remove_resources = eqos_remove_resources_jh7110,
	.eqos_stop_resets = eqos_stop_resets_jh7110,
	.eqos_start_resets = eqos_start_resets_jh7110,
	.eqos_stop_clks = eqos_stop_clks_jh7110,
	.eqos_start_clks = eqos_start_clks_jh7110,
	.eqos_calibrate_pads = eqos_null_ops,
	.eqos_disable_calibration = eqos_null_ops,
	.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_jh7110,
	.eqos_get_enetaddr = eqos_null_ops,
	.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_jh7110
};

/* mdio_wait: There is no need to wait after setting the MAC_MDIO_Address register
 * swr_wait: Software reset bit must be read at least 4 CSR clock cycles
 *          after it is written to 1.
 * config_mac: Enable rx queue to DCB mode.
 * config_mac_mdio: CSR clock range is 250-300 Mhz.
 * axi_bus_width: The width of the data bus is 64 bit.
 */
struct eqos_config __maybe_unused eqos_jh7110_config = {
	.reg_access_always_ok = false,
	.mdio_wait = 0,
	.swr_wait = 4,
	.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
	.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
	.axi_bus_width = EQOS_AXI_WIDTH_64,
	.interface = dev_read_phy_mode,
	.ops = &eqos_jh7110_ops
};
Commit	Line	Data
736733b4 YW	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright (C) 2023 StarFive Technology Co., Ltd.
	4	* Author: Yanhong Wang<[email protected]>
	5	*/
	6
d678a59d	7	#include <common.h>
736733b4 YW	8	#include <asm/cache.h>
	9	#include <asm/gpio.h>
	10	#include <clk.h>
	11	#include <dm.h>
	12	#include <eth_phy.h>
	13	#include <net.h>
	14	#include <regmap.h>
	15	#include <reset.h>
	16	#include <syscon.h>
	17
	18	#include "dwc_eth_qos.h"
	19
	20	#define STARFIVE_DWMAC_PHY_INFT_RGMII 0x1
	21	#define STARFIVE_DWMAC_PHY_INFT_RMII 0x4
	22	#define STARFIVE_DWMAC_PHY_INFT_FIELD 0x7U
	23
	24	struct starfive_platform_data {
	25	struct regmap *regmap;
	26	struct reset_ctl_bulk resets;
	27	struct clk_bulk clks;
	28	phy_interface_t interface;
	29	u32 offset;
	30	u32 shift;
	31	bool tx_use_rgmii_clk;
	32	};
	33
	34	static int eqos_interface_init_jh7110(struct udevice *dev)
	35	{
	36	struct eth_pdata *pdata = dev_get_plat(dev);
	37	struct starfive_platform_data *data = pdata->priv_pdata;
	38	struct ofnode_phandle_args args;
	39	unsigned int mode;
	40	int ret;
	41
	42	switch (data->interface) {
	43	case PHY_INTERFACE_MODE_RMII:
	44	mode = STARFIVE_DWMAC_PHY_INFT_RMII;
	45	break;
	46
	47	case PHY_INTERFACE_MODE_RGMII:
	48	case PHY_INTERFACE_MODE_RGMII_ID:
	49	mode = STARFIVE_DWMAC_PHY_INFT_RGMII;
	50	break;
	51
	52	default:
	53	return -EINVAL;
	54	}
	55
	56	ret = dev_read_phandle_with_args(dev, "starfive,syscon", NULL,
	57	2, 0, &args);
	58	if (ret)
	59	return ret;
	60
	61	if (args.args_count != 2)
	62	return -EINVAL;
	63
	64	data->offset = args.args[0];
	65	data->shift = args.args[1];
	66	data->regmap = syscon_regmap_lookup_by_phandle(dev, "starfive,syscon");
	67	if (IS_ERR(data->regmap)) {
	68	ret = PTR_ERR(data->regmap);
	69	pr_err("Failed to get regmap: %d\n", ret);
	70	return ret;
	71	}
72
73	return regmap_update_bits(data->regmap, data->offset,
74	STARFIVE_DWMAC_PHY_INFT_FIELD << data->shift,
75	mode << data->shift);
76	}
77
78	static int eqos_set_tx_clk_speed_jh7110(struct udevice *dev)
79	{
80	struct eqos_priv *eqos = dev_get_priv(dev);
81	struct eth_pdata *pdata = dev_get_plat(dev);
82	struct starfive_platform_data *data = pdata->priv_pdata;
83	struct clk pclk, c;
84	ulong rate;
85	int ret;
86
87	/* Generally, the rgmii_tx clock is provided by the internal clock,
88	* which needs to match the corresponding clock frequency according
89	* to different speeds. If the rgmii_tx clock is provided by the
90	* external rgmii_rxin, there is no need to configure the clock
91	* internally, because rgmii_rxin will be adaptively adjusted.
92	*/
93	if (data->tx_use_rgmii_clk)
94	return 0;
95
96	switch (eqos->phy->speed) {
97	case SPEED_1000:
98	rate = 125 * 1000 * 1000;
99	break;
100	case SPEED_100:
101	rate = 25 * 1000 * 1000;
102	break;
103	case SPEED_10:
104	rate = 2.5 * 1000 * 1000;
105	break;
106	default:
107	pr_err("invalid speed %d", eqos->phy->speed);
108	return -EINVAL;
109	}
110
111	/* eqos->clk_tx clock has no set rate operation, so just set the parent
112	* clock rate directly
113	*/
114	ret = clk_get_by_id(eqos->clk_tx.id, &c);
115	if (ret)
116	return ret;
117
118	pclk = clk_get_parent(c);
119	if (pclk) {
120	ret = clk_set_rate(pclk, rate);
121	if (ret < 0) {
122	pr_err("jh7110 (clk_tx, %lu) failed: %d", rate, ret);
123	return ret;
124	}
125	}
126
127	return 0;
128	}
129
130	static ulong eqos_get_tick_clk_rate_jh7110(struct udevice *dev)
131	{
132	struct eqos_priv *eqos = dev_get_priv(dev);
133
134	return clk_get_rate(&eqos->clk_tx);
135	}
136
137	static int eqos_start_clks_jh7110(struct udevice *dev)
138	{
139	struct eth_pdata *pdata = dev_get_plat(dev);
140	struct starfive_platform_data *data = pdata->priv_pdata;
141
142	return clk_enable_bulk(&data->clks);
143	}
144
145	static int eqos_stop_clks_jh7110(struct udevice *dev)
146	{
147	struct eth_pdata *pdata = dev_get_plat(dev);
148	struct starfive_platform_data *data = pdata->priv_pdata;
149
150	return clk_disable_bulk(&data->clks);
151	}
152
153	static int eqos_start_resets_jh7110(struct udevice *dev)
154	{
155	struct eth_pdata *pdata = dev_get_plat(dev);
156	struct starfive_platform_data *data = pdata->priv_pdata;
157
158	return reset_deassert_bulk(&data->resets);
159	}
160
161	static int eqos_stop_resets_jh7110(struct udevice *dev)
162	{
163	struct eth_pdata *pdata = dev_get_plat(dev);
164	struct starfive_platform_data *data = pdata->priv_pdata;
165
166	return reset_assert_bulk(&data->resets);
167	}
168
169	static int eqos_remove_resources_jh7110(struct udevice *dev)
170	{
171	struct eth_pdata *pdata = dev_get_plat(dev);
172	struct starfive_platform_data *data = pdata->priv_pdata;
173
174	reset_assert_bulk(&data->resets);
175	clk_disable_bulk(&data->clks);
176
177	return 0;
178	}
179
180	static int eqos_probe_resources_jh7110(struct udevice *dev)
181	{
182	struct eqos_priv *eqos = dev_get_priv(dev);
183	struct eth_pdata *pdata = dev_get_plat(dev);
184	struct starfive_platform_data *data;
185	int ret;
186
187	data = calloc(1, sizeof(struct starfive_platform_data));
188	if (!data)
189	return -ENOMEM;
190
191	pdata->priv_pdata = data;
192	data->interface = eqos->config->interface(dev);
193	if (data->interface == PHY_INTERFACE_MODE_NA) {
194	pr_err("Invalid PHY interface\n");
195	return -EINVAL;
196	}
197
198	ret = reset_get_bulk(dev, &data->resets);
199	if (ret < 0)
200	return ret;
201
202	ret = clk_get_bulk(dev, &data->clks);
203	if (ret < 0)
204	return ret;
205
206	ret = clk_get_by_name(dev, "gtx", &eqos->clk_tx);
207	if (ret)
208	return ret;
209
210	data->tx_use_rgmii_clk = dev_read_bool(dev, "starfive,tx-use-rgmii-clk");
211
212	return eqos_interface_init_jh7110(dev);
213	}
214
215	static struct eqos_ops eqos_jh7110_ops = {
216	.eqos_inval_desc = eqos_inval_desc_generic,
217	.eqos_flush_desc = eqos_flush_desc_generic,
218	.eqos_inval_buffer = eqos_inval_buffer_generic,
219	.eqos_flush_buffer = eqos_flush_buffer_generic,
220	.eqos_probe_resources = eqos_probe_resources_jh7110,
221	.eqos_remove_resources = eqos_remove_resources_jh7110,
222	.eqos_stop_resets = eqos_stop_resets_jh7110,
223	.eqos_start_resets = eqos_start_resets_jh7110,
224	.eqos_stop_clks = eqos_stop_clks_jh7110,
225	.eqos_start_clks = eqos_start_clks_jh7110,
226	.eqos_calibrate_pads = eqos_null_ops,
227	.eqos_disable_calibration = eqos_null_ops,
228	.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_jh7110,
229	.eqos_get_enetaddr = eqos_null_ops,
230	.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_jh7110
231	};
232
233	/* mdio_wait: There is no need to wait after setting the MAC_MDIO_Address register
234	* swr_wait: Software reset bit must be read at least 4 CSR clock cycles
235	* after it is written to 1.
236	* config_mac: Enable rx queue to DCB mode.
237	* config_mac_mdio: CSR clock range is 250-300 Mhz.
238	* axi_bus_width: The width of the data bus is 64 bit.
239	*/
240	struct eqos_config __maybe_unused eqos_jh7110_config = {
241	.reg_access_always_ok = false,
242	.mdio_wait = 0,
243	.swr_wait = 4,
244	.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
245	.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
246	.axi_bus_width = EQOS_AXI_WIDTH_64,
247	.interface = dev_read_phy_mode,
248	.ops = &eqos_jh7110_ops
249	};