projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 4c835a60 SR |
1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* | |
| 3 | * Copyright (C) 2018 Stefan Roese <[email protected]> | |
| 4 | */ | |
| 5 | ||
| 6 | #ifndef __MT76XX_H | |
| 7 | #define __MT76XX_H | |
| 8 | ||
| 9 | #define MT76XX_SYSCTL_BASE 0x10000000 | |
| 10 | ||
| 11 | #define MT76XX_CHIPID_OFFS 0x00 | |
| 12 | #define MT76XX_CHIP_REV_ID_OFFS 0x0c | |
| 13 | #define MT76XX_SYSCFG0_OFFS 0x10 | |
| 14 | ||
| 15 | #define MT76XX_MEMCTRL_BASE (MT76XX_SYSCTL_BASE + 0x0300) | |
| 16 | #define MT76XX_RGCTRL_BASE (MT76XX_SYSCTL_BASE + 0x1000) | |
| 17 | ||
| 18 | #define MT76XX_ROM_STATUS_REG (MT76XX_SYSCTL_BASE + 0x0028) | |
| 19 | #define MT76XX_CLKCFG0_REG (MT76XX_SYSCTL_BASE + 0x002c) | |
| 20 | #define MT76XX_DYN_CFG0_REG (MT76XX_SYSCTL_BASE + 0x0440) | |
| 21 | ||
| 22 | #define DDR_CFG1_REG (MT76XX_MEMCTRL_BASE + 0x44) | |
| 23 | #define DDR_CFG2_REG (MT76XX_MEMCTRL_BASE + 0x48) | |
| 24 | #define DDR_CFG3_REG (MT76XX_MEMCTRL_BASE + 0x4c) | |
| 25 | #define DDR_CFG4_REG (MT76XX_MEMCTRL_BASE + 0x50) | |
| 26 | ||
| 27 | #ifndef __ASSEMBLY__ | |
| 28 | /* Prototypes */ | |
| 29 | void ddr_calibrate(void); | |
| 30 | #endif | |
| 31 | ||
| 32 | #endif |