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rockchip: rk3399: Add Nanopi M4 2GB board support
[J-u-boot.git] / arch / arm / dts / r8a7793.dtsi
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83d290c5 1// SPDX-License-Identifier: GPL-2.0
92aa0995 2/*
3abd800e 3 * Device Tree Source for the R-Car M2-N (R8A77930) SoC
92aa0995
MV		 4 *
5 * Copyright (C) 2014-2015 Renesas Electronics Corporation
92aa0995
MV		 6 */
7
8#include <dt-bindings/clock/r8a7793-cpg-mssr.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/power/r8a7793-sysc.h>
12
13/ {
14 compatible = "renesas,r8a7793";
92aa0995
MV		 15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 aliases {
19 i2c0 = &i2c0;
20 i2c1 = &i2c1;
21 i2c2 = &i2c2;
22 i2c3 = &i2c3;
23 i2c4 = &i2c4;
24 i2c5 = &i2c5;
25 i2c6 = &i2c6;
26 i2c7 = &i2c7;
27 i2c8 = &i2c8;
28 spi0 = &qspi;
29 };
30
252c8b45
MV		 31 /*
32 * The external audio clocks are configured as 0 Hz fixed frequency
33 * clocks by default.
34 * Boards that provide audio clocks should override them.
35 */
36 audio_clk_a: audio_clk_a {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <0>;
40 };
41 audio_clk_b: audio_clk_b {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
44 clock-frequency = <0>;
45 };
46 audio_clk_c: audio_clk_c {
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <0>;
50 };
51
52 /* External CAN clock */
53 can_clk: can {
54 compatible = "fixed-clock";
55 #clock-cells = <0>;
56 /* This value must be overridden by the board. */
57 clock-frequency = <0>;
58 };
59
92aa0995
MV		 60 cpus {
61 #address-cells = <1>;
62 #size-cells = <0>;
63 enable-method = "renesas,apmu";
64
65 cpu0: cpu@0 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a15";
68 reg = <0>;
69 clock-frequency = <1500000000>;
92aa0995 70 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
92aa0995 71 power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
3b255531
MV		 72 voltage-tolerance = <1>; /* 1% */
73 clock-latency = <300000>; /* 300 us */
92aa0995
MV		 74
75 /* kHz - uV - OPPs unknown yet */
76 operating-points = <1500000 1000000>,
77 <1312500 1000000>,
78 <1125000 1000000>,
79 < 937500 1000000>,
80 < 750000 1000000>,
81 < 375000 1000000>;
82 next-level-cache = <&L2_CA15>;
83 };
84
85 cpu1: cpu@1 {
86 device_type = "cpu";
87 compatible = "arm,cortex-a15";
88 reg = <1>;
89 clock-frequency = <1500000000>;
90 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
91 power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
3b255531
MV		 92 voltage-tolerance = <1>; /* 1% */
93 clock-latency = <300000>; /* 300 us */
94
95 /* kHz - uV - OPPs unknown yet */
96 operating-points = <1500000 1000000>,
97 <1312500 1000000>,
98 <1125000 1000000>,
99 < 937500 1000000>,
100 < 750000 1000000>,
101 < 375000 1000000>;
102 next-level-cache = <&L2_CA15>;
92aa0995
MV		 103 };
104
105 L2_CA15: cache-controller-0 {
106 compatible = "cache";
107 power-domains = <&sysc R8A7793_PD_CA15_SCU>;
108 cache-unified;
109 cache-level = <2>;
110 };
111 };
112
252c8b45
MV		 113 /* External root clock */
114 extal_clk: extal {
115 compatible = "fixed-clock";
116 #clock-cells = <0>;
117 /* This value must be overridden by the board. */
118 clock-frequency = <0>;
92aa0995
MV		 119 };
120
3b255531
MV		 121 pmu {
122 compatible = "arm,cortex-a15-pmu";
123 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
124 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
125 interrupt-affinity = <&cpu0>, <&cpu1>;
126 };
127
252c8b45
MV		 128 /* External SCIF clock */
129 scif_clk: scif {
130 compatible = "fixed-clock";
131 #clock-cells = <0>;
132 /* This value must be overridden by the board. */
133 clock-frequency = <0>;
92aa0995
MV		 134 };
135
252c8b45
MV		 136 soc {
137 compatible = "simple-bus";
138 interrupt-parent = <&gic>;
139
140 #address-cells = <2>;
141 #size-cells = <2>;
142 ranges;
143
3b255531
MV		 144 rwdt: watchdog@e6020000 {
145 compatible = "renesas,r8a7793-wdt",
146 "renesas,rcar-gen2-wdt";
147 reg = <0 0xe6020000 0 0x0c>;
148 clocks = <&cpg CPG_MOD 402>;
149 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
150 resets = <&cpg 402>;
151 status = "disabled";
152 };
153
252c8b45
MV		 154 gpio0: gpio@e6050000 {
155 compatible = "renesas,gpio-r8a7793",
156 "renesas,rcar-gen2-gpio";
157 reg = <0 0xe6050000 0 0x50>;
158 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
159 #gpio-cells = <2>;
160 gpio-controller;
161 gpio-ranges = <&pfc 0 0 32>;
162 #interrupt-cells = <2>;
163 interrupt-controller;
164 clocks = <&cpg CPG_MOD 912>;
165 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
166 resets = <&cpg 912>;
167 };
92aa0995 168
252c8b45
MV		 169 gpio1: gpio@e6051000 {
170 compatible = "renesas,gpio-r8a7793",
171 "renesas,rcar-gen2-gpio";
172 reg = <0 0xe6051000 0 0x50>;
173 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
174 #gpio-cells = <2>;
175 gpio-controller;
176 gpio-ranges = <&pfc 0 32 26>;
177 #interrupt-cells = <2>;
178 interrupt-controller;
179 clocks = <&cpg CPG_MOD 911>;
180 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
181 resets = <&cpg 911>;
182 };
92aa0995 183
252c8b45
MV		 184 gpio2: gpio@e6052000 {
185 compatible = "renesas,gpio-r8a7793",
186 "renesas,rcar-gen2-gpio";
187 reg = <0 0xe6052000 0 0x50>;
188 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
189 #gpio-cells = <2>;
190 gpio-controller;
191 gpio-ranges = <&pfc 0 64 32>;
192 #interrupt-cells = <2>;
193 interrupt-controller;
194 clocks = <&cpg CPG_MOD 910>;
195 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
196 resets = <&cpg 910>;
197 };
92aa0995 198
252c8b45
MV		 199 gpio3: gpio@e6053000 {
200 compatible = "renesas,gpio-r8a7793",
201 "renesas,rcar-gen2-gpio";
202 reg = <0 0xe6053000 0 0x50>;
203 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
204 #gpio-cells = <2>;
205 gpio-controller;
206 gpio-ranges = <&pfc 0 96 32>;
207 #interrupt-cells = <2>;
208 interrupt-controller;
209 clocks = <&cpg CPG_MOD 909>;
210 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
211 resets = <&cpg 909>;
212 };
92aa0995 213
252c8b45
MV		 214 gpio4: gpio@e6054000 {
215 compatible = "renesas,gpio-r8a7793",
216 "renesas,rcar-gen2-gpio";
217 reg = <0 0xe6054000 0 0x50>;
218 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
219 #gpio-cells = <2>;
220 gpio-controller;
221 gpio-ranges = <&pfc 0 128 32>;
222 #interrupt-cells = <2>;
223 interrupt-controller;
224 clocks = <&cpg CPG_MOD 908>;
225 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
226 resets = <&cpg 908>;
227 };
92aa0995 228
252c8b45
MV		 229 gpio5: gpio@e6055000 {
230 compatible = "renesas,gpio-r8a7793",
231 "renesas,rcar-gen2-gpio";
232 reg = <0 0xe6055000 0 0x50>;
233 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
234 #gpio-cells = <2>;
235 gpio-controller;
236 gpio-ranges = <&pfc 0 160 32>;
237 #interrupt-cells = <2>;
238 interrupt-controller;
239 clocks = <&cpg CPG_MOD 907>;
240 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
241 resets = <&cpg 907>;
242 };
92aa0995 243
252c8b45
MV		 244 gpio6: gpio@e6055400 {
245 compatible = "renesas,gpio-r8a7793",
246 "renesas,rcar-gen2-gpio";
247 reg = <0 0xe6055400 0 0x50>;
248 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
249 #gpio-cells = <2>;
250 gpio-controller;
251 gpio-ranges = <&pfc 0 192 32>;
252 #interrupt-cells = <2>;
253 interrupt-controller;
254 clocks = <&cpg CPG_MOD 905>;
255 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
256 resets = <&cpg 905>;
257 };
92aa0995 258
252c8b45
MV		 259 gpio7: gpio@e6055800 {
260 compatible = "renesas,gpio-r8a7793",
261 "renesas,rcar-gen2-gpio";
262 reg = <0 0xe6055800 0 0x50>;
263 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
264 #gpio-cells = <2>;
265 gpio-controller;
266 gpio-ranges = <&pfc 0 224 26>;
267 #interrupt-cells = <2>;
268 interrupt-controller;
269 clocks = <&cpg CPG_MOD 904>;
270 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
271 resets = <&cpg 904>;
272 };
92aa0995 273
252c8b45
MV		 274 pfc: pin-controller@e6060000 {
275 compatible = "renesas,pfc-r8a7793";
276 reg = <0 0xe6060000 0 0x250>;
277 };
92aa0995 278
252c8b45
MV		 279 /* Special CPG clocks */
280 cpg: clock-controller@e6150000 {
281 compatible = "renesas,r8a7793-cpg-mssr";
282 reg = <0 0xe6150000 0 0x1000>;
283 clocks = <&extal_clk>, <&usb_extal_clk>;
284 clock-names = "extal", "usb_extal";
285 #clock-cells = <2>;
286 #power-domain-cells = <0>;
287 #reset-cells = <1>;
288 };
92aa0995 289
252c8b45
MV		 290 apmu@e6152000 {
291 compatible = "renesas,r8a7793-apmu", "renesas,apmu";
292 reg = <0 0xe6152000 0 0x188>;
293 cpus = <&cpu0 &cpu1>;
294 };
92aa0995 295
252c8b45
MV		 296 rst: reset-controller@e6160000 {
297 compatible = "renesas,r8a7793-rst";
298 reg = <0 0xe6160000 0 0x0100>;
299 };
92aa0995 300
252c8b45
MV		 301 sysc: system-controller@e6180000 {
302 compatible = "renesas,r8a7793-sysc";
303 reg = <0 0xe6180000 0 0x0200>;
304 #power-domain-cells = <1>;
305 };
92aa0995 306
252c8b45
MV		 307 irqc0: interrupt-controller@e61c0000 {
308 compatible = "renesas,irqc-r8a7793", "renesas,irqc";
309 #interrupt-cells = <2>;
310 interrupt-controller;
311 reg = <0 0xe61c0000 0 0x200>;
312 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&cpg CPG_MOD 407>;
323 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
324 resets = <&cpg 407>;
325 };
92aa0995 326
252c8b45
MV		 327 thermal: thermal@e61f0000 {
328 compatible = "renesas,thermal-r8a7793",
329 "renesas,rcar-gen2-thermal",
330 "renesas,rcar-thermal";
331 reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
332 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&cpg CPG_MOD 522>;
334 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
335 resets = <&cpg 522>;
336 #thermal-sensor-cells = <0>;
337 };
92aa0995 338
252c8b45
MV		 339 ipmmu_sy0: mmu@e6280000 {
340 compatible = "renesas,ipmmu-r8a7793",
341 "renesas,ipmmu-vmsa";
342 reg = <0 0xe6280000 0 0x1000>;
343 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
345 #iommu-cells = <1>;
346 status = "disabled";
347 };
92aa0995 348
252c8b45
MV		 349 ipmmu_sy1: mmu@e6290000 {
350 compatible = "renesas,ipmmu-r8a7793",
351 "renesas,ipmmu-vmsa";
352 reg = <0 0xe6290000 0 0x1000>;
353 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
354 #iommu-cells = <1>;
355 status = "disabled";
356 };
92aa0995 357
252c8b45
MV		 358 ipmmu_ds: mmu@e6740000 {
359 compatible = "renesas,ipmmu-r8a7793",
360 "renesas,ipmmu-vmsa";
361 reg = <0 0xe6740000 0 0x1000>;
362 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
363 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
364 #iommu-cells = <1>;
365 status = "disabled";
366 };
92aa0995 367
252c8b45
MV		 368 ipmmu_mp: mmu@ec680000 {
369 compatible = "renesas,ipmmu-r8a7793",
370 "renesas,ipmmu-vmsa";
371 reg = <0 0xec680000 0 0x1000>;
372 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
373 #iommu-cells = <1>;
374 status = "disabled";
375 };
92aa0995 376
252c8b45
MV		 377 ipmmu_mx: mmu@fe951000 {
378 compatible = "renesas,ipmmu-r8a7793",
379 "renesas,ipmmu-vmsa";
380 reg = <0 0xfe951000 0 0x1000>;
381 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
382 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
383 #iommu-cells = <1>;
384 status = "disabled";
385 };
92aa0995 386
252c8b45
MV		 387 ipmmu_rt: mmu@ffc80000 {
388 compatible = "renesas,ipmmu-r8a7793",
389 "renesas,ipmmu-vmsa";
390 reg = <0 0xffc80000 0 0x1000>;
391 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
392 #iommu-cells = <1>;
393 status = "disabled";
394 };
92aa0995 395
252c8b45
MV		 396 ipmmu_gp: mmu@e62a0000 {
397 compatible = "renesas,ipmmu-r8a7793",
398 "renesas,ipmmu-vmsa";
399 reg = <0 0xe62a0000 0 0x1000>;
400 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
402 #iommu-cells = <1>;
403 status = "disabled";
404 };
92aa0995 405
252c8b45
MV		 406 icram0: sram@e63a0000 {
407 compatible = "mmio-sram";
408 reg = <0 0xe63a0000 0 0x12000>;
409 };
92aa0995 410
252c8b45
MV		 411 icram1: sram@e63c0000 {
412 compatible = "mmio-sram";
413 reg = <0 0xe63c0000 0 0x1000>;
414 #address-cells = <1>;
415 #size-cells = <1>;
416 ranges = <0 0 0xe63c0000 0x1000>;
92aa0995 417
252c8b45
MV		 418 smp-sram@0 {
419 compatible = "renesas,smp-sram";
3b255531 420 reg = <0 0x100>;
252c8b45
MV		 421 };
422 };
92aa0995 423
252c8b45
MV		 424 /* The memory map in the User's Manual maps the cores to
425 * bus numbers
426 */
427 i2c0: i2c@e6508000 {
428 #address-cells = <1>;
429 #size-cells = <0>;
430 compatible = "renesas,i2c-r8a7793",
431 "renesas,rcar-gen2-i2c";
432 reg = <0 0xe6508000 0 0x40>;
433 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&cpg CPG_MOD 931>;
435 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
436 resets = <&cpg 931>;
437 i2c-scl-internal-delay-ns = <6>;
438 status = "disabled";
439 };
92aa0995 440
252c8b45
MV		 441 i2c1: i2c@e6518000 {
442 #address-cells = <1>;
443 #size-cells = <0>;
444 compatible = "renesas,i2c-r8a7793",
445 "renesas,rcar-gen2-i2c";
446 reg = <0 0xe6518000 0 0x40>;
447 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&cpg CPG_MOD 930>;
449 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
450 resets = <&cpg 930>;
451 i2c-scl-internal-delay-ns = <6>;
452 status = "disabled";
453 };
92aa0995 454
252c8b45
MV		 455 i2c2: i2c@e6530000 {
456 #address-cells = <1>;
457 #size-cells = <0>;
458 compatible = "renesas,i2c-r8a7793",
459 "renesas,rcar-gen2-i2c";
460 reg = <0 0xe6530000 0 0x40>;
461 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&cpg CPG_MOD 929>;
463 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
464 resets = <&cpg 929>;
465 i2c-scl-internal-delay-ns = <6>;
466 status = "disabled";
467 };
92aa0995 468
252c8b45
MV		 469 i2c3: i2c@e6540000 {
470 #address-cells = <1>;
471 #size-cells = <0>;
472 compatible = "renesas,i2c-r8a7793",
473 "renesas,rcar-gen2-i2c";
474 reg = <0 0xe6540000 0 0x40>;
475 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&cpg CPG_MOD 928>;
477 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
478 resets = <&cpg 928>;
479 i2c-scl-internal-delay-ns = <6>;
480 status = "disabled";
481 };
92aa0995 482
252c8b45
MV		 483 i2c4: i2c@e6520000 {
484 #address-cells = <1>;
485 #size-cells = <0>;
486 compatible = "renesas,i2c-r8a7793",
487 "renesas,rcar-gen2-i2c";
488 reg = <0 0xe6520000 0 0x40>;
489 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&cpg CPG_MOD 927>;
491 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
492 resets = <&cpg 927>;
493 i2c-scl-internal-delay-ns = <6>;
494 status = "disabled";
495 };
92aa0995 496
252c8b45
MV		 497 i2c5: i2c@e6528000 {
498 /* doesn't need pinmux */
499 #address-cells = <1>;
500 #size-cells = <0>;
501 compatible = "renesas,i2c-r8a7793",
502 "renesas,rcar-gen2-i2c";
503 reg = <0 0xe6528000 0 0x40>;
504 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&cpg CPG_MOD 925>;
506 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
507 resets = <&cpg 925>;
508 i2c-scl-internal-delay-ns = <110>;
509 status = "disabled";
510 };
92aa0995 511
252c8b45
MV		 512 i2c6: i2c@e60b0000 {
513 /* doesn't need pinmux */
514 #address-cells = <1>;
515 #size-cells = <0>;
516 compatible = "renesas,iic-r8a7793",
517 "renesas,rcar-gen2-iic",
518 "renesas,rmobile-iic";
519 reg = <0 0xe60b0000 0 0x425>;
520 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&cpg CPG_MOD 926>;
522 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
523 <&dmac1 0x77>, <&dmac1 0x78>;
524 dma-names = "tx", "rx", "tx", "rx";
525 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
526 resets = <&cpg 926>;
527 status = "disabled";
528 };
92aa0995 529
252c8b45
MV		 530 i2c7: i2c@e6500000 {
531 #address-cells = <1>;
532 #size-cells = <0>;
533 compatible = "renesas,iic-r8a7793",
534 "renesas,rcar-gen2-iic",
535 "renesas,rmobile-iic";
536 reg = <0 0xe6500000 0 0x425>;
537 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&cpg CPG_MOD 318>;
539 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
540 <&dmac1 0x61>, <&dmac1 0x62>;
541 dma-names = "tx", "rx", "tx", "rx";
542 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
543 resets = <&cpg 318>;
544 status = "disabled";
545 };
92aa0995 546
252c8b45
MV		 547 i2c8: i2c@e6510000 {
548 #address-cells = <1>;
549 #size-cells = <0>;
550 compatible = "renesas,iic-r8a7793",
551 "renesas,rcar-gen2-iic",
552 "renesas,rmobile-iic";
553 reg = <0 0xe6510000 0 0x425>;
554 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
555 clocks = <&cpg CPG_MOD 323>;
556 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
557 <&dmac1 0x65>, <&dmac1 0x66>;
558 dma-names = "tx", "rx", "tx", "rx";
559 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
560 resets = <&cpg 323>;
561 status = "disabled";
562 };
92aa0995 563
252c8b45
MV		 564 dmac0: dma-controller@e6700000 {
565 compatible = "renesas,dmac-r8a7793",
566 "renesas,rcar-dmac";
567 reg = <0 0xe6700000 0 0x20000>;
568 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
569 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
570 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
571 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
572 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
573 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
574 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
575 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
576 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
577 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
578 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
579 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
580 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
581 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
582 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
583 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
584 interrupt-names = "error",
585 "ch0", "ch1", "ch2", "ch3",
586 "ch4", "ch5", "ch6", "ch7",
587 "ch8", "ch9", "ch10", "ch11",
588 "ch12", "ch13", "ch14";
589 clocks = <&cpg CPG_MOD 219>;
590 clock-names = "fck";
591 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
592 resets = <&cpg 219>;
593 #dma-cells = <1>;
594 dma-channels = <15>;
595 };
92aa0995 596
252c8b45
MV		 597 dmac1: dma-controller@e6720000 {
598 compatible = "renesas,dmac-r8a7793",
599 "renesas,rcar-dmac";
600 reg = <0 0xe6720000 0 0x20000>;
601 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
602 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
603 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
604 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
605 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
606 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
607 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
608 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
609 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
610 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
611 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
612 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
613 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
614 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
615 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
616 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
617 interrupt-names = "error",
618 "ch0", "ch1", "ch2", "ch3",
619 "ch4", "ch5", "ch6", "ch7",
620 "ch8", "ch9", "ch10", "ch11",
621 "ch12", "ch13", "ch14";
622 clocks = <&cpg CPG_MOD 218>;
623 clock-names = "fck";
624 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
625 resets = <&cpg 218>;
626 #dma-cells = <1>;
627 dma-channels = <15>;
628 };
92aa0995 629
252c8b45
MV		 630 qspi: spi@e6b10000 {
631 compatible = "renesas,qspi-r8a7793", "renesas,qspi";
632 reg = <0 0xe6b10000 0 0x2c>;
633 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&cpg CPG_MOD 917>;
635 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
636 <&dmac1 0x17>, <&dmac1 0x18>;
637 dma-names = "tx", "rx", "tx", "rx";
638 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
639 resets = <&cpg 917>;
640 num-cs = <1>;
641 #address-cells = <1>;
642 #size-cells = <0>;
643 status = "disabled";
644 };
92aa0995 645
252c8b45
MV		 646 scifa0: serial@e6c40000 {
647 compatible = "renesas,scifa-r8a7793",
648 "renesas,rcar-gen2-scifa", "renesas,scifa";
649 reg = <0 0xe6c40000 0 64>;
650 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&cpg CPG_MOD 204>;
652 clock-names = "fck";
653 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
654 <&dmac1 0x21>, <&dmac1 0x22>;
655 dma-names = "tx", "rx", "tx", "rx";
656 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
657 resets = <&cpg 204>;
658 status = "disabled";
659 };
92aa0995 660
252c8b45
MV		 661 scifa1: serial@e6c50000 {
662 compatible = "renesas,scifa-r8a7793",
663 "renesas,rcar-gen2-scifa", "renesas,scifa";
664 reg = <0 0xe6c50000 0 64>;
665 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&cpg CPG_MOD 203>;
667 clock-names = "fck";
668 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
669 <&dmac1 0x25>, <&dmac1 0x26>;
670 dma-names = "tx", "rx", "tx", "rx";
671 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
672 resets = <&cpg 203>;
673 status = "disabled";
674 };
92aa0995 675
252c8b45
MV		 676 scifa2: serial@e6c60000 {
677 compatible = "renesas,scifa-r8a7793",
678 "renesas,rcar-gen2-scifa", "renesas,scifa";
679 reg = <0 0xe6c60000 0 64>;
680 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&cpg CPG_MOD 202>;
682 clock-names = "fck";
683 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
684 <&dmac1 0x27>, <&dmac1 0x28>;
685 dma-names = "tx", "rx", "tx", "rx";
686 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
687 resets = <&cpg 202>;
688 status = "disabled";
689 };
92aa0995 690
252c8b45
MV		 691 scifa3: serial@e6c70000 {
692 compatible = "renesas,scifa-r8a7793",
693 "renesas,rcar-gen2-scifa", "renesas,scifa";
694 reg = <0 0xe6c70000 0 64>;
695 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
696 clocks = <&cpg CPG_MOD 1106>;
697 clock-names = "fck";
698 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
699 <&dmac1 0x1b>, <&dmac1 0x1c>;
700 dma-names = "tx", "rx", "tx", "rx";
701 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
702 resets = <&cpg 1106>;
703 status = "disabled";
704 };
92aa0995 705
252c8b45
MV		 706 scifa4: serial@e6c78000 {
707 compatible = "renesas,scifa-r8a7793",
708 "renesas,rcar-gen2-scifa", "renesas,scifa";
709 reg = <0 0xe6c78000 0 64>;
710 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&cpg CPG_MOD 1107>;
712 clock-names = "fck";
713 dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
714 <&dmac1 0x1f>, <&dmac1 0x20>;
715 dma-names = "tx", "rx", "tx", "rx";
716 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
717 resets = <&cpg 1107>;
718 status = "disabled";
719 };
92aa0995 720
252c8b45
MV		 721 scifa5: serial@e6c80000 {
722 compatible = "renesas,scifa-r8a7793",
723 "renesas,rcar-gen2-scifa", "renesas,scifa";
724 reg = <0 0xe6c80000 0 64>;
725 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&cpg CPG_MOD 1108>;
727 clock-names = "fck";
728 dmas = <&dmac0 0x23>, <&dmac0 0x24>,
729 <&dmac1 0x23>, <&dmac1 0x24>;
730 dma-names = "tx", "rx", "tx", "rx";
731 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
732 resets = <&cpg 1108>;
733 status = "disabled";
734 };
92aa0995 735
252c8b45
MV		 736 scifb0: serial@e6c20000 {
737 compatible = "renesas,scifb-r8a7793",
738 "renesas,rcar-gen2-scifb", "renesas,scifb";
739 reg = <0 0xe6c20000 0 0x100>;
740 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&cpg CPG_MOD 206>;
742 clock-names = "fck";
743 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
744 <&dmac1 0x3d>, <&dmac1 0x3e>;
745 dma-names = "tx", "rx", "tx", "rx";
746 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
747 resets = <&cpg 206>;
748 status = "disabled";
749 };
92aa0995 750
252c8b45
MV		 751 scifb1: serial@e6c30000 {
752 compatible = "renesas,scifb-r8a7793",
753 "renesas,rcar-gen2-scifb", "renesas,scifb";
754 reg = <0 0xe6c30000 0 0x100>;
755 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
756 clocks = <&cpg CPG_MOD 207>;
757 clock-names = "fck";
758 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
759 <&dmac1 0x19>, <&dmac1 0x1a>;
760 dma-names = "tx", "rx", "tx", "rx";
761 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
762 resets = <&cpg 207>;
763 status = "disabled";
764 };
92aa0995 765
252c8b45
MV		 766 scifb2: serial@e6ce0000 {
767 compatible = "renesas,scifb-r8a7793",
768 "renesas,rcar-gen2-scifb", "renesas,scifb";
769 reg = <0 0xe6ce0000 0 0x100>;
770 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
771 clocks = <&cpg CPG_MOD 216>;
772 clock-names = "fck";
773 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
774 <&dmac1 0x1d>, <&dmac1 0x1e>;
775 dma-names = "tx", "rx", "tx", "rx";
776 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
777 resets = <&cpg 216>;
778 status = "disabled";
779 };
92aa0995 780
252c8b45
MV		 781 scif0: serial@e6e60000 {
782 compatible = "renesas,scif-r8a7793",
783 "renesas,rcar-gen2-scif", "renesas,scif";
784 reg = <0 0xe6e60000 0 64>;
785 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
787 <&scif_clk>;
788 clock-names = "fck", "brg_int", "scif_clk";
789 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
790 <&dmac1 0x29>, <&dmac1 0x2a>;
791 dma-names = "tx", "rx", "tx", "rx";
792 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
793 resets = <&cpg 721>;
794 status = "disabled";
795 };
92aa0995 796
252c8b45
MV		 797 scif1: serial@e6e68000 {
798 compatible = "renesas,scif-r8a7793",
799 "renesas,rcar-gen2-scif", "renesas,scif";
800 reg = <0 0xe6e68000 0 64>;
801 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
802 clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
803 <&scif_clk>;
804 clock-names = "fck", "brg_int", "scif_clk";
805 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
806 <&dmac1 0x2d>, <&dmac1 0x2e>;
807 dma-names = "tx", "rx", "tx", "rx";
808 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
809 resets = <&cpg 720>;
810 status = "disabled";
811 };
92aa0995 812
252c8b45
MV		 813 scif2: serial@e6e58000 {
814 compatible = "renesas,scif-r8a7793",
815 "renesas,rcar-gen2-scif", "renesas,scif";
816 reg = <0 0xe6e58000 0 64>;
817 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
819 <&scif_clk>;
820 clock-names = "fck", "brg_int", "scif_clk";
821 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
822 <&dmac1 0x2b>, <&dmac1 0x2c>;
823 dma-names = "tx", "rx", "tx", "rx";
824 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
825 resets = <&cpg 719>;
826 status = "disabled";
827 };
92aa0995 828
252c8b45
MV		 829 scif3: serial@e6ea8000 {
830 compatible = "renesas,scif-r8a7793",
831 "renesas,rcar-gen2-scif", "renesas,scif";
832 reg = <0 0xe6ea8000 0 64>;
833 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
834 clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
835 <&scif_clk>;
836 clock-names = "fck", "brg_int", "scif_clk";
837 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
838 <&dmac1 0x2f>, <&dmac1 0x30>;
839 dma-names = "tx", "rx", "tx", "rx";
840 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
841 resets = <&cpg 718>;
842 status = "disabled";
843 };
92aa0995 844
252c8b45
MV		 845 scif4: serial@e6ee0000 {
846 compatible = "renesas,scif-r8a7793",
847 "renesas,rcar-gen2-scif", "renesas,scif";
848 reg = <0 0xe6ee0000 0 64>;
849 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
851 <&scif_clk>;
852 clock-names = "fck", "brg_int", "scif_clk";
853 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
854 <&dmac1 0xfb>, <&dmac1 0xfc>;
855 dma-names = "tx", "rx", "tx", "rx";
856 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
857 resets = <&cpg 715>;
858 status = "disabled";
859 };
92aa0995 860
252c8b45
MV		 861 scif5: serial@e6ee8000 {
862 compatible = "renesas,scif-r8a7793",
863 "renesas,rcar-gen2-scif", "renesas,scif";
864 reg = <0 0xe6ee8000 0 64>;
865 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
866 clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
867 <&scif_clk>;
868 clock-names = "fck", "brg_int", "scif_clk";
869 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
870 <&dmac1 0xfd>, <&dmac1 0xfe>;
871 dma-names = "tx", "rx", "tx", "rx";
872 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
873 resets = <&cpg 714>;
874 status = "disabled";
875 };
92aa0995 876
252c8b45
MV		 877 hscif0: serial@e62c0000 {
878 compatible = "renesas,hscif-r8a7793",
879 "renesas,rcar-gen2-hscif", "renesas,hscif";
880 reg = <0 0xe62c0000 0 96>;
881 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
882 clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
883 <&scif_clk>;
884 clock-names = "fck", "brg_int", "scif_clk";
885 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
886 <&dmac1 0x39>, <&dmac1 0x3a>;
887 dma-names = "tx", "rx", "tx", "rx";
888 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
889 resets = <&cpg 717>;
890 status = "disabled";
891 };
92aa0995 892
252c8b45
MV		 893 hscif1: serial@e62c8000 {
894 compatible = "renesas,hscif-r8a7793",
895 "renesas,rcar-gen2-hscif", "renesas,hscif";
896 reg = <0 0xe62c8000 0 96>;
897 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
899 <&scif_clk>;
900 clock-names = "fck", "brg_int", "scif_clk";
901 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
902 <&dmac1 0x4d>, <&dmac1 0x4e>;
903 dma-names = "tx", "rx", "tx", "rx";
904 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
905 resets = <&cpg 716>;
906 status = "disabled";
907 };
92aa0995 908
252c8b45
MV		 909 hscif2: serial@e62d0000 {
910 compatible = "renesas,hscif-r8a7793",
911 "renesas,rcar-gen2-hscif", "renesas,hscif";
912 reg = <0 0xe62d0000 0 96>;
913 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
914 clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
915 <&scif_clk>;
916 clock-names = "fck", "brg_int", "scif_clk";
917 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
918 <&dmac1 0x3b>, <&dmac1 0x3c>;
919 dma-names = "tx", "rx", "tx", "rx";
920 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
921 resets = <&cpg 713>;
922 status = "disabled";
92aa0995 923 };
92aa0995 924
252c8b45
MV		 925 can0: can@e6e80000 {
926 compatible = "renesas,can-r8a7793",
927 "renesas,rcar-gen2-can";
928 reg = <0 0xe6e80000 0 0x1000>;
929 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
930 clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>,
931 <&can_clk>;
932 clock-names = "clkp1", "clkp2", "can_clk";
933 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
934 resets = <&cpg 916>;
935 status = "disabled";
936 };
92aa0995 937
252c8b45
MV		 938 can1: can@e6e88000 {
939 compatible = "renesas,can-r8a7793",
940 "renesas,rcar-gen2-can";
941 reg = <0 0xe6e88000 0 0x1000>;
942 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
943 clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>,
944 <&can_clk>;
945 clock-names = "clkp1", "clkp2", "can_clk";
946 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
947 resets = <&cpg 915>;
948 status = "disabled";
949 };
92aa0995 950
252c8b45
MV		 951 vin0: video@e6ef0000 {
952 compatible = "renesas,vin-r8a7793",
953 "renesas,rcar-gen2-vin";
954 reg = <0 0xe6ef0000 0 0x1000>;
955 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
956 clocks = <&cpg CPG_MOD 811>;
957 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
958 resets = <&cpg 811>;
959 status = "disabled";
960 };
92aa0995 961
252c8b45
MV		 962 vin1: video@e6ef1000 {
963 compatible = "renesas,vin-r8a7793",
964 "renesas,rcar-gen2-vin";
965 reg = <0 0xe6ef1000 0 0x1000>;
966 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
967 clocks = <&cpg CPG_MOD 810>;
968 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
969 resets = <&cpg 810>;
970 status = "disabled";
971 };
92aa0995 972
252c8b45
MV		 973 vin2: video@e6ef2000 {
974 compatible = "renesas,vin-r8a7793",
975 "renesas,rcar-gen2-vin";
976 reg = <0 0xe6ef2000 0 0x1000>;
977 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
978 clocks = <&cpg CPG_MOD 809>;
979 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
980 resets = <&cpg 809>;
981 status = "disabled";
982 };
92aa0995 983
252c8b45
MV		 984 rcar_sound: sound@ec500000 {
985 /*
986 * #sound-dai-cells is required
987 *
988 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
989 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
990 */
991 compatible = "renesas,rcar_sound-r8a7793",
992 "renesas,rcar_sound-gen2";
993 reg = <0 0xec500000 0 0x1000>, /* SCU */
994 <0 0xec5a0000 0 0x100>, /* ADG */
995 <0 0xec540000 0 0x1000>, /* SSIU */
996 <0 0xec541000 0 0x280>, /* SSI */
997 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
998 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
999
1000 clocks = <&cpg CPG_MOD 1005>,
1001 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1002 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1003 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1004 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1005 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1006 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1007 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1008 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1009 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1010 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1011 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1012 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
1013 <&cpg CPG_CORE R8A7793_CLK_M2>;
1014 clock-names = "ssi-all",
1015 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1016 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1017 "ssi.1", "ssi.0",
1018 "src.9", "src.8", "src.7", "src.6",
1019 "src.5", "src.4", "src.3", "src.2",
1020 "src.1", "src.0",
1021 "dvc.0", "dvc.1",
1022 "clk_a", "clk_b", "clk_c", "clk_i";
1023 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1024 resets = <&cpg 1005>,
1025 <&cpg 1006>, <&cpg 1007>,
1026 <&cpg 1008>, <&cpg 1009>,
1027 <&cpg 1010>, <&cpg 1011>,
1028 <&cpg 1012>, <&cpg 1013>,
1029 <&cpg 1014>, <&cpg 1015>;
1030 reset-names = "ssi-all",
1031 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1032 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1033 "ssi.1", "ssi.0";
1034
1035 status = "disabled";
1036
1037 rcar_sound,dvc {
1038 dvc0: dvc-0 {
1039 dmas = <&audma1 0xbc>;
1040 dma-names = "tx";
1041 };
1042 dvc1: dvc-1 {
1043 dmas = <&audma1 0xbe>;
1044 dma-names = "tx";
1045 };
1046 };
92aa0995 1047
252c8b45
MV		 1048 rcar_sound,src {
1049 src0: src-0 {
1050 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1051 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1052 dma-names = "rx", "tx";
1053 };
1054 src1: src-1 {
1055 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1056 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1057 dma-names = "rx", "tx";
1058 };
1059 src2: src-2 {
1060 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1061 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1062 dma-names = "rx", "tx";
1063 };
1064 src3: src-3 {
1065 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1066 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1067 dma-names = "rx", "tx";
1068 };
1069 src4: src-4 {
1070 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1071 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1072 dma-names = "rx", "tx";
1073 };
1074 src5: src-5 {
1075 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1076 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1077 dma-names = "rx", "tx";
1078 };
1079 src6: src-6 {
1080 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1081 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1082 dma-names = "rx", "tx";
1083 };
1084 src7: src-7 {
1085 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1086 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1087 dma-names = "rx", "tx";
1088 };
1089 src8: src-8 {
1090 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1091 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1092 dma-names = "rx", "tx";
1093 };
1094 src9: src-9 {
1095 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1096 dmas = <&audma0 0x97>, <&audma1 0xba>;
1097 dma-names = "rx", "tx";
92aa0995
MV		 1098 };
1099 };
252c8b45
MV		 1100
1101 rcar_sound,ssi {
1102 ssi0: ssi-0 {
1103 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1104 dmas = <&audma0 0x01>, <&audma1 0x02>,
1105 <&audma0 0x15>, <&audma1 0x16>;
1106 dma-names = "rx", "tx", "rxu", "txu";
1107 };
1108 ssi1: ssi-1 {
1109 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1110 dmas = <&audma0 0x03>, <&audma1 0x04>,
1111 <&audma0 0x49>, <&audma1 0x4a>;
1112 dma-names = "rx", "tx", "rxu", "txu";
1113 };
1114 ssi2: ssi-2 {
1115 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1116 dmas = <&audma0 0x05>, <&audma1 0x06>,
1117 <&audma0 0x63>, <&audma1 0x64>;
1118 dma-names = "rx", "tx", "rxu", "txu";
1119 };
1120 ssi3: ssi-3 {
1121 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1122 dmas = <&audma0 0x07>, <&audma1 0x08>,
1123 <&audma0 0x6f>, <&audma1 0x70>;
1124 dma-names = "rx", "tx", "rxu", "txu";
1125 };
1126 ssi4: ssi-4 {
1127 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1128 dmas = <&audma0 0x09>, <&audma1 0x0a>,
1129 <&audma0 0x71>, <&audma1 0x72>;
1130 dma-names = "rx", "tx", "rxu", "txu";
1131 };
1132 ssi5: ssi-5 {
1133 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1134 dmas = <&audma0 0x0b>, <&audma1 0x0c>,
1135 <&audma0 0x73>, <&audma1 0x74>;
1136 dma-names = "rx", "tx", "rxu", "txu";
1137 };
1138 ssi6: ssi-6 {
1139 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1140 dmas = <&audma0 0x0d>, <&audma1 0x0e>,
1141 <&audma0 0x75>, <&audma1 0x76>;
1142 dma-names = "rx", "tx", "rxu", "txu";
1143 };
1144 ssi7: ssi-7 {
1145 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1146 dmas = <&audma0 0x0f>, <&audma1 0x10>,
1147 <&audma0 0x79>, <&audma1 0x7a>;
1148 dma-names = "rx", "tx", "rxu", "txu";
1149 };
1150 ssi8: ssi-8 {
1151 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1152 dmas = <&audma0 0x11>, <&audma1 0x12>,
1153 <&audma0 0x7b>, <&audma1 0x7c>;
1154 dma-names = "rx", "tx", "rxu", "txu";
1155 };
1156 ssi9: ssi-9 {
1157 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1158 dmas = <&audma0 0x13>, <&audma1 0x14>,
1159 <&audma0 0x7d>, <&audma1 0x7e>;
1160 dma-names = "rx", "tx", "rxu", "txu";
92aa0995
MV		 1161 };
1162 };
1163 };
92aa0995 1164
252c8b45
MV		 1165 audma0: dma-controller@ec700000 {
1166 compatible = "renesas,dmac-r8a7793",
1167 "renesas,rcar-dmac";
1168 reg = <0 0xec700000 0 0x10000>;
1169 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
1170 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
1171 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
1172 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
1173 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
1174 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
1175 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
1176 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
1177 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
1178 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
1179 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
1180 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
1181 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
1182 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1183 interrupt-names = "error",
1184 "ch0", "ch1", "ch2", "ch3",
1185 "ch4", "ch5", "ch6", "ch7",
1186 "ch8", "ch9", "ch10", "ch11",
1187 "ch12";
1188 clocks = <&cpg CPG_MOD 502>;
1189 clock-names = "fck";
1190 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1191 resets = <&cpg 502>;
1192 #dma-cells = <1>;
1193 dma-channels = <13>;
1194 };
92aa0995 1195
252c8b45
MV		 1196 audma1: dma-controller@ec720000 {
1197 compatible = "renesas,dmac-r8a7793",
1198 "renesas,rcar-dmac";
1199 reg = <0 0xec720000 0 0x10000>;
1200 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
1201 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
1202 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
1203 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
1204 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
1205 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
1206 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
1207 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
1208 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
1209 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
1210 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
1211 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
1212 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
1213 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
1214 interrupt-names = "error",
1215 "ch0", "ch1", "ch2", "ch3",
1216 "ch4", "ch5", "ch6", "ch7",
1217 "ch8", "ch9", "ch10", "ch11",
1218 "ch12";
1219 clocks = <&cpg CPG_MOD 501>;
1220 clock-names = "fck";
1221 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1222 resets = <&cpg 501>;
1223 #dma-cells = <1>;
1224 dma-channels = <13>;
1225 };
92aa0995 1226
252c8b45
MV		 1227 sdhi0: sd@ee100000 {
1228 compatible = "renesas,sdhi-r8a7793",
1229 "renesas,rcar-gen2-sdhi";
1230 reg = <0 0xee100000 0 0x328>;
1231 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1232 clocks = <&cpg CPG_MOD 314>;
1233 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
1234 <&dmac1 0xcd>, <&dmac1 0xce>;
1235 dma-names = "tx", "rx", "tx", "rx";
1236 max-frequency = <195000000>;
1237 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1238 resets = <&cpg 314>;
1239 status = "disabled";
1240 };
92aa0995 1241
252c8b45
MV		 1242 sdhi1: sd@ee140000 {
1243 compatible = "renesas,sdhi-r8a7793",
1244 "renesas,rcar-gen2-sdhi";
1245 reg = <0 0xee140000 0 0x100>;
1246 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1247 clocks = <&cpg CPG_MOD 312>;
1248 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
1249 <&dmac1 0xc1>, <&dmac1 0xc2>;
1250 dma-names = "tx", "rx", "tx", "rx";
1251 max-frequency = <97500000>;
1252 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1253 resets = <&cpg 312>;
1254 status = "disabled";
1255 };
92aa0995 1256
252c8b45
MV		 1257 sdhi2: sd@ee160000 {
1258 compatible = "renesas,sdhi-r8a7793",
1259 "renesas,rcar-gen2-sdhi";
1260 reg = <0 0xee160000 0 0x100>;
1261 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1262 clocks = <&cpg CPG_MOD 311>;
1263 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
1264 <&dmac1 0xd3>, <&dmac1 0xd4>;
1265 dma-names = "tx", "rx", "tx", "rx";
1266 max-frequency = <97500000>;
1267 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1268 resets = <&cpg 311>;
1269 status = "disabled";
1270 };
92aa0995 1271
252c8b45
MV		 1272 mmcif0: mmc@ee200000 {
1273 compatible = "renesas,mmcif-r8a7793",
1274 "renesas,sh-mmcif";
1275 reg = <0 0xee200000 0 0x80>;
1276 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
1277 clocks = <&cpg CPG_MOD 315>;
1278 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
1279 <&dmac1 0xd1>, <&dmac1 0xd2>;
1280 dma-names = "tx", "rx", "tx", "rx";
1281 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1282 resets = <&cpg 315>;
1283 reg-io-width = <4>;
1284 status = "disabled";
1285 max-frequency = <97500000>;
1286 };
92aa0995 1287
252c8b45
MV		 1288 ether: ethernet@ee700000 {
1289 compatible = "renesas,ether-r8a7793",
1290 "renesas,rcar-gen2-ether";
1291 reg = <0 0xee700000 0 0x400>;
1292 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1293 clocks = <&cpg CPG_MOD 813>;
1294 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1295 resets = <&cpg 813>;
1296 phy-mode = "rmii";
1297 #address-cells = <1>;
1298 #size-cells = <0>;
1299 status = "disabled";
1300 };
92aa0995 1301
252c8b45
MV		 1302 gic: interrupt-controller@f1001000 {
1303 compatible = "arm,gic-400";
1304 #interrupt-cells = <3>;
1305 #address-cells = <0>;
1306 interrupt-controller;
1307 reg = <0 0xf1001000 0 0x1000>,
1308 <0 0xf1002000 0 0x2000>,
1309 <0 0xf1004000 0 0x2000>,
1310 <0 0xf1006000 0 0x2000>;
1311 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
1312 clocks = <&cpg CPG_MOD 408>;
1313 clock-names = "clk";
1314 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1315 resets = <&cpg 408>;
1316 };
92aa0995 1317
3b255531
MV		 1318 fdp1@fe940000 {
1319 compatible = "renesas,fdp1";
1320 reg = <0 0xfe940000 0 0x2400>;
1321 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
1322 clocks = <&cpg CPG_MOD 119>;
1323 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1324 resets = <&cpg 119>;
1325 };
1326
1327 fdp1@fe944000 {
1328 compatible = "renesas,fdp1";
1329 reg = <0 0xfe944000 0 0x2400>;
1330 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1331 clocks = <&cpg CPG_MOD 118>;
1332 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1333 resets = <&cpg 118>;
1334 };
1335
252c8b45
MV		 1336 du: display@feb00000 {
1337 compatible = "renesas,du-r8a7793";
1338 reg = <0 0xfeb00000 0 0x40000>;
1339 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1341 clocks = <&cpg CPG_MOD 724>,
1342 <&cpg CPG_MOD 723>;
1343 clock-names = "du.0", "du.1";
1344 status = "disabled";
1345
1346 ports {
1347 #address-cells = <1>;
1348 #size-cells = <0>;
1349
1350 port@0 {
1351 reg = <0>;
1352 du_out_rgb: endpoint {
1353 };
1354 };
1355 port@1 {
1356 reg = <1>;
1357 du_out_lvds0: endpoint {
1358 remote-endpoint = <&lvds0_in>;
1359 };
1360 };
1361 };
1362 };
92aa0995 1363
252c8b45
MV		 1364 lvds0: lvds@feb90000 {
1365 compatible = "renesas,r8a7793-lvds";
1366 reg = <0 0xfeb90000 0 0x1c>;
1367 clocks = <&cpg CPG_MOD 726>;
1368 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1369 resets = <&cpg 726>;
92aa0995 1370
252c8b45 1371 status = "disabled";
92aa0995 1372
252c8b45
MV		 1373 ports {
1374 #address-cells = <1>;
1375 #size-cells = <0>;
92aa0995 1376
252c8b45
MV		 1377 port@0 {
1378 reg = <0>;
1379 lvds0_in: endpoint {
1380 remote-endpoint = <&du_out_lvds0>;
1381 };
1382 };
1383 port@1 {
1384 reg = <1>;
1385 lvds0_out: endpoint {
1386 };
1387 };
1388 };
1389 };
92aa0995 1390
252c8b45
MV		 1391 prr: chipid@ff000044 {
1392 compatible = "renesas,prr";
1393 reg = <0 0xff000044 0 4>;
1394 };
92aa0995 1395
252c8b45
MV		 1396 cmt0: timer@ffca0000 {
1397 compatible = "renesas,r8a7793-cmt0",
1398 "renesas,rcar-gen2-cmt0";
1399 reg = <0 0xffca0000 0 0x1004>;
1400 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1401 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1402 clocks = <&cpg CPG_MOD 124>;
1403 clock-names = "fck";
1404 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1405 resets = <&cpg 124>;
1406
1407 status = "disabled";
1408 };
92aa0995 1409
252c8b45
MV		 1410 cmt1: timer@e6130000 {
1411 compatible = "renesas,r8a7793-cmt1",
1412 "renesas,rcar-gen2-cmt1";
1413 reg = <0 0xe6130000 0 0x1004>;
1414 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1415 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1416 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1417 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1418 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1419 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1420 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1421 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1422 clocks = <&cpg CPG_MOD 329>;
1423 clock-names = "fck";
1424 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1425 resets = <&cpg 329>;
1426
1427 status = "disabled";
1428 };
92aa0995
MV		 1429 };
1430
252c8b45
MV		 1431 thermal-zones {
1432 cpu_thermal: cpu-thermal {
1433 polling-delay-passive = <0>;
1434 polling-delay = <0>;
92aa0995 1435
252c8b45 1436 thermal-sensors = <&thermal>;
92aa0995 1437
252c8b45
MV		 1438 trips {
1439 cpu-crit {
1440 temperature = <95000>;
1441 hysteresis = <0>;
1442 type = "critical";
1443 };
92aa0995 1444 };
252c8b45 1445 cooling-maps {
92aa0995
MV		 1446 };
1447 };
252c8b45 1448 };
92aa0995 1449
252c8b45
MV		 1450 timer {
1451 compatible = "arm,armv7-timer";
1452 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1453 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1454 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1455 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1456 };
92aa0995 1457
252c8b45
MV		 1458 /* External USB clock - can be overridden by the board */
1459 usb_extal_clk: usb_extal {
1460 compatible = "fixed-clock";
1461 #clock-cells = <0>;
1462 clock-frequency = <48000000>;
92aa0995
MV		 1463 };
1464};
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