projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 0442ed86 | 1 | /*----------------------------------------------------------------------------+ |
| 31773496 JB |
2 | | This source code is dual-licensed. You may use it under the terms of the |
| 3 | | GNU General Public License version 2, or under the license below. | |
| 0442ed86 | 4 | | |
| 53677ef1 WD |
5 | | This source code has been made available to you by IBM on an AS-IS |
| 6 | | basis. Anyone receiving this source is licensed under IBM | |
| 7 | | copyrights to use it in any way he or she deems fit, including | |
| 8 | | copying it, modifying it, compiling it, and redistributing it either | |
| 9 | | with or without modifications. No license under IBM patents or | |
| 10 | | patent applications is to be implied by the copyright license. | |
| 0442ed86 | 11 | | |
| 53677ef1 WD |
12 | | Any user of this software should understand that IBM cannot provide |
| 13 | | technical support for this software and will not be responsible for | |
| 14 | | any consequences resulting from the use of this software. | |
| 0442ed86 | 15 | | |
| 53677ef1 WD |
16 | | Any person who transfers this source code or any derivative work |
| 17 | | must include the IBM copyright notice, this paragraph, and the | |
| 18 | | preceding two paragraphs in the transferred software. | |
| 0442ed86 | 19 | | |
| 53677ef1 WD |
20 | | COPYRIGHT I B M CORPORATION 1999 |
| 21 | | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M | |
| 0442ed86 WD |
22 | +----------------------------------------------------------------------------*/ |
| 23 | ||
| 24 | #ifndef __PPC405_H__ | |
| 25 | #define __PPC405_H__ | |
| 26 | ||
| c821b5f1 GE |
27 | /* Define bits and masks for real-mode storage attribute control registers */ |
| 28 | #define PPC_128MB_SACR_BIT(addr) ((addr) >> 27) | |
| 29 | #define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1) | |
| 30 | ||
| 9b94ac61 | 31 | #ifndef CONFIG_IOP480 |
| dbcc3571 | 32 | #define CONFIG_SYS_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */ |
| 9b94ac61 | 33 | #else |
| dbcc3571 | 34 | #define CONFIG_SYS_DCACHE_SIZE (2 << 10) /* For PLX IOP480(403)*/ |
| 9b94ac61 SR |
35 | #endif |
| 36 | ||
| 0442ed86 WD |
37 | /****************************************************************************** |
| 38 | * Special for PPC405GP | |
| 39 | ******************************************************************************/ | |
| 40 | ||
| 41 | /****************************************************************************** | |
| 42 | * DMA | |
| 43 | ******************************************************************************/ | |
| 44 | #define DMA_DCR_BASE 0x100 | |
| d1c3b275 SR |
45 | #define DMACR0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ |
| 46 | #define DMACT0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ | |
| 47 | #define DMADA0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */ | |
| 48 | #define DMASA0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */ | |
| 49 | #define DMASB0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */ | |
| 50 | #define DMACR1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ | |
| 51 | #define DMACT1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ | |
| 52 | #define DMADA1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */ | |
| 53 | #define DMASA1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */ | |
| 54 | #define DMASB1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */ | |
| 55 | #define DMACR2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ | |
| 56 | #define DMACT2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ | |
| 57 | #define DMADA2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */ | |
| 58 | #define DMASA2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */ | |
| 59 | #define DMASB2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */ | |
| 60 | #define DMACR3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */ | |
| 61 | #define DMACT3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */ | |
| 62 | #define DMADA3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */ | |
| 63 | #define DMASA3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */ | |
| 64 | #define DMASB3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */ | |
| 65 | #define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */ | |
| 66 | #define DMASGC (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ | |
| 67 | #define DMAADR (DMA_DCR_BASE+0x24) /* DMA address decode register */ | |
| 0442ed86 | 68 | |
| e075fbe6 | 69 | #ifndef CONFIG_405EP |
| 0442ed86 WD |
70 | /****************************************************************************** |
| 71 | * Decompression Controller | |
| 72 | ******************************************************************************/ | |
| 73 | #define DECOMP_DCR_BASE 0x14 | |
| dbcc3571 NG |
74 | #define KIAR (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */ |
| 75 | #define KIDR (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */ | |
| d1c3b275 | 76 | /* values for kiar register - indirect addressing of these regs */ |
| dbcc3571 | 77 | #define KCONF 0x40 /* decompression core config register */ |
| e075fbe6 | 78 | #endif |
| 0442ed86 WD |
79 | |
| 80 | /****************************************************************************** | |
| 81 | * Power Management | |
| 82 | ******************************************************************************/ | |
| dbbd1257 SR |
83 | #ifdef CONFIG_405EX |
| 84 | #define POWERMAN_DCR_BASE 0xb0 | |
| 85 | #else | |
| 0442ed86 | 86 | #define POWERMAN_DCR_BASE 0xb8 |
| dbbd1257 | 87 | #endif |
| dbcc3571 NG |
88 | #define CPMSR (POWERMAN_DCR_BASE+0x0) /* Power management status */ |
| 89 | #define CPMER (POWERMAN_DCR_BASE+0x1) /* Power management enable */ | |
| 90 | #define CPMFR (POWERMAN_DCR_BASE+0x2) /* Power management force */ | |
| 0442ed86 WD |
91 | |
| 92 | /****************************************************************************** | |
| 93 | * Extrnal Bus Controller | |
| 94 | ******************************************************************************/ | |
| d1c3b275 | 95 | /* values for EBC0_CFGADDR register - indirect addressing of these regs */ |
| dbcc3571 NG |
96 | #define PB0CR 0x00 /* periph bank 0 config reg */ |
| 97 | #define PB1CR 0x01 /* periph bank 1 config reg */ | |
| 98 | #define PB2CR 0x02 /* periph bank 2 config reg */ | |
| 99 | #define PB3CR 0x03 /* periph bank 3 config reg */ | |
| 100 | #define PB4CR 0x04 /* periph bank 4 config reg */ | |
| e075fbe6 | 101 | #ifndef CONFIG_405EP |
| dbcc3571 NG |
102 | #define PB5CR 0x05 /* periph bank 5 config reg */ |
| 103 | #define PB6CR 0x06 /* periph bank 6 config reg */ | |
| 104 | #define PB7CR 0x07 /* periph bank 7 config reg */ | |
| e075fbe6 | 105 | #endif |
| dbcc3571 NG |
106 | #define PB0AP 0x10 /* periph bank 0 access parameters */ |
| 107 | #define PB1AP 0x11 /* periph bank 1 access parameters */ | |
| 108 | #define PB2AP 0x12 /* periph bank 2 access parameters */ | |
| 109 | #define PB3AP 0x13 /* periph bank 3 access parameters */ | |
| 110 | #define PB4AP 0x14 /* periph bank 4 access parameters */ | |
| e075fbe6 | 111 | #ifndef CONFIG_405EP |
| dbcc3571 NG |
112 | #define PB5AP 0x15 /* periph bank 5 access parameters */ |
| 113 | #define PB6AP 0x16 /* periph bank 6 access parameters */ | |
| 114 | #define PB7AP 0x17 /* periph bank 7 access parameters */ | |
| e075fbe6 | 115 | #endif |
| dbcc3571 NG |
116 | #define PBEAR 0x20 /* periph bus error addr reg */ |
| 117 | #define PBESR0 0x21 /* periph bus error status reg 0 */ | |
| 118 | #define PBESR1 0x22 /* periph bus error status reg 1 */ | |
| 119 | #define EBC0_CFG 0x23 /* external bus configuration reg */ | |
| 0442ed86 | 120 | |
| b867d705 SR |
121 | #ifdef CONFIG_405EP |
| 122 | /****************************************************************************** | |
| 123 | * Control | |
| 124 | ******************************************************************************/ | |
| 125 | #define CNTRL_DCR_BASE 0x0f0 | |
| dbcc3571 NG |
126 | #define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ |
| 127 | #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Clock status register */ | |
| 128 | #define CPC0_EPCTL (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ | |
| 129 | #define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ | |
| 130 | #define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART control register */ | |
| 131 | #define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI control register */ | |
| 132 | ||
| 133 | #define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ | |
| 134 | #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ | |
| 135 | #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ | |
| 136 | #define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */ | |
| 137 | #define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ | |
| 138 | #define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ | |
| 139 | #define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ | |
| 140 | #define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ | |
| 141 | #define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ | |
| 142 | #define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ | |
| b867d705 SR |
143 | |
| 144 | /* Bit definitions */ | |
| 53677ef1 WD |
145 | #define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */ |
| 146 | #define PLLMR0_CPU_DIV_BYPASS 0x00000000 | |
| 147 | #define PLLMR0_CPU_DIV_2 0x00100000 | |
| 148 | #define PLLMR0_CPU_DIV_3 0x00200000 | |
| 149 | #define PLLMR0_CPU_DIV_4 0x00300000 | |
| 150 | ||
| 151 | #define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */ | |
| 152 | #define PLLMR0_CPU_PLB_DIV_1 0x00000000 | |
| 153 | #define PLLMR0_CPU_PLB_DIV_2 0x00010000 | |
| 154 | #define PLLMR0_CPU_PLB_DIV_3 0x00020000 | |
| 155 | #define PLLMR0_CPU_PLB_DIV_4 0x00030000 | |
| 156 | ||
| 157 | #define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */ | |
| 158 | #define PLLMR0_OPB_PLB_DIV_1 0x00000000 | |
| 159 | #define PLLMR0_OPB_PLB_DIV_2 0x00001000 | |
| 160 | #define PLLMR0_OPB_PLB_DIV_3 0x00002000 | |
| 161 | #define PLLMR0_OPB_PLB_DIV_4 0x00003000 | |
| 162 | ||
| dbcc3571 | 163 | #define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */ |
| 53677ef1 WD |
164 | #define PLLMR0_EXB_PLB_DIV_2 0x00000000 |
| 165 | #define PLLMR0_EXB_PLB_DIV_3 0x00000100 | |
| 166 | #define PLLMR0_EXB_PLB_DIV_4 0x00000200 | |
| 167 | #define PLLMR0_EXB_PLB_DIV_5 0x00000300 | |
| 168 | ||
| dbcc3571 | 169 | #define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */ |
| 53677ef1 WD |
170 | #define PLLMR0_MAL_PLB_DIV_1 0x00000000 |
| 171 | #define PLLMR0_MAL_PLB_DIV_2 0x00000010 | |
| 172 | #define PLLMR0_MAL_PLB_DIV_3 0x00000020 | |
| 173 | #define PLLMR0_MAL_PLB_DIV_4 0x00000030 | |
| 174 | ||
| 175 | #define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */ | |
| 176 | #define PLLMR0_PCI_PLB_DIV_1 0x00000000 | |
| 177 | #define PLLMR0_PCI_PLB_DIV_2 0x00000001 | |
| 178 | #define PLLMR0_PCI_PLB_DIV_3 0x00000002 | |
| 179 | #define PLLMR0_PCI_PLB_DIV_4 0x00000003 | |
| 180 | ||
| 181 | #define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */ | |
| 182 | #define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */ | |
| dbcc3571 | 183 | #define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */ |
| 53677ef1 WD |
184 | #define PLLMR1_FBMUL_DIV_16 0x00000000 |
| 185 | #define PLLMR1_FBMUL_DIV_1 0x00100000 | |
| 186 | #define PLLMR1_FBMUL_DIV_2 0x00200000 | |
| 187 | #define PLLMR1_FBMUL_DIV_3 0x00300000 | |
| 188 | #define PLLMR1_FBMUL_DIV_4 0x00400000 | |
| 189 | #define PLLMR1_FBMUL_DIV_5 0x00500000 | |
| 190 | #define PLLMR1_FBMUL_DIV_6 0x00600000 | |
| 191 | #define PLLMR1_FBMUL_DIV_7 0x00700000 | |
| 192 | #define PLLMR1_FBMUL_DIV_8 0x00800000 | |
| 193 | #define PLLMR1_FBMUL_DIV_9 0x00900000 | |
| 194 | #define PLLMR1_FBMUL_DIV_10 0x00A00000 | |
| 195 | #define PLLMR1_FBMUL_DIV_11 0x00B00000 | |
| 196 | #define PLLMR1_FBMUL_DIV_12 0x00C00000 | |
| 197 | #define PLLMR1_FBMUL_DIV_13 0x00D00000 | |
| 198 | #define PLLMR1_FBMUL_DIV_14 0x00E00000 | |
| 199 | #define PLLMR1_FBMUL_DIV_15 0x00F00000 | |
| 200 | ||
| dbcc3571 | 201 | #define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */ |
| 53677ef1 WD |
202 | #define PLLMR1_FWDVA_DIV_8 0x00000000 |
| 203 | #define PLLMR1_FWDVA_DIV_7 0x00010000 | |
| 204 | #define PLLMR1_FWDVA_DIV_6 0x00020000 | |
| 205 | #define PLLMR1_FWDVA_DIV_5 0x00030000 | |
| 206 | #define PLLMR1_FWDVA_DIV_4 0x00040000 | |
| 207 | #define PLLMR1_FWDVA_DIV_3 0x00050000 | |
| 208 | #define PLLMR1_FWDVA_DIV_2 0x00060000 | |
| 209 | #define PLLMR1_FWDVA_DIV_1 0x00070000 | |
| dbcc3571 NG |
210 | #define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */ |
| 211 | #define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */ | |
| b867d705 SR |
212 | |
| 213 | /* Defines for CPC0_EPRCSR register */ | |
| dbcc3571 NG |
214 | #define CPC0_EPRCSR_E0NFE 0x80000000 |
| 215 | #define CPC0_EPRCSR_E1NFE 0x40000000 | |
| 216 | #define CPC0_EPRCSR_E1RPP 0x00000080 | |
| 217 | #define CPC0_EPRCSR_E0RPP 0x00000040 | |
| 218 | #define CPC0_EPRCSR_E1ERP 0x00000020 | |
| 219 | #define CPC0_EPRCSR_E0ERP 0x00000010 | |
| 220 | #define CPC0_EPRCSR_E1PCI 0x00000002 | |
| 221 | #define CPC0_EPRCSR_E0PCI 0x00000001 | |
| b867d705 SR |
222 | |
| 223 | /* Defines for CPC0_PCI Register */ | |
| dbcc3571 NG |
224 | #define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */ |
| 225 | #define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */ | |
| 226 | #define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled */ | |
| b867d705 SR |
227 | |
| 228 | /* Defines for CPC0_BOOR Register */ | |
| dbcc3571 | 229 | #define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */ |
| b867d705 SR |
230 | |
| 231 | /* Defines for CPC0_PLLMR1 Register fields */ | |
| dbcc3571 NG |
232 | #define PLL_ACTIVE 0x80000000 |
| 233 | #define CPC0_PLLMR1_SSCS 0x80000000 | |
| 234 | #define PLL_RESET 0x40000000 | |
| 235 | #define CPC0_PLLMR1_PLLR 0x40000000 | |
| 236 | /* Feedback multiplier */ | |
| 237 | #define PLL_FBKDIV 0x00F00000 | |
| 238 | #define CPC0_PLLMR1_FBDV 0x00F00000 | |
| 239 | #define PLL_FBKDIV_16 0x00000000 | |
| 240 | #define PLL_FBKDIV_1 0x00100000 | |
| 241 | #define PLL_FBKDIV_2 0x00200000 | |
| 242 | #define PLL_FBKDIV_3 0x00300000 | |
| 243 | #define PLL_FBKDIV_4 0x00400000 | |
| 244 | #define PLL_FBKDIV_5 0x00500000 | |
| 245 | #define PLL_FBKDIV_6 0x00600000 | |
| 246 | #define PLL_FBKDIV_7 0x00700000 | |
| 247 | #define PLL_FBKDIV_8 0x00800000 | |
| 248 | #define PLL_FBKDIV_9 0x00900000 | |
| 249 | #define PLL_FBKDIV_10 0x00A00000 | |
| 250 | #define PLL_FBKDIV_11 0x00B00000 | |
| 251 | #define PLL_FBKDIV_12 0x00C00000 | |
| 252 | #define PLL_FBKDIV_13 0x00D00000 | |
| 253 | #define PLL_FBKDIV_14 0x00E00000 | |
| 254 | #define PLL_FBKDIV_15 0x00F00000 | |
| 255 | /* Forward A divisor */ | |
| 256 | #define PLL_FWDDIVA 0x00070000 | |
| 257 | #define CPC0_PLLMR1_FWDVA 0x00070000 | |
| 258 | #define PLL_FWDDIVA_8 0x00000000 | |
| 259 | #define PLL_FWDDIVA_7 0x00010000 | |
| 260 | #define PLL_FWDDIVA_6 0x00020000 | |
| 261 | #define PLL_FWDDIVA_5 0x00030000 | |
| 262 | #define PLL_FWDDIVA_4 0x00040000 | |
| 263 | #define PLL_FWDDIVA_3 0x00050000 | |
| 264 | #define PLL_FWDDIVA_2 0x00060000 | |
| 265 | #define PLL_FWDDIVA_1 0x00070000 | |
| 266 | /* Forward B divisor */ | |
| 267 | #define PLL_FWDDIVB 0x00007000 | |
| 268 | #define CPC0_PLLMR1_FWDVB 0x00007000 | |
| 269 | #define PLL_FWDDIVB_8 0x00000000 | |
| 270 | #define PLL_FWDDIVB_7 0x00001000 | |
| 271 | #define PLL_FWDDIVB_6 0x00002000 | |
| 272 | #define PLL_FWDDIVB_5 0x00003000 | |
| 273 | #define PLL_FWDDIVB_4 0x00004000 | |
| 274 | #define PLL_FWDDIVB_3 0x00005000 | |
| 275 | #define PLL_FWDDIVB_2 0x00006000 | |
| 276 | #define PLL_FWDDIVB_1 0x00007000 | |
| 277 | /* PLL tune bits */ | |
| 53677ef1 | 278 | #define PLL_TUNE_MASK 0x000003FF |
| dbcc3571 NG |
279 | #define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ |
| 280 | #define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ | |
| 281 | #define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ | |
| 282 | #define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ | |
| 283 | #define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ | |
| 284 | #define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ | |
| 285 | #define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ | |
| b867d705 SR |
286 | |
| 287 | /* Defines for CPC0_PLLMR0 Register fields */ | |
| dbcc3571 NG |
288 | /* CPU divisor */ |
| 289 | #define PLL_CPUDIV 0x00300000 | |
| 290 | #define CPC0_PLLMR0_CCDV 0x00300000 | |
| 291 | #define PLL_CPUDIV_1 0x00000000 | |
| 292 | #define PLL_CPUDIV_2 0x00100000 | |
| 293 | #define PLL_CPUDIV_3 0x00200000 | |
| 294 | #define PLL_CPUDIV_4 0x00300000 | |
| 295 | /* PLB divisor */ | |
| 296 | #define PLL_PLBDIV 0x00030000 | |
| 297 | #define CPC0_PLLMR0_CBDV 0x00030000 | |
| 298 | #define PLL_PLBDIV_1 0x00000000 | |
| 299 | #define PLL_PLBDIV_2 0x00010000 | |
| 300 | #define PLL_PLBDIV_3 0x00020000 | |
| 301 | #define PLL_PLBDIV_4 0x00030000 | |
| 302 | /* OPB divisor */ | |
| 303 | #define PLL_OPBDIV 0x00003000 | |
| 304 | #define CPC0_PLLMR0_OPDV 0x00003000 | |
| 305 | #define PLL_OPBDIV_1 0x00000000 | |
| 306 | #define PLL_OPBDIV_2 0x00001000 | |
| 307 | #define PLL_OPBDIV_3 0x00002000 | |
| 308 | #define PLL_OPBDIV_4 0x00003000 | |
| 309 | /* EBC divisor */ | |
| 310 | #define PLL_EXTBUSDIV 0x00000300 | |
| 311 | #define CPC0_PLLMR0_EPDV 0x00000300 | |
| 312 | #define PLL_EXTBUSDIV_2 0x00000000 | |
| 313 | #define PLL_EXTBUSDIV_3 0x00000100 | |
| 314 | #define PLL_EXTBUSDIV_4 0x00000200 | |
| 315 | #define PLL_EXTBUSDIV_5 0x00000300 | |
| 316 | /* MAL divisor */ | |
| 317 | #define PLL_MALDIV 0x00000030 | |
| 318 | #define CPC0_PLLMR0_MPDV 0x00000030 | |
| 319 | #define PLL_MALDIV_1 0x00000000 | |
| 320 | #define PLL_MALDIV_2 0x00000010 | |
| 321 | #define PLL_MALDIV_3 0x00000020 | |
| 322 | #define PLL_MALDIV_4 0x00000030 | |
| 323 | /* PCI divisor */ | |
| 324 | #define PLL_PCIDIV 0x00000003 | |
| 325 | #define CPC0_PLLMR0_PPFD 0x00000003 | |
| 326 | #define PLL_PCIDIV_1 0x00000000 | |
| 327 | #define PLL_PCIDIV_2 0x00000001 | |
| 328 | #define PLL_PCIDIV_3 0x00000002 | |
| 329 | #define PLL_PCIDIV_4 0x00000003 | |
| b867d705 SR |
330 | |
| 331 | /* | |
| dbcc3571 | 332 | *------------------------------------------------------------------------------ |
| b867d705 SR |
333 | * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, |
| 334 | * assuming a 33.3MHz input clock to the 405EP. | |
| dbcc3571 | 335 | *------------------------------------------------------------------------------ |
| b867d705 SR |
336 | */ |
| 337 | #define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ | |
| 8bde7f77 WD |
338 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ |
| 339 | PLL_MALDIV_1 | PLL_PCIDIV_4) | |
| b867d705 | 340 | #define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \ |
| 8bde7f77 WD |
341 | PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ |
| 342 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) | |
| b867d705 SR |
343 | |
| 344 | #define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ | |
| 53677ef1 | 345 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ |
| 8bde7f77 | 346 | PLL_MALDIV_1 | PLL_PCIDIV_4) |
| b867d705 | 347 | #define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \ |
| 8bde7f77 WD |
348 | PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ |
| 349 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) | |
| b867d705 | 350 | #define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ |
| 53677ef1 | 351 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ |
| 8bde7f77 | 352 | PLL_MALDIV_1 | PLL_PCIDIV_4) |
| b867d705 | 353 | #define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ |
| 8bde7f77 WD |
354 | PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ |
| 355 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) | |
| b867d705 | 356 | #define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ |
| 53677ef1 | 357 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ |
| 8bde7f77 | 358 | PLL_MALDIV_1 | PLL_PCIDIV_4) |
| b867d705 | 359 | #define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \ |
| 8bde7f77 WD |
360 | PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ |
| 361 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) | |
| 44acc8d3 | 362 | #define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \ |
| 53677ef1 | 363 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ |
| efe2a4d5 | 364 | PLL_MALDIV_1 | PLL_PCIDIV_2) |
| 44acc8d3 | 365 | #define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \ |
| efe2a4d5 WD |
366 | PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ |
| 367 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) | |
| 779e9751 | 368 | #define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ |
| 53677ef1 | 369 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ |
| 779e9751 | 370 | PLL_MALDIV_1 | PLL_PCIDIV_3) |
| 53677ef1 | 371 | #define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \ |
| 779e9751 SR |
372 | PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ |
| 373 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) | |
| 374 | #define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ | |
| 53677ef1 | 375 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ |
| 779e9751 SR |
376 | PLL_MALDIV_1 | PLL_PCIDIV_1) |
| 377 | #define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \ | |
| 378 | PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ | |
| 379 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) | |
| b867d705 SR |
380 | |
| 381 | /* | |
| 382 | * PLL Voltage Controlled Oscillator (VCO) definitions | |
| 383 | * Maximum and minimum values (in MHz) for correct PLL operation. | |
| 384 | */ | |
| 385 | #define VCO_MIN 500 | |
| 386 | #define VCO_MAX 1000 | |
| e01bd218 | 387 | #elif defined(CONFIG_405EZ) |
| d1c3b275 SR |
388 | #define SDR0_NAND0 0x4000 |
| 389 | #define SDR0_ULTRA0 0x4040 | |
| 390 | #define SDR0_ULTRA1 0x4050 | |
| 391 | #define SDR0_ICINTSTAT 0x4510 | |
| e01bd218 SR |
392 | |
| 393 | #define SDR_NAND0_NDEN 0x80000000 | |
| c440bfe6 SR |
394 | #define SDR_NAND0_NDBTEN 0x40000000 |
| 395 | #define SDR_NAND0_NDBADR_MASK 0x30000000 | |
| 396 | #define SDR_NAND0_NDBPG_MASK 0x0f000000 | |
| 397 | #define SDR_NAND0_NDAREN 0x00800000 | |
| 398 | #define SDR_NAND0_NDRBEN 0x00400000 | |
| e01bd218 SR |
399 | |
| 400 | #define SDR_ULTRA0_NDGPIOBP 0x80000000 | |
| 401 | #define SDR_ULTRA0_CSN_MASK 0x78000000 | |
| 402 | #define SDR_ULTRA0_CSNSEL0 0x40000000 | |
| 403 | #define SDR_ULTRA0_CSNSEL1 0x20000000 | |
| 404 | #define SDR_ULTRA0_CSNSEL2 0x10000000 | |
| 405 | #define SDR_ULTRA0_CSNSEL3 0x08000000 | |
| c440bfe6 SR |
406 | #define SDR_ULTRA0_EBCRDYEN 0x04000000 |
| 407 | #define SDR_ULTRA0_SPISSINEN 0x02000000 | |
| 408 | #define SDR_ULTRA0_NFSRSTEN 0x01000000 | |
| e01bd218 SR |
409 | |
| 410 | #define SDR_ULTRA1_LEDNENABLE 0x40000000 | |
| 411 | ||
| 412 | #define SDR_ICRX_STAT 0x80000000 | |
| 413 | #define SDR_ICTX0_STAT 0x40000000 | |
| 414 | #define SDR_ICTX1_STAT 0x20000000 | |
| 415 | ||
| d1c3b275 | 416 | #define SDR0_PINSTP 0x40 |
| 90e6f41c | 417 | |
| e01bd218 SR |
418 | /****************************************************************************** |
| 419 | * Control | |
| 420 | ******************************************************************************/ | |
| e01bd218 | 421 | /* CPR Registers */ |
| d1c3b275 SR |
422 | #define CPR0_CLKUP 0x020 /* CPR_CLKUPD */ |
| 423 | #define CPR0_PLLC 0x040 /* CPR_PLLC */ | |
| 424 | #define CPR0_PLLD 0x060 /* CPR_PLLD */ | |
| 425 | #define CPC0_PRIMAD 0x080 /* CPR_PRIMAD */ | |
| 426 | #define CPC0_PERD0 0x0e0 /* CPR_PERD0 */ | |
| 427 | #define CPC0_PERD1 0x0e1 /* CPR_PERD1 */ | |
| 428 | #define CPC0_PERC0 0x180 /* CPR_PERC0 */ | |
| e01bd218 | 429 | |
| dbcc3571 NG |
430 | #define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */ |
| 431 | #define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */ | |
| 432 | #define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */ | |
| e01bd218 | 433 | |
| dbcc3571 | 434 | #define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ |
| 273db7e1 | 435 | |
| dbcc3571 NG |
436 | #define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */ |
| 437 | #define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */ | |
| 438 | #define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */ | |
| e01bd218 | 439 | |
| dbcc3571 NG |
440 | #define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */ |
| 441 | #define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */ | |
| 442 | #define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */ | |
| 443 | #define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */ | |
| e01bd218 | 444 | |
| dbcc3571 NG |
445 | #define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */ |
| 446 | #define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */ | |
| 447 | #define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */ | |
| 448 | #define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */ | |
| e01bd218 | 449 | |
| b867d705 | 450 | #else /* #ifdef CONFIG_405EP */ |
| 0442ed86 WD |
451 | /****************************************************************************** |
| 452 | * Control | |
| 453 | ******************************************************************************/ | |
| 454 | #define CNTRL_DCR_BASE 0x0b0 | |
| d1c3b275 SR |
455 | #define CPC0_PLLMR (CNTRL_DCR_BASE + 0x0) /* PLL mode register */ |
| 456 | #define CPC0_CR0 (CNTRL_DCR_BASE + 0x1) /* chip control register 0 */ | |
| 457 | #define CPC0_CR1 (CNTRL_DCR_BASE + 0x2) /* chip control register 1 */ | |
| 458 | #define CPC0_PSR (CNTRL_DCR_BASE + 0x4) /* chip pin strapping reg */ | |
| 8cc10d06 NG |
459 | |
| 460 | /* CPC0_ECR/CPC0_EIRR: PPC405GPr only */ | |
| d1c3b275 SR |
461 | #define CPC0_EIRR (CNTRL_DCR_BASE + 0x6) /* ext interrupt routing reg */ |
| 462 | #define CPC0_ECR 0xaa /* edge conditioner register */ | |
| 0442ed86 WD |
463 | |
| 464 | /* Bit definitions */ | |
| dbcc3571 | 465 | #define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */ |
| 53677ef1 WD |
466 | #define PLLMR_FWD_DIV_BYPASS 0xE0000000 |
| 467 | #define PLLMR_FWD_DIV_3 0xA0000000 | |
| 468 | #define PLLMR_FWD_DIV_4 0x80000000 | |
| 469 | #define PLLMR_FWD_DIV_6 0x40000000 | |
| 470 | ||
| dbcc3571 | 471 | #define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */ |
| 53677ef1 WD |
472 | #define PLLMR_FB_DIV_1 0x02000000 |
| 473 | #define PLLMR_FB_DIV_2 0x04000000 | |
| 474 | #define PLLMR_FB_DIV_3 0x06000000 | |
| 475 | #define PLLMR_FB_DIV_4 0x08000000 | |
| 476 | ||
| 477 | #define PLLMR_TUNING_MASK 0x01F80000 | |
| 478 | ||
| dbcc3571 | 479 | #define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */ |
| 53677ef1 WD |
480 | #define PLLMR_CPU_PLB_DIV_1 0x00000000 |
| 481 | #define PLLMR_CPU_PLB_DIV_2 0x00020000 | |
| 482 | #define PLLMR_CPU_PLB_DIV_3 0x00040000 | |
| 483 | #define PLLMR_CPU_PLB_DIV_4 0x00060000 | |
| 484 | ||
| dbcc3571 | 485 | #define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */ |
| 53677ef1 WD |
486 | #define PLLMR_OPB_PLB_DIV_1 0x00000000 |
| 487 | #define PLLMR_OPB_PLB_DIV_2 0x00008000 | |
| 488 | #define PLLMR_OPB_PLB_DIV_3 0x00010000 | |
| 489 | #define PLLMR_OPB_PLB_DIV_4 0x00018000 | |
| 490 | ||
| dbcc3571 | 491 | #define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */ |
| 53677ef1 WD |
492 | #define PLLMR_PCI_PLB_DIV_1 0x00000000 |
| 493 | #define PLLMR_PCI_PLB_DIV_2 0x00002000 | |
| 494 | #define PLLMR_PCI_PLB_DIV_3 0x00004000 | |
| 495 | #define PLLMR_PCI_PLB_DIV_4 0x00006000 | |
| 496 | ||
| dbcc3571 | 497 | #define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */ |
| 53677ef1 WD |
498 | #define PLLMR_EXB_PLB_DIV_2 0x00000000 |
| 499 | #define PLLMR_EXB_PLB_DIV_3 0x00000800 | |
| 500 | #define PLLMR_EXB_PLB_DIV_4 0x00001000 | |
| 501 | #define PLLMR_EXB_PLB_DIV_5 0x00001800 | |
| 0442ed86 WD |
502 | |
| 503 | /* definitions for PPC405GPr (new mode strapping) */ | |
| dbcc3571 | 504 | #define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */ |
| 53677ef1 WD |
505 | |
| 506 | #define PSR_PLL_FWD_MASK 0xC0000000 | |
| 507 | #define PSR_PLL_FDBACK_MASK 0x30000000 | |
| 508 | #define PSR_PLL_TUNING_MASK 0x0E000000 | |
| 509 | #define PSR_PLB_CPU_MASK 0x01800000 | |
| 510 | #define PSR_OPB_PLB_MASK 0x00600000 | |
| 511 | #define PSR_PCI_PLB_MASK 0x00180000 | |
| 512 | #define PSR_EB_PLB_MASK 0x00060000 | |
| 513 | #define PSR_ROM_WIDTH_MASK 0x00018000 | |
| 514 | #define PSR_ROM_LOC 0x00004000 | |
| 515 | #define PSR_PCI_ASYNC_EN 0x00001000 | |
| dbcc3571 | 516 | #define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */ |
| 53677ef1 | 517 | #define PSR_PCI_ARBIT_EN 0x00000400 |
| dbcc3571 | 518 | #define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */ |
| 0442ed86 | 519 | |
| 44acc8d3 | 520 | #ifndef CONFIG_IOP480 |
| 0442ed86 WD |
521 | /* |
| 522 | * PLL Voltage Controlled Oscillator (VCO) definitions | |
| 523 | * Maximum and minimum values (in MHz) for correct PLL operation. | |
| dbcc3571 | 524 | */ |
| 0442ed86 WD |
525 | #define VCO_MIN 400 |
| 526 | #define VCO_MAX 800 | |
| 44acc8d3 | 527 | #endif /* #ifndef CONFIG_IOP480 */ |
| b867d705 | 528 | #endif /* #ifdef CONFIG_405EP */ |
| 0442ed86 WD |
529 | |
| 530 | /****************************************************************************** | |
| 531 | * Memory Access Layer | |
| 532 | ******************************************************************************/ | |
| e01bd218 SR |
533 | #if defined(CONFIG_405EZ) |
| 534 | #define MAL_DCR_BASE 0x380 | |
| d1c3b275 SR |
535 | #else |
| 536 | #define MAL_DCR_BASE 0x180 | |
| 537 | #endif | |
| dbcc3571 NG |
538 | #define MAL0_CFG (MAL_DCR_BASE + 0x00) /* MAL Config reg */ |
| 539 | #define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Err Status (Read/Clear) */ | |
| 540 | #define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */ | |
| 541 | #define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ | |
| 542 | #define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset) */ | |
| 543 | #define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status */ | |
| 544 | #define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int reg */ | |
| 545 | #define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */ | |
| 546 | #define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */ | |
| 547 | #define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status */ | |
| 548 | #define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int reg */ | |
| 549 | #define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table ptr */ | |
| 550 | #define MAL0_TXCTP1R (MAL_DCR_BASE + 0x21) /* TX 1 Channel table ptr */ | |
| 551 | #define MAL0_TXCTP2R (MAL_DCR_BASE + 0x22) /* TX 2 Channel table ptr */ | |
| 552 | #define MAL0_TXCTP3R (MAL_DCR_BASE + 0x23) /* TX 3 Channel table ptr */ | |
| 553 | #define MAL0_RXCTP0R (MAL_DCR_BASE + 0x40) /* RX 0 Channel table ptr */ | |
| 554 | #define MAL0_RXCTP1R (MAL_DCR_BASE + 0x41) /* RX 1 Channel table ptr */ | |
| 555 | #define MAL0_RXCTP2R (MAL_DCR_BASE + 0x42) /* RX 2 Channel table ptr */ | |
| 556 | #define MAL0_RXCTP3R (MAL_DCR_BASE + 0x43) /* RX 3 Channel table ptr */ | |
| 557 | #define MAL0_RXCTP8R (MAL_DCR_BASE + 0x48) /* RX 8 Channel table ptr */ | |
| 558 | #define MAL0_RXCTP16R (MAL_DCR_BASE + 0x50) /* RX 16 Channel table ptr */ | |
| 559 | #define MAL0_RXCTP24R (MAL_DCR_BASE + 0x58) /* RX 24 Channel table ptr */ | |
| 560 | #define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */ | |
| 561 | #define MAL0_RCBS1 (MAL_DCR_BASE + 0x61) /* RX 1 Channel buffer size */ | |
| 562 | #define MAL0_RCBS2 (MAL_DCR_BASE + 0x62) /* RX 2 Channel buffer size */ | |
| 563 | #define MAL0_RCBS3 (MAL_DCR_BASE + 0x63) /* RX 3 Channel buffer size */ | |
| 564 | #define MAL0_RCBS8 (MAL_DCR_BASE + 0x68) /* RX 8 Channel buffer size */ | |
| 565 | #define MAL0_RCBS16 (MAL_DCR_BASE + 0x70) /* RX 16 Channel buffer size */ | |
| 566 | #define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */ | |
| 0442ed86 | 567 | |
| 0442ed86 WD |
568 | /*----------------------------------------------------------------------------- |
| 569 | | UART Register Offsets | |
| 570 | '----------------------------------------------------------------------------*/ | |
| 571 | #define DATA_REG 0x00 | |
| 1636d1c8 WD |
572 | #define DL_LSB 0x00 |
| 573 | #define DL_MSB 0x01 | |
| 53677ef1 WD |
574 | #define INT_ENABLE 0x01 |
| 575 | #define FIFO_CONTROL 0x02 | |
| 576 | #define LINE_CONTROL 0x03 | |
| 577 | #define MODEM_CONTROL 0x04 | |
| 1636d1c8 | 578 | #define LINE_STATUS 0x05 |
| 53677ef1 WD |
579 | #define MODEM_STATUS 0x06 |
| 580 | #define SCRATCH 0x07 | |
| 0442ed86 WD |
581 | |
| 582 | /****************************************************************************** | |
| 583 | * On Chip Memory | |
| 584 | ******************************************************************************/ | |
| e01bd218 SR |
585 | #if defined(CONFIG_405EZ) |
| 586 | #define OCM_DCR_BASE 0x020 | |
| d1c3b275 SR |
587 | #define OCM0_PLBCR1 (OCM_DCR_BASE + 0x00) /* OCM PLB3 Bank 1 Config */ |
| 588 | #define OCM0_PLBCR2 (OCM_DCR_BASE + 0x01) /* OCM PLB3 Bank 2 Config */ | |
| 589 | #define OCM0_PLBBEAR (OCM_DCR_BASE + 0x02) /* OCM PLB3 Bus Error Add */ | |
| 590 | #define OCM0_DSRC1 (OCM_DCR_BASE + 0x08) /* OCM D-side Bank 1 Config */ | |
| 591 | #define OCM0_DSRC2 (OCM_DCR_BASE + 0x09) /* OCM D-side Bank 2 Config */ | |
| 592 | #define OCM0_ISRC1 (OCM_DCR_BASE + 0x0A) /* OCM I-side Bank 1Config */ | |
| 593 | #define OCM0_ISRC2 (OCM_DCR_BASE + 0x0B) /* OCM I-side Bank 2 Config */ | |
| dbcc3571 | 594 | #define OCM0_DISDPC (OCM_DCR_BASE + 0x0C) /* OCM D-/I-side Data Par Chk */ |
| e01bd218 | 595 | #else |
| 0442ed86 | 596 | #define OCM_DCR_BASE 0x018 |
| d1c3b275 SR |
597 | #define OCM0_ISCNTL (OCM_DCR_BASE+0x01) /* OCM I-side control reg */ |
| 598 | #define OCM0_DSARC (OCM_DCR_BASE+0x02) /* OCM D-side address compare */ | |
| 599 | #define OCM0_DSCNTL (OCM_DCR_BASE+0x03) /* OCM D-side control */ | |
| e01bd218 | 600 | #endif /* CONFIG_405EZ */ |
| 0442ed86 | 601 | |
| b867d705 SR |
602 | /****************************************************************************** |
| 603 | * GPIO macro register defines | |
| 604 | ******************************************************************************/ | |
| e01bd218 SR |
605 | #if defined(CONFIG_405EZ) |
| 606 | /* Only the 405EZ has 2 GPIOs */ | |
| 607 | #define GPIO_BASE 0xEF600700 | |
| 608 | #define GPIO0_OR (GPIO_BASE+0x0) | |
| 609 | #define GPIO0_TCR (GPIO_BASE+0x4) | |
| 610 | #define GPIO0_OSRL (GPIO_BASE+0x8) | |
| 611 | #define GPIO0_OSRH (GPIO_BASE+0xC) | |
| 612 | #define GPIO0_TSRL (GPIO_BASE+0x10) | |
| 613 | #define GPIO0_TSRH (GPIO_BASE+0x14) | |
| 614 | #define GPIO0_ODR (GPIO_BASE+0x18) | |
| 615 | #define GPIO0_IR (GPIO_BASE+0x1C) | |
| 616 | #define GPIO0_RR1 (GPIO_BASE+0x20) | |
| 617 | #define GPIO0_RR2 (GPIO_BASE+0x24) | |
| 618 | #define GPIO0_RR3 (GPIO_BASE+0x28) | |
| 619 | #define GPIO0_ISR1L (GPIO_BASE+0x30) | |
| 620 | #define GPIO0_ISR1H (GPIO_BASE+0x34) | |
| 621 | #define GPIO0_ISR2L (GPIO_BASE+0x38) | |
| 622 | #define GPIO0_ISR2H (GPIO_BASE+0x3C) | |
| 623 | #define GPIO0_ISR3L (GPIO_BASE+0x40) | |
| 624 | #define GPIO0_ISR3H (GPIO_BASE+0x44) | |
| 625 | ||
| 626 | #define GPIO1_BASE 0xEF600800 | |
| 627 | #define GPIO1_OR (GPIO1_BASE+0x0) | |
| 628 | #define GPIO1_TCR (GPIO1_BASE+0x4) | |
| 629 | #define GPIO1_OSRL (GPIO1_BASE+0x8) | |
| 630 | #define GPIO1_OSRH (GPIO1_BASE+0xC) | |
| 631 | #define GPIO1_TSRL (GPIO1_BASE+0x10) | |
| 632 | #define GPIO1_TSRH (GPIO1_BASE+0x14) | |
| 633 | #define GPIO1_ODR (GPIO1_BASE+0x18) | |
| 634 | #define GPIO1_IR (GPIO1_BASE+0x1C) | |
| 635 | #define GPIO1_RR1 (GPIO1_BASE+0x20) | |
| 636 | #define GPIO1_RR2 (GPIO1_BASE+0x24) | |
| 637 | #define GPIO1_RR3 (GPIO1_BASE+0x28) | |
| 638 | #define GPIO1_ISR1L (GPIO1_BASE+0x30) | |
| 639 | #define GPIO1_ISR1H (GPIO1_BASE+0x34) | |
| 640 | #define GPIO1_ISR2L (GPIO1_BASE+0x38) | |
| 641 | #define GPIO1_ISR2H (GPIO1_BASE+0x3C) | |
| 642 | #define GPIO1_ISR3L (GPIO1_BASE+0x40) | |
| 643 | #define GPIO1_ISR3H (GPIO1_BASE+0x44) | |
| 644 | ||
| dbbd1257 SR |
645 | #elif defined(CONFIG_405EX) |
| 646 | #define GPIO_BASE 0xEF600800 | |
| 53677ef1 WD |
647 | #define GPIO0_OR (GPIO_BASE+0x0) |
| 648 | #define GPIO0_TCR (GPIO_BASE+0x4) | |
| 649 | #define GPIO0_OSRL (GPIO_BASE+0x8) | |
| 650 | #define GPIO0_OSRH (GPIO_BASE+0xC) | |
| 651 | #define GPIO0_TSRL (GPIO_BASE+0x10) | |
| 652 | #define GPIO0_TSRH (GPIO_BASE+0x14) | |
| 653 | #define GPIO0_ODR (GPIO_BASE+0x18) | |
| 654 | #define GPIO0_IR (GPIO_BASE+0x1C) | |
| 655 | #define GPIO0_RR1 (GPIO_BASE+0x20) | |
| 656 | #define GPIO0_RR2 (GPIO_BASE+0x24) | |
| 657 | #define GPIO0_ISR1L (GPIO_BASE+0x30) | |
| 658 | #define GPIO0_ISR1H (GPIO_BASE+0x34) | |
| 659 | #define GPIO0_ISR2L (GPIO_BASE+0x38) | |
| 660 | #define GPIO0_ISR2H (GPIO_BASE+0x3C) | |
| 661 | #define GPIO0_ISR3L (GPIO_BASE+0x40) | |
| 662 | #define GPIO0_ISR3H (GPIO_BASE+0x44) | |
| dbbd1257 | 663 | |
| e01bd218 SR |
664 | #else /* !405EZ */ |
| 665 | ||
| b867d705 | 666 | #define GPIO_BASE 0xEF600700 |
| 53677ef1 WD |
667 | #define GPIO0_OR (GPIO_BASE+0x0) |
| 668 | #define GPIO0_TCR (GPIO_BASE+0x4) | |
| 669 | #define GPIO0_OSRH (GPIO_BASE+0x8) | |
| 670 | #define GPIO0_OSRL (GPIO_BASE+0xC) | |
| 671 | #define GPIO0_TSRH (GPIO_BASE+0x10) | |
| 672 | #define GPIO0_TSRL (GPIO_BASE+0x14) | |
| 673 | #define GPIO0_ODR (GPIO_BASE+0x18) | |
| 674 | #define GPIO0_IR (GPIO_BASE+0x1C) | |
| 675 | #define GPIO0_RR1 (GPIO_BASE+0x20) | |
| 676 | #define GPIO0_RR2 (GPIO_BASE+0x24) | |
| 677 | #define GPIO0_ISR1H (GPIO_BASE+0x30) | |
| 678 | #define GPIO0_ISR1L (GPIO_BASE+0x34) | |
| 679 | #define GPIO0_ISR2H (GPIO_BASE+0x38) | |
| 680 | #define GPIO0_ISR2L (GPIO_BASE+0x3C) | |
| b867d705 | 681 | |
| e01bd218 | 682 | #endif /* CONFIG_405EZ */ |
| 0442ed86 | 683 | |
| aee747f1 SR |
684 | #define GPIO0_BASE GPIO_BASE |
| 685 | ||
| dbbd1257 SR |
686 | #if defined(CONFIG_405EX) |
| 687 | #define SDR0_SRST 0x0200 | |
| 688 | ||
| 10320173 GE |
689 | /* |
| 690 | * Software Reset Register | |
| 691 | */ | |
| 692 | #define SDR0_SRST_BGO PPC_REG_VAL(0, 1) | |
| 693 | #define SDR0_SRST_PLB4 PPC_REG_VAL(1, 1) | |
| 694 | #define SDR0_SRST_EBC PPC_REG_VAL(2, 1) | |
| 695 | #define SDR0_SRST_OPB PPC_REG_VAL(3, 1) | |
| 696 | #define SDR0_SRST_UART0 PPC_REG_VAL(4, 1) | |
| 697 | #define SDR0_SRST_UART1 PPC_REG_VAL(5, 1) | |
| 698 | #define SDR0_SRST_IIC0 PPC_REG_VAL(6, 1) | |
| 699 | #define SDR0_SRST_BGI PPC_REG_VAL(7, 1) | |
| 700 | #define SDR0_SRST_GPIO PPC_REG_VAL(8, 1) | |
| 701 | #define SDR0_SRST_GPT PPC_REG_VAL(9, 1) | |
| 702 | #define SDR0_SRST_DMC PPC_REG_VAL(10, 1) | |
| 703 | #define SDR0_SRST_RGMII PPC_REG_VAL(11, 1) | |
| 704 | #define SDR0_SRST_EMAC0 PPC_REG_VAL(12, 1) | |
| 705 | #define SDR0_SRST_EMAC1 PPC_REG_VAL(13, 1) | |
| 706 | #define SDR0_SRST_CPM PPC_REG_VAL(14, 1) | |
| 707 | #define SDR0_SRST_EPLL PPC_REG_VAL(15, 1) | |
| 708 | #define SDR0_SRST_UIC PPC_REG_VAL(16, 1) | |
| 709 | #define SDR0_SRST_UPRST PPC_REG_VAL(17, 1) | |
| 710 | #define SDR0_SRST_IIC1 PPC_REG_VAL(18, 1) | |
| 711 | #define SDR0_SRST_SCP PPC_REG_VAL(19, 1) | |
| 712 | #define SDR0_SRST_UHRST PPC_REG_VAL(20, 1) | |
| 713 | #define SDR0_SRST_DMA PPC_REG_VAL(21, 1) | |
| 714 | #define SDR0_SRST_DMAC PPC_REG_VAL(22, 1) | |
| 715 | #define SDR0_SRST_MAL PPC_REG_VAL(23, 1) | |
| 716 | #define SDR0_SRST_EBM PPC_REG_VAL(24, 1) | |
| 717 | #define SDR0_SRST_GPTR PPC_REG_VAL(25, 1) | |
| 718 | #define SDR0_SRST_PE0 PPC_REG_VAL(26, 1) | |
| 719 | #define SDR0_SRST_PE1 PPC_REG_VAL(27, 1) | |
| 720 | #define SDR0_SRST_CRYP PPC_REG_VAL(28, 1) | |
| 721 | #define SDR0_SRST_PKP PPC_REG_VAL(29, 1) | |
| 722 | #define SDR0_SRST_AHB PPC_REG_VAL(30, 1) | |
| 723 | #define SDR0_SRST_NDFC PPC_REG_VAL(31, 1) | |
| 724 | ||
| d1c3b275 SR |
725 | #define SDR0_UART0 0x0120 /* UART0 Config */ |
| 726 | #define SDR0_UART1 0x0121 /* UART1 Config */ | |
| 727 | #define SDR0_MFR 0x4300 /* SDR0_MFR reg */ | |
| dbbd1257 SR |
728 | |
| 729 | /* Defines for CPC0_EPRCSR register */ | |
| dbcc3571 NG |
730 | #define CPC0_EPRCSR_E0NFE 0x80000000 |
| 731 | #define CPC0_EPRCSR_E1NFE 0x40000000 | |
| 732 | #define CPC0_EPRCSR_E1RPP 0x00000080 | |
| 733 | #define CPC0_EPRCSR_E0RPP 0x00000040 | |
| 734 | #define CPC0_EPRCSR_E1ERP 0x00000020 | |
| 735 | #define CPC0_EPRCSR_E0ERP 0x00000010 | |
| 736 | #define CPC0_EPRCSR_E1PCI 0x00000002 | |
| 737 | #define CPC0_EPRCSR_E0PCI 0x00000001 | |
| dbbd1257 | 738 | |
| d1c3b275 SR |
739 | #define CPR0_CLKUPD 0x020 |
| 740 | #define CPR0_PLLC 0x040 | |
| 741 | #define CPR0_PLLD 0x060 | |
| 742 | #define CPR0_CPUD 0x080 | |
| 743 | #define CPR0_PLBD 0x0a0 | |
| f80e61dc | 744 | #define CPR0_OPBD0 0x0c0 |
| d1c3b275 SR |
745 | #define CPR0_PERD 0x0e0 |
| 746 | ||
| 747 | #define SDR0_PINSTP 0x0040 | |
| 748 | #define SDR0_SDCS0 0x0060 | |
| dbbd1257 SR |
749 | |
| 750 | #define SDR0_SDCS_SDD (0x80000000 >> 31) | |
| 751 | ||
| 752 | /* CUST0 Customer Configuration Register0 */ | |
| 53677ef1 | 753 | #define SDR0_CUST0 0x4000 |
| dbcc3571 NG |
754 | #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ |
| 755 | #define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ | |
| 756 | #define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ | |
| 757 | #define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ | |
| 758 | ||
| 759 | #define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ | |
| 760 | #define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ | |
| 761 | #define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ | |
| 762 | ||
| 763 | #define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ | |
| 764 | #define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width= 16 Bit */ | |
| 765 | #define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width= 8 Bit */ | |
| 766 | ||
| 767 | #define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ | |
| 768 | #define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) | |
| 769 | #define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) | |
| 770 | ||
| 771 | #define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ | |
| 772 | #define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22) | |
| 773 | #define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03) | |
| 774 | ||
| 775 | #define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ | |
| 776 | #define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ | |
| 777 | #define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ | |
| 778 | ||
| 779 | #define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ | |
| 780 | #define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ | |
| 781 | #define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ | |
| 782 | ||
| 783 | #define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ | |
| 784 | #define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4) | |
| 785 | #define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF) | |
| 786 | ||
| 787 | #define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Sel Gating Mask */ | |
| 788 | #define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Sel Gating Disable */ | |
| 789 | #define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Sel Gating Enable */ | |
| 790 | #define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Sel0 Gating Enable */ | |
| 791 | #define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Sel1 Gating Enable */ | |
| 792 | #define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Sel2 Gating Enable */ | |
| 793 | #define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Sel3 Gating Enable */ | |
| 7cfc12a7 SR |
794 | |
| 795 | #define SDR0_PFC0 0x4100 | |
| 796 | #define SDR0_PFC1 0x4101 | |
| 797 | #define SDR0_PFC1_U1ME 0x02000000 | |
| 798 | #define SDR0_PFC1_U0ME 0x00080000 | |
| 799 | #define SDR0_PFC1_U0IM 0x00040000 | |
| 800 | #define SDR0_PFC1_SIS 0x00020000 | |
| 801 | #define SDR0_PFC1_DMAAEN 0x00010000 | |
| 802 | #define SDR0_PFC1_DMADEN 0x00008000 | |
| 803 | #define SDR0_PFC1_USBEN 0x00004000 | |
| 804 | #define SDR0_PFC1_AHBSWAP 0x00000020 | |
| 805 | #define SDR0_PFC1_USBBIGEN 0x00000010 | |
| 806 | #define SDR0_PFC1_GPT_FREQ 0x0000000f | |
| dbbd1257 SR |
807 | #endif |
| 808 | ||
| c821b5f1 GE |
809 | /* General Purpose Timer (GPT) Register Offsets */ |
| 810 | #define GPT0_TBC 0x00000000 | |
| 811 | #define GPT0_IM 0x00000018 | |
| 812 | #define GPT0_ISS 0x0000001C | |
| 813 | #define GPT0_ISC 0x00000020 | |
| 814 | #define GPT0_IE 0x00000024 | |
| 815 | #define GPT0_COMP0 0x00000080 | |
| 816 | #define GPT0_COMP1 0x00000084 | |
| 817 | #define GPT0_COMP2 0x00000088 | |
| 818 | #define GPT0_COMP3 0x0000008C | |
| 819 | #define GPT0_COMP4 0x00000090 | |
| 820 | #define GPT0_COMP5 0x00000094 | |
| 821 | #define GPT0_COMP6 0x00000098 | |
| 822 | #define GPT0_MASK0 0x000000C0 | |
| 823 | #define GPT0_MASK1 0x000000C4 | |
| 824 | #define GPT0_MASK2 0x000000C8 | |
| 825 | #define GPT0_MASK3 0x000000CC | |
| 826 | #define GPT0_MASK4 0x000000D0 | |
| 827 | #define GPT0_MASK5 0x000000D4 | |
| 828 | #define GPT0_MASK6 0x000000D8 | |
| 829 | #define GPT0_DCT0 0x00000110 | |
| 830 | #define GPT0_DCIS 0x0000011C | |
| 831 | ||
| 0442ed86 | 832 | #endif /* __PPC405_H__ */ |