[J-u-boot.git] / include / configs / omap5912osk.h

/*
 * (C) Copyright 2003
 * Texas Instruments.
 * Kshitij Gupta <[email protected]>
 * Configuation settings for the TI OMAP Innovator board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_ARM926EJS	1	/* This is an arm926ejs CPU core  */
#define CONFIG_OMAP	1			/* in a TI OMAP core    */
#define CONFIG_OMAP1610	1		/* 5912 is same as 1610  */
#define CONFIG_OSK_OMAP5912	1	/*  a OSK Board  */

#define CONFIG_DISPLAY_CPUINFO	1	/* display cpu info (and speed)	*/
#define CONFIG_DISPLAY_BOARDINFO 1	/* display board info		*/

/* input clock of PLL */
/* the OMAP5912 OSK has 12MHz input clock */
#define CONFIG_SYS_CLK_FREQ	12000000

#undef CONFIG_USE_IRQ	/* we don't need IRQ/FIQ stuff */

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG      1       /* Required for ramdisk support */

/*
 * Size of malloc() pool
 */
#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */

/*
 * Hardware drivers
 */
/*
*/
#define CONFIG_DRIVER_LAN91C96
#define CONFIG_LAN91C96_BASE 0x04800300
#define CONFIG_LAN91C96_EXT_PHY

/*
 * NS16550 Configuration
 */
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE	(-4)
#define CFG_NS16550_CLK	(48000000)	/* can be 12M/32Khz or 48Mhz */
#define CFG_NS16550_COM1	0xfffb0000	/* uart1, bluetooth uart
						on helen */

/*
 * select serial console configuration
 */
#define CONFIG_SERIAL1	1	/* we use SERIAL 1 on OMAP5912 OSK */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE	115200
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH


#include <configs/omap1510.h>

#define CONFIG_BOOTDELAY	3
#define CONFIG_BOOTARGS	"mem=32M console=ttyS0,115200n8 noinitrd \
				root=/dev/nfs rw nfsroot=157.87.82.48:\
				/home/mwd/myfs/target ip=dhcp"
#define CONFIG_NETMASK	255.255.254.0	/* talk on MY local net */
#define CONFIG_IPADDR	156.117.97.156	/* static IP I currently own */
#define CONFIG_SERVERIP	156.117.97.139	/* current IP of my dev pc */
#define CONFIG_BOOTFILE	"uImage"	/* file to load */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	1	/* which serial port to use */
#endif

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP	/* undef to save memory     */
#define CFG_PROMPT	"OMAP5912 OSK # "	/* Monitor Command Prompt   */
#define CFG_CBSIZE	256		/* Console I/O Buffer Size  */
/* Print Buffer Size */
#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
#define CFG_MAXARGS	16		/* max number of command args   */
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size    */

#define CFG_MEMTEST_START	0x10000000	/* memtest works on */
#define CFG_MEMTEST_END	0x12000000	/* 32 MB in DRAM    */

#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */

#define CFG_LOAD_ADDR	0x10000000	/* default load address */

/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
 * DPLL1. This time is further subdivided by a local divisor.
 */
#define CFG_TIMERBASE	0xFFFEC500	/* use timer 1 */
#define CFG_PVT	7	/* 2^(pvt+1), divide by 256 */
#define CFG_HZ	((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
#endif

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1	/* we have 1 bank of DRAM */
#define PHYS_SDRAM_1		0x10000000	/* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE	0x02000000	/* 32 MB */

#define PHYS_FLASH_1		0x00000000	/* Flash Bank #1 */
#define PHYS_FLASH_2		0x01000000	/* Flash Bank #2 */

#define CFG_FLASH_BASE		PHYS_FLASH_1

#define CFG_MONITOR_BASE       CFG_FLASH_BASE  /* Monitor at beginning of flash */

/*-----------------------------------------------------------------------
 * FLASH driver setup
 */
#define CFG_FLASH_CFI          1       /* Flash memory is CFI compliant */
#define CFG_FLASH_CFI_DRIVER   1       /* Use drivers/cfi_flash.c */

#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }

#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
#define PHYS_FLASH_SIZE	0x02000000	/* 32MB */
#define CFG_MAX_FLASH_SECT	(259)	/* max number of sectors on one chip */

#define CFG_FLASH_USE_BUFFER_WRITE     1       /* Use buffered writes (~10x faster) */
#define CFG_FLASH_PROTECTION   1       /* Use hardware sector protection */

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Write */

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#define CFG_ENV_IS_IN_FLASH	1
/* addr of environment */
#define CFG_ENV_ADDR	(CFG_FLASH_BASE + 0x020000)

#define CFG_ENV_SIZE	0x20000	/* Total Size of Environment Sector */
#define CFG_ENV_OFFSET	0x20000	/* environment starts here  */

#endif							/* __CONFIG_H */
Commit	Line	Data
1eaeb58e WD	1	/*
	2	* (C) Copyright 2003
	3	* Texas Instruments.
	4	* Kshitij Gupta <[email protected]>
	5	* Configuation settings for the TI OMAP Innovator board.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#ifndef __CONFIG_H
	27	#define __CONFIG_H
	28
1eaeb58e WD	29	/*
	30	* High Level Configuration Options
	31	* (easy to change)
	32	*/
	33	#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
	34	#define CONFIG_OMAP 1 /* in a TI OMAP core */
	35	#define CONFIG_OMAP1610 1 /* 5912 is same as 1610 */
	36	#define CONFIG_OSK_OMAP5912 1 /* a OSK Board */
	37
6080a0eb SR	38	#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
	39	#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
	40
1eaeb58e WD	41	/* input clock of PLL */
	42	/* the OMAP5912 OSK has 12MHz input clock */
	43	#define CONFIG_SYS_CLK_FREQ 12000000
	44
	45	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
	46
	47	#define CONFIG_MISC_INIT_R
	48
	49	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	50	#define CONFIG_SETUP_MEMORY_TAGS 1
6080a0eb	51	#define CONFIG_INITRD_TAG 1 /* Required for ramdisk support */
1eaeb58e WD	52
	53	/*
	54	* Size of malloc() pool
	55	*/
	56	#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
6080a0eb	57	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
1eaeb58e WD	58
	59	/*
	60	* Hardware drivers
	61	*/
	62	/*
	63	*/
	64	#define CONFIG_DRIVER_LAN91C96
	65	#define CONFIG_LAN91C96_BASE 0x04800300
	66	#define CONFIG_LAN91C96_EXT_PHY
	67
	68	/*
	69	* NS16550 Configuration
	70	*/
	71	#define CFG_NS16550
	72	#define CFG_NS16550_SERIAL
	73	#define CFG_NS16550_REG_SIZE (-4)
	74	#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
	75	#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart
	76	on helen */
	77
	78	/*
	79	* select serial console configuration
	80	*/
	81	#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP5912 OSK */
	82
	83	/* allow to overwrite serial and ethaddr */
	84	#define CONFIG_ENV_OVERWRITE
	85	#define CONFIG_CONS_INDEX 1
	86	#define CONFIG_BAUDRATE 115200
	87	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	88
a5cb2309 JL	89
	90	/*
	91	* Command line configuration.
	92	*/
	93	#include <config_cmd_default.h>
	94
	95	#define CONFIG_CMD_DHCP
	96
	97
d3b8c1a7 JL	98	/*
	99	* BOOTP options
	100	*/
	101	#define CONFIG_BOOTP_SUBNETMASK
	102	#define CONFIG_BOOTP_GATEWAY
	103	#define CONFIG_BOOTP_HOSTNAME
	104	#define CONFIG_BOOTP_BOOTPATH
	105
1eaeb58e	106
1eaeb58e WD	107	#include <configs/omap1510.h>
	108
	109	#define CONFIG_BOOTDELAY 3
	110	#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd \
	111	root=/dev/nfs rw nfsroot=157.87.82.48:\
	112	/home/mwd/myfs/target ip=dhcp"
	113	#define CONFIG_NETMASK 255.255.254.0 /* talk on MY local net */
	114	#define CONFIG_IPADDR 156.117.97.156 /* static IP I currently own */
	115	#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */
	116	#define CONFIG_BOOTFILE "uImage" /* file to load */
	117
a5cb2309	118	#if defined(CONFIG_CMD_KGDB)
1eaeb58e WD	119	#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
	120	#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
	121	#endif
	122
	123	/*
	124	* Miscellaneous configurable options
	125	*/
	126	#define CFG_LONGHELP /* undef to save memory */
	127	#define CFG_PROMPT "OMAP5912 OSK # " /* Monitor Command Prompt */
	128	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	129	/* Print Buffer Size */
	130	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
	131	#define CFG_MAXARGS 16 /* max number of command args */
	132	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	133
	134	#define CFG_MEMTEST_START 0x10000000 /* memtest works on */
	135	#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
	136
	137	#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
	138
	139	#define CFG_LOAD_ADDR 0x10000000 /* default load address */
	140
	141	/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
	142	* DPLL1. This time is further subdivided by a local divisor.
	143	*/
	144	#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */
	145	#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */
	146	#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
	147
	148	/*-----------------------------------------------------------------------
	149	* Stack sizes
	150	*
	151	* The stack sizes are set up in start.S using the settings below
	152	*/
	153	#define CONFIG_STACKSIZE (1281024) / regular stack */
	154	#ifdef CONFIG_USE_IRQ
	155	#define CONFIG_STACKSIZE_IRQ (41024) / IRQ stack */
	156	#define CONFIG_STACKSIZE_FIQ (41024) / FIQ stack */
	157	#endif
	158
	159	/*-----------------------------------------------------------------------
	160	* Physical Memory Map
	161	*/
	162	#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
6080a0eb	163	#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
1eaeb58e WD	164	#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
1eaeb58e WD	165
6080a0eb SR	166	#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
	167	#define PHYS_FLASH_2 0x01000000 /* Flash Bank #2 */
	168
	169	#define CFG_FLASH_BASE PHYS_FLASH_1
1eaeb58e	170
6080a0eb	171	#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */
1eaeb58e WD	172
1eaeb58e WD	173	/*-----------------------------------------------------------------------
6080a0eb	174	* FLASH driver setup
1eaeb58e	175	*/
6080a0eb SR	176	#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
	177	#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
	178
	179	#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
	180
	181	#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
1eaeb58e WD	182	#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
1eaeb58e WD	183	#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
6080a0eb SR	184
	185	#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
	186	#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
	187
	188	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
1eaeb58e WD	189
	190	/* timeout values are in ticks */
	191	#define CFG_FLASH_ERASE_TOUT (20CFG_HZ) / Timeout for Flash Erase */
	192	#define CFG_FLASH_WRITE_TOUT (20CFG_HZ) / Timeout for Flash Write */
	193
6080a0eb SR	194	/*-----------------------------------------------------------------------
	195	* FLASH and environment organization
	196	*/
1eaeb58e	197	#define CFG_ENV_IS_IN_FLASH 1
6080a0eb SR	198	/* addr of environment */
	199	#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x020000)
	200
1eaeb58e WD	201	#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
	202	#define CFG_ENV_OFFSET 0x20000 /* environment starts here */
	203
	204	#endif /* __CONFIG_H */