]> Git Repo - J-u-boot.git/blame - drivers/spi/mpc8xxx_spi.c
spi: Use spi_alloc_slave() in each SPI driver
[J-u-boot.git] / drivers / spi / mpc8xxx_spi.c
CommitLineData
04a9e118
BW
1/*
2 * Copyright (c) 2006 Ben Warren, Qstreams Networks Inc.
a47a12be 3 * With help from the common/soft_spi and arch/powerpc/cpu/mpc8260 drivers
04a9e118
BW
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
8931ab17 25
d255bb0e 26#include <malloc.h>
04a9e118
BW
27#include <spi.h>
28#include <asm/mpc8xxx_spi.h>
29
2956acd5
KP
30#define SPI_EV_NE (0x80000000 >> 22) /* Receiver Not Empty */
31#define SPI_EV_NF (0x80000000 >> 23) /* Transmitter Not Full */
04a9e118 32
2956acd5
KP
33#define SPI_MODE_LOOP (0x80000000 >> 1) /* Loopback mode */
34#define SPI_MODE_REV (0x80000000 >> 5) /* Reverse mode - MSB first */
35#define SPI_MODE_MS (0x80000000 >> 6) /* Always master */
36#define SPI_MODE_EN (0x80000000 >> 7) /* Enable interface */
04a9e118
BW
37
38#define SPI_TIMEOUT 1000
39
d255bb0e
HS
40struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
41 unsigned int max_hz, unsigned int mode)
42{
43 struct spi_slave *slave;
44
45 if (!spi_cs_is_valid(bus, cs))
46 return NULL;
47
d3504fee 48 slave = spi_alloc_slave_base(bus, cs);
d255bb0e
HS
49 if (!slave)
50 return NULL;
51
d255bb0e
HS
52 /*
53 * TODO: Some of the code in spi_init() should probably move
54 * here, or into spi_claim_bus() below.
55 */
56
57 return slave;
58}
59
60void spi_free_slave(struct spi_slave *slave)
61{
62 free(slave);
63}
64
04a9e118
BW
65void spi_init(void)
66{
6d0f6bcf 67 volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi;
04a9e118 68
2956acd5 69 /*
04a9e118
BW
70 * SPI pins on the MPC83xx are not muxed, so all we do is initialize
71 * some registers
2956acd5 72 */
04a9e118 73 spi->mode = SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN;
2956acd5
KP
74 spi->mode = (spi->mode & 0xfff0ffff) | (1 << 16); /* Use SYSCLK / 8
75 (16.67MHz typ.) */
04a9e118
BW
76 spi->event = 0xffffffff; /* Clear all SPI events */
77 spi->mask = 0x00000000; /* Mask all SPI interrupts */
78 spi->com = 0; /* LST bit doesn't do anything, so disregard */
79}
80
d255bb0e
HS
81int spi_claim_bus(struct spi_slave *slave)
82{
83 return 0;
84}
85
86void spi_release_bus(struct spi_slave *slave)
87{
88
89}
90
91int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
92 void *din, unsigned long flags)
04a9e118 93{
6d0f6bcf 94 volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi;
04a9e118
BW
95 unsigned int tmpdout, tmpdin, event;
96 int numBlks = bitlen / 32 + (bitlen % 32 ? 1 : 0);
97 int tm, isRead = 0;
98 unsigned char charSize = 32;
99
d255bb0e
HS
100 debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
101 slave->bus, slave->cs, *(uint *) dout, *(uint *) din, bitlen);
04a9e118 102
d255bb0e
HS
103 if (flags & SPI_XFER_BEGIN)
104 spi_cs_activate(slave);
04a9e118
BW
105
106 spi->event = 0xffffffff; /* Clear all SPI events */
107
108 /* handle data in 32-bit chunks */
109 while (numBlks--) {
110 tmpdout = 0;
111 charSize = (bitlen >= 32 ? 32 : bitlen);
112
113 /* Shift data so it's msb-justified */
114 tmpdout = *(u32 *) dout >> (32 - charSize);
115
116 /* The LEN field of the SPMODE register is set as follows:
117 *
2956acd5
KP
118 * Bit length setting
119 * len <= 4 3
120 * 4 < len <= 16 len - 1
121 * len > 16 0
04a9e118
BW
122 */
123
f138ca13
IS
124 spi->mode &= ~SPI_MODE_EN;
125
2956acd5
KP
126 if (bitlen <= 16) {
127 if (bitlen <= 4)
128 spi->mode = (spi->mode & 0xff0fffff) |
129 (3 << 20);
130 else
131 spi->mode = (spi->mode & 0xff0fffff) |
132 ((bitlen - 1) << 20);
133 } else {
134 spi->mode = (spi->mode & 0xff0fffff);
04a9e118
BW
135 /* Set up the next iteration if sending > 32 bits */
136 bitlen -= 32;
137 dout += 4;
138 }
139
f138ca13
IS
140 spi->mode |= SPI_MODE_EN;
141
04a9e118
BW
142 spi->tx = tmpdout; /* Write the data out */
143 debug("*** spi_xfer: ... %08x written\n", tmpdout);
144
2956acd5 145 /*
04a9e118
BW
146 * Wait for SPI transmit to get out
147 * or time out (1 second = 1000 ms)
148 * The NE event must be read and cleared first
2956acd5 149 */
04a9e118
BW
150 for (tm = 0, isRead = 0; tm < SPI_TIMEOUT; ++tm) {
151 event = spi->event;
152 if (event & SPI_EV_NE) {
153 tmpdin = spi->rx;
154 spi->event |= SPI_EV_NE;
155 isRead = 1;
156
157 *(u32 *) din = (tmpdin << (32 - charSize));
158 if (charSize == 32) {
159 /* Advance output buffer by 32 bits */
160 din += 4;
161 }
162 }
2956acd5
KP
163 /*
164 * Only bail when we've had both NE and NF events.
04a9e118
BW
165 * This will cause timeouts on RO devices, so maybe
166 * in the future put an arbitrary delay after writing
2956acd5
KP
167 * the device. Arbitrary delays suck, though...
168 */
04a9e118
BW
169 if (isRead && (event & SPI_EV_NF))
170 break;
171 }
172 if (tm >= SPI_TIMEOUT)
173 puts("*** spi_xfer: Time out during SPI transfer");
174
175 debug("*** spi_xfer: transfer ended. Value=%08x\n", tmpdin);
176 }
177
d255bb0e
HS
178 if (flags & SPI_XFER_END)
179 spi_cs_deactivate(slave);
2956acd5 180
04a9e118
BW
181 return 0;
182}
This page took 0.225159 seconds and 4 git commands to generate.