[J-u-boot.git] / drivers / serial / atmel_usart.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2004-2006 Atmel Corporation
 *
 * Modified to support C structur SoC access by
 * Andreas Bießmann <[email protected]>
 */
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <malloc.h>
#include <watchdog.h>
#include <serial.h>
#include <debug_uart.h>
#include <linux/compiler.h>
#include <linux/delay.h>

#include <asm/io.h>
#ifdef CONFIG_DM_SERIAL
#include <asm/arch/atmel_serial.h>
#endif
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>

#include "atmel_usart.h"

DECLARE_GLOBAL_DATA_PTR;

#ifndef CONFIG_DM_SERIAL
static void atmel_serial_setbrg_internal(atmel_usart3_t *usart, int id,
					 int baudrate)
{
	unsigned long divisor;
	unsigned long usart_hz;

	/*
	 *              Master Clock
	 * Baud Rate = --------------
	 *                16 * CD
	 */
	usart_hz = get_usart_clk_rate(id);
	divisor = (usart_hz / 16 + baudrate / 2) / baudrate;
	writel(USART3_BF(CD, divisor), &usart->brgr);
}

static void atmel_serial_init_internal(atmel_usart3_t *usart)
{
	/*
	 * Just in case: drain transmitter register
	 * 1000us is enough for baudrate >= 9600
	 */
	if (!(readl(&usart->csr) & USART3_BIT(TXEMPTY)))
		__udelay(1000);

	writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
}

static void atmel_serial_activate(atmel_usart3_t *usart)
{
	writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
			   | USART3_BF(USCLKS, USART3_USCLKS_MCK)
			   | USART3_BF(CHRL, USART3_CHRL_8)
			   | USART3_BF(PAR, USART3_PAR_NONE)
			   | USART3_BF(NBSTOP, USART3_NBSTOP_1)),
			   &usart->mr);
	writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
	/* 100us is enough for the new settings to be settled */
	__udelay(100);
}

static void atmel_serial_setbrg(void)
{
	atmel_serial_setbrg_internal((atmel_usart3_t *)CONFIG_USART_BASE,
				     CONFIG_USART_ID, gd->baudrate);
}

static int atmel_serial_init(void)
{
	atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;

	atmel_serial_init_internal(usart);
	serial_setbrg();
	atmel_serial_activate(usart);

	return 0;
}

static void atmel_serial_putc(char c)
{
	atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;

	if (c == '\n')
		serial_putc('\r');

	while (!(readl(&usart->csr) & USART3_BIT(TXRDY)));
	writel(c, &usart->thr);
}

static int atmel_serial_getc(void)
{
	atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;

	while (!(readl(&usart->csr) & USART3_BIT(RXRDY)))
		 WATCHDOG_RESET();
	return readl(&usart->rhr);
}

static int atmel_serial_tstc(void)
{
	atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
	return (readl(&usart->csr) & USART3_BIT(RXRDY)) != 0;
}

static struct serial_device atmel_serial_drv = {
	.name	= "atmel_serial",
	.start	= atmel_serial_init,
	.stop	= NULL,
	.setbrg	= atmel_serial_setbrg,
	.putc	= atmel_serial_putc,
	.puts	= default_serial_puts,
	.getc	= atmel_serial_getc,
	.tstc	= atmel_serial_tstc,
};

void atmel_serial_initialize(void)
{
	serial_register(&atmel_serial_drv);
}

__weak struct serial_device *default_serial_console(void)
{
	return &atmel_serial_drv;
}
#endif

#ifdef CONFIG_DM_SERIAL
enum serial_clk_type {
	CLK_TYPE_NORMAL = 0,
	CLK_TYPE_DBGU,
};

struct atmel_serial_priv {
	atmel_usart3_t *usart;
	ulong usart_clk_rate;
};

static void _atmel_serial_set_brg(atmel_usart3_t *usart,
				  ulong usart_clk_rate, int baudrate)
{
	unsigned long divisor;

	divisor = (usart_clk_rate / 16 + baudrate / 2) / baudrate;
	writel(USART3_BF(CD, divisor), &usart->brgr);
}

void _atmel_serial_init(atmel_usart3_t *usart,
			ulong usart_clk_rate, int baudrate)
{
	writel(USART3_BIT(RXDIS) | USART3_BIT(TXDIS), &usart->cr);

	writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL) |
		USART3_BF(USCLKS, USART3_USCLKS_MCK) |
		USART3_BF(CHRL, USART3_CHRL_8) |
		USART3_BF(PAR, USART3_PAR_NONE) |
		USART3_BF(NBSTOP, USART3_NBSTOP_1)), &usart->mr);

	_atmel_serial_set_brg(usart, usart_clk_rate, baudrate);

	writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
	writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
}

int atmel_serial_setbrg(struct udevice *dev, int baudrate)
{
	struct atmel_serial_priv *priv = dev_get_priv(dev);

	_atmel_serial_set_brg(priv->usart, priv->usart_clk_rate, baudrate);

	return 0;
}

static int atmel_serial_getc(struct udevice *dev)
{
	struct atmel_serial_priv *priv = dev_get_priv(dev);

	if (!(readl(&priv->usart->csr) & USART3_BIT(RXRDY)))
		return -EAGAIN;

	return readl(&priv->usart->rhr);
}

static int atmel_serial_putc(struct udevice *dev, const char ch)
{
	struct atmel_serial_priv *priv = dev_get_priv(dev);

	if (!(readl(&priv->usart->csr) & USART3_BIT(TXRDY)))
		return -EAGAIN;

	writel(ch, &priv->usart->thr);

	return 0;
}

static int atmel_serial_pending(struct udevice *dev, bool input)
{
	struct atmel_serial_priv *priv = dev_get_priv(dev);
	uint32_t csr = readl(&priv->usart->csr);

	if (input)
		return csr & USART3_BIT(RXRDY) ? 1 : 0;
	else
		return csr & USART3_BIT(TXEMPTY) ? 0 : 1;
}

static const struct dm_serial_ops atmel_serial_ops = {
	.putc = atmel_serial_putc,
	.pending = atmel_serial_pending,
	.getc = atmel_serial_getc,
	.setbrg = atmel_serial_setbrg,
};

#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_CLK)
static int atmel_serial_enable_clk(struct udevice *dev)
{
	struct atmel_serial_priv *priv = dev_get_priv(dev);

	/* Use fixed clock value in SPL */
	priv->usart_clk_rate = CONFIG_SPL_UART_CLOCK;

	return 0;
}
#else
static int atmel_serial_enable_clk(struct udevice *dev)
{
	struct atmel_serial_priv *priv = dev_get_priv(dev);
	struct clk clk;
	ulong clk_rate;
	int ret;

	ret = clk_get_by_index(dev, 0, &clk);
	if (ret)
		return -EINVAL;

	if (dev_get_driver_data(dev) == CLK_TYPE_NORMAL) {
		ret = clk_enable(&clk);
		if (ret)
			return ret;
	}

	clk_rate = clk_get_rate(&clk);
	if (!clk_rate)
		return -EINVAL;

	priv->usart_clk_rate = clk_rate;

	clk_free(&clk);

	return 0;
}
#endif

static int atmel_serial_probe(struct udevice *dev)
{
	struct atmel_serial_platdata *plat = dev->platdata;
	struct atmel_serial_priv *priv = dev_get_priv(dev);
	int ret;
#if CONFIG_IS_ENABLED(OF_CONTROL)
	fdt_addr_t addr_base;

	addr_base = dev_read_addr(dev);
	if (addr_base == FDT_ADDR_T_NONE)
		return -ENODEV;

	plat->base_addr = (uint32_t)addr_base;
#endif
	priv->usart = (atmel_usart3_t *)plat->base_addr;

	ret = atmel_serial_enable_clk(dev);
	if (ret)
		return ret;

	_atmel_serial_init(priv->usart, priv->usart_clk_rate, gd->baudrate);

	return 0;
}

#if CONFIG_IS_ENABLED(OF_CONTROL)
static const struct udevice_id atmel_serial_ids[] = {
	{
		.compatible = "atmel,at91sam9260-dbgu",
		.data = CLK_TYPE_DBGU,
	},
	{
		.compatible = "atmel,at91sam9260-usart",
		.data = CLK_TYPE_NORMAL,
	},
	{ }
};
#endif

U_BOOT_DRIVER(serial_atmel) = {
	.name	= "serial_atmel",
	.id	= UCLASS_SERIAL,
#if CONFIG_IS_ENABLED(OF_CONTROL)
	.of_match = atmel_serial_ids,
	.platdata_auto_alloc_size = sizeof(struct atmel_serial_platdata),
#endif
	.probe = atmel_serial_probe,
	.ops	= &atmel_serial_ops,
#if !CONFIG_IS_ENABLED(OF_CONTROL)
	.flags = DM_FLAG_PRE_RELOC,
#endif
	.priv_auto_alloc_size	= sizeof(struct atmel_serial_priv),
};
#endif

#ifdef CONFIG_DEBUG_UART_ATMEL
static inline void _debug_uart_init(void)
{
	atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE;

	_atmel_serial_init(usart, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
}

static inline void _debug_uart_putc(int ch)
{
	atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE;

	while (!(readl(&usart->csr) & USART3_BIT(TXRDY)))
		;

	writel(ch, &usart->thr);
}

DEBUG_UART_FUNCS
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
f93ae788 WD	2	/*
	3	* Copyright (C) 2004-2006 Atmel Corporation
	4	*
125637c5 AB	5	* Modified to support C structur SoC access by
125637c5 AB	6	* Andreas Bießmann <[email protected]>
f93ae788 WD	7	*/
f93ae788 WD	8	#include <common.h>
f8b7fff1	9	#include <clk.h>
0f65f48b SG	10	#include <dm.h>
0f65f48b SG	11	#include <errno.h>
336d4615	12	#include <malloc.h>
843a2654	13	#include <watchdog.h>
cfba4573	14	#include <serial.h>
998cf3c2	15	#include <debug_uart.h>
cfba4573	16	#include <linux/compiler.h>
c05ed00a	17	#include <linux/delay.h>
f93ae788	18
f93ae788	19	#include <asm/io.h>
0f65f48b SG	20	#ifdef CONFIG_DM_SERIAL
	21	#include <asm/arch/atmel_serial.h>
	22	#endif
df548d3c	23	#include <asm/arch/clk.h>
329f0f52	24	#include <asm/arch/hardware.h>
f93ae788 WD	25
	26	#include "atmel_usart.h"
	27
	28	DECLARE_GLOBAL_DATA_PTR;
	29
5f29e799	30	#ifndef CONFIG_DM_SERIAL
62137fc0 SG	31	static void atmel_serial_setbrg_internal(atmel_usart3_t *usart, int id,
62137fc0 SG	32	int baudrate)
f93ae788 WD	33	{
	34	unsigned long divisor;
	35	unsigned long usart_hz;
	36
	37	/*
	38	* Master Clock
	39	* Baud Rate = --------------
	40	* 16 * CD
	41	*/
62137fc0 SG	42	usart_hz = get_usart_clk_rate(id);
62137fc0 SG	43	divisor = (usart_hz / 16 + baudrate / 2) / baudrate;
125637c5	44	writel(USART3_BF(CD, divisor), &usart->brgr);
f93ae788 WD	45	}
f93ae788 WD	46
62137fc0	47	static void atmel_serial_init_internal(atmel_usart3_t *usart)
f93ae788	48	{
1f4faedd XH	49	/*
	50	* Just in case: drain transmitter register
	51	* 1000us is enough for baudrate >= 9600
	52	*/
	53	if (!(readl(&usart->csr) & USART3_BIT(TXEMPTY)))
	54	__udelay(1000);
	55
125637c5	56	writel(USART3_BIT(RSTRX) \| USART3_BIT(RSTTX), &usart->cr);
62137fc0	57	}
f93ae788	58
62137fc0 SG	59	static void atmel_serial_activate(atmel_usart3_t *usart)
62137fc0 SG	60	{
125637c5	61	writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
df548d3c HS	62	\| USART3_BF(USCLKS, USART3_USCLKS_MCK)
	63	\| USART3_BF(CHRL, USART3_CHRL_8)
	64	\| USART3_BF(PAR, USART3_PAR_NONE)
125637c5 AB	65	\| USART3_BF(NBSTOP, USART3_NBSTOP_1)),
125637c5 AB	66	&usart->mr);
1f4faedd XH	67	writel(USART3_BIT(RXEN) \| USART3_BIT(TXEN), &usart->cr);
	68	/* 100us is enough for the new settings to be settled */
	69	__udelay(100);
62137fc0 SG	70	}
	71
	72	static void atmel_serial_setbrg(void)
	73	{
	74	atmel_serial_setbrg_internal((atmel_usart3_t *)CONFIG_USART_BASE,
	75	CONFIG_USART_ID, gd->baudrate);
	76	}
	77
	78	static int atmel_serial_init(void)
	79	{
	80	atmel_usart3_t usart = (atmel_usart3_t )CONFIG_USART_BASE;
	81
	82	atmel_serial_init_internal(usart);
	83	serial_setbrg();
	84	atmel_serial_activate(usart);
f93ae788 WD	85
	86	return 0;
	87	}
	88
cfba4573	89	static void atmel_serial_putc(char c)
f93ae788	90	{
329f0f52	91	atmel_usart3_t usart = (atmel_usart3_t )CONFIG_USART_BASE;
125637c5	92
f93ae788 WD	93	if (c == '\n')
	94	serial_putc('\r');
	95
125637c5 AB	96	while (!(readl(&usart->csr) & USART3_BIT(TXRDY)));
125637c5 AB	97	writel(c, &usart->thr);
f93ae788 WD	98	}
f93ae788 WD	99
cfba4573	100	static int atmel_serial_getc(void)
f93ae788	101	{
329f0f52	102	atmel_usart3_t usart = (atmel_usart3_t )CONFIG_USART_BASE;
125637c5 AB	103
125637c5 AB	104	while (!(readl(&usart->csr) & USART3_BIT(RXRDY)))
843a2654	105	WATCHDOG_RESET();
125637c5	106	return readl(&usart->rhr);
f93ae788 WD	107	}
f93ae788 WD	108
cfba4573	109	static int atmel_serial_tstc(void)
f93ae788	110	{
329f0f52	111	atmel_usart3_t usart = (atmel_usart3_t )CONFIG_USART_BASE;
125637c5	112	return (readl(&usart->csr) & USART3_BIT(RXRDY)) != 0;
f93ae788	113	}
cfba4573	114
cfba4573 MV	115	static struct serial_device atmel_serial_drv = {
	116	.name = "atmel_serial",
	117	.start = atmel_serial_init,
	118	.stop = NULL,
	119	.setbrg = atmel_serial_setbrg,
	120	.putc = atmel_serial_putc,
ec3fd689	121	.puts = default_serial_puts,
cfba4573 MV	122	.getc = atmel_serial_getc,
	123	.tstc = atmel_serial_tstc,
	124	};
	125
	126	void atmel_serial_initialize(void)
	127	{
	128	serial_register(&atmel_serial_drv);
	129	}
	130
	131	__weak struct serial_device *default_serial_console(void)
	132	{
	133	return &atmel_serial_drv;
	134	}
0f65f48b SG	135	#endif
	136
	137	#ifdef CONFIG_DM_SERIAL
f8b7fff1 WY	138	enum serial_clk_type {
	139	CLK_TYPE_NORMAL = 0,
	140	CLK_TYPE_DBGU,
	141	};
0f65f48b SG	142
	143	struct atmel_serial_priv {
	144	atmel_usart3_t *usart;
f8b7fff1	145	ulong usart_clk_rate;
0f65f48b SG	146	};
0f65f48b SG	147
5f29e799 WY	148	static void _atmel_serial_set_brg(atmel_usart3_t *usart,
	149	ulong usart_clk_rate, int baudrate)
	150	{
	151	unsigned long divisor;
	152
	153	divisor = (usart_clk_rate / 16 + baudrate / 2) / baudrate;
	154	writel(USART3_BF(CD, divisor), &usart->brgr);
	155	}
	156
	157	void _atmel_serial_init(atmel_usart3_t *usart,
	158	ulong usart_clk_rate, int baudrate)
	159	{
	160	writel(USART3_BIT(RXDIS) \| USART3_BIT(TXDIS), &usart->cr);
	161
	162	writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL) \|
	163	USART3_BF(USCLKS, USART3_USCLKS_MCK) \|
	164	USART3_BF(CHRL, USART3_CHRL_8) \|
	165	USART3_BF(PAR, USART3_PAR_NONE) \|
	166	USART3_BF(NBSTOP, USART3_NBSTOP_1)), &usart->mr);
	167
	168	_atmel_serial_set_brg(usart, usart_clk_rate, baudrate);
	169
	170	writel(USART3_BIT(RSTRX) \| USART3_BIT(RSTTX), &usart->cr);
	171	writel(USART3_BIT(RXEN) \| USART3_BIT(TXEN), &usart->cr);
	172	}
	173
0f65f48b SG	174	int atmel_serial_setbrg(struct udevice *dev, int baudrate)
	175	{
	176	struct atmel_serial_priv *priv = dev_get_priv(dev);
	177
f8b7fff1	178	_atmel_serial_set_brg(priv->usart, priv->usart_clk_rate, baudrate);
0f65f48b SG	179
	180	return 0;
	181	}
	182
	183	static int atmel_serial_getc(struct udevice *dev)
	184	{
	185	struct atmel_serial_priv *priv = dev_get_priv(dev);
	186
	187	if (!(readl(&priv->usart->csr) & USART3_BIT(RXRDY)))
	188	return -EAGAIN;
	189
	190	return readl(&priv->usart->rhr);
	191	}
	192
	193	static int atmel_serial_putc(struct udevice *dev, const char ch)
	194	{
	195	struct atmel_serial_priv *priv = dev_get_priv(dev);
	196
	197	if (!(readl(&priv->usart->csr) & USART3_BIT(TXRDY)))
	198	return -EAGAIN;
	199
	200	writel(ch, &priv->usart->thr);
	201
	202	return 0;
	203	}
	204
	205	static int atmel_serial_pending(struct udevice *dev, bool input)
	206	{
	207	struct atmel_serial_priv *priv = dev_get_priv(dev);
	208	uint32_t csr = readl(&priv->usart->csr);
	209
	210	if (input)
	211	return csr & USART3_BIT(RXRDY) ? 1 : 0;
	212	else
	213	return csr & USART3_BIT(TXEMPTY) ? 0 : 1;
	214	}
	215
	216	static const struct dm_serial_ops atmel_serial_ops = {
	217	.putc = atmel_serial_putc,
	218	.pending = atmel_serial_pending,
	219	.getc = atmel_serial_getc,
	220	.setbrg = atmel_serial_setbrg,
	221	};
	222
e567dfb2 SR	223	#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_CLK)
	224	static int atmel_serial_enable_clk(struct udevice *dev)
	225	{
	226	struct atmel_serial_priv *priv = dev_get_priv(dev);
	227
	228	/* Use fixed clock value in SPL */
	229	priv->usart_clk_rate = CONFIG_SPL_UART_CLOCK;
	230
	231	return 0;
	232	}
	233	#else
f8b7fff1 WY	234	static int atmel_serial_enable_clk(struct udevice *dev)
	235	{
	236	struct atmel_serial_priv *priv = dev_get_priv(dev);
	237	struct clk clk;
	238	ulong clk_rate;
	239	int ret;
	240
	241	ret = clk_get_by_index(dev, 0, &clk);
	242	if (ret)
	243	return -EINVAL;
	244
	245	if (dev_get_driver_data(dev) == CLK_TYPE_NORMAL) {
	246	ret = clk_enable(&clk);
	247	if (ret)
	248	return ret;
	249	}
	250
	251	clk_rate = clk_get_rate(&clk);
	252	if (!clk_rate)
	253	return -EINVAL;
	254
	255	priv->usart_clk_rate = clk_rate;
	256
	257	clk_free(&clk);
	258
	259	return 0;
	260	}
e567dfb2	261	#endif
f8b7fff1	262
0f65f48b SG	263	static int atmel_serial_probe(struct udevice *dev)
	264	{
	265	struct atmel_serial_platdata *plat = dev->platdata;
	266	struct atmel_serial_priv *priv = dev_get_priv(dev);
f8b7fff1	267	int ret;
c1631c8a WY	268	#if CONFIG_IS_ENABLED(OF_CONTROL)
c1631c8a WY	269	fdt_addr_t addr_base;
0f65f48b	270
2548493a	271	addr_base = dev_read_addr(dev);
c1631c8a WY	272	if (addr_base == FDT_ADDR_T_NONE)
	273	return -ENODEV;
	274
	275	plat->base_addr = (uint32_t)addr_base;
	276	#endif
0f65f48b	277	priv->usart = (atmel_usart3_t *)plat->base_addr;
5f29e799	278
f8b7fff1 WY	279	ret = atmel_serial_enable_clk(dev);
	280	if (ret)
	281	return ret;
	282
	283	_atmel_serial_init(priv->usart, priv->usart_clk_rate, gd->baudrate);
0f65f48b SG	284
	285	return 0;
	286	}
	287
c1631c8a WY	288	#if CONFIG_IS_ENABLED(OF_CONTROL)
c1631c8a WY	289	static const struct udevice_id atmel_serial_ids[] = {
f8b7fff1 WY	290	{
	291	.compatible = "atmel,at91sam9260-dbgu",
	292	.data = CLK_TYPE_DBGU,
	293	},
	294	{
	295	.compatible = "atmel,at91sam9260-usart",
	296	.data = CLK_TYPE_NORMAL,
	297	},
c1631c8a WY	298	{ }
	299	};
	300	#endif
	301
0f65f48b SG	302	U_BOOT_DRIVER(serial_atmel) = {
	303	.name = "serial_atmel",
	304	.id = UCLASS_SERIAL,
c1631c8a WY	305	#if CONFIG_IS_ENABLED(OF_CONTROL)
	306	.of_match = atmel_serial_ids,
	307	.platdata_auto_alloc_size = sizeof(struct atmel_serial_platdata),
	308	#endif
0f65f48b SG	309	.probe = atmel_serial_probe,
0f65f48b SG	310	.ops = &atmel_serial_ops,
46879196	311	#if !CONFIG_IS_ENABLED(OF_CONTROL)
0f65f48b	312	.flags = DM_FLAG_PRE_RELOC,
46879196	313	#endif
0f65f48b SG	314	.priv_auto_alloc_size = sizeof(struct atmel_serial_priv),
	315	};
	316	#endif
998cf3c2 WY	317
	318	#ifdef CONFIG_DEBUG_UART_ATMEL
	319	static inline void _debug_uart_init(void)
	320	{
	321	atmel_usart3_t usart = (atmel_usart3_t )CONFIG_DEBUG_UART_BASE;
	322
5f29e799	323	_atmel_serial_init(usart, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
998cf3c2 WY	324	}
	325
	326	static inline void _debug_uart_putc(int ch)
	327	{
	328	atmel_usart3_t usart = (atmel_usart3_t )CONFIG_DEBUG_UART_BASE;
	329
	330	while (!(readl(&usart->csr) & USART3_BIT(TXRDY)))
	331	;
	332
	333	writel(ch, &usart->thr);
	334	}
	335
	336	DEBUG_UART_FUNCS
	337	#endif