]>
Commit | Line | Data |
---|---|---|
83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
4581b717 SW |
2 | /* |
3 | * Copyright (c) 2016, NVIDIA CORPORATION. | |
4581b717 SW |
4 | */ |
5 | ||
6 | #include <common.h> | |
7 | #include <dm.h> | |
f7ae49fc | 8 | #include <log.h> |
336d4615 | 9 | #include <malloc.h> |
4581b717 SW |
10 | #include <reset.h> |
11 | #include <asm/io.h> | |
12 | #include <asm/reset.h> | |
bad24331 | 13 | #include <linux/err.h> |
4581b717 SW |
14 | |
15 | struct sandbox_reset_test { | |
16 | struct reset_ctl ctl; | |
91f5f8b7 | 17 | struct reset_ctl_bulk bulk; |
bad24331 JJH |
18 | |
19 | struct reset_ctl *ctlp; | |
20 | struct reset_ctl_bulk *bulkp; | |
4581b717 SW |
21 | }; |
22 | ||
23 | int sandbox_reset_test_get(struct udevice *dev) | |
24 | { | |
25 | struct sandbox_reset_test *sbrt = dev_get_priv(dev); | |
26 | ||
bad24331 | 27 | sbrt->ctlp = &sbrt->ctl; |
4581b717 SW |
28 | return reset_get_by_name(dev, "test", &sbrt->ctl); |
29 | } | |
30 | ||
bad24331 JJH |
31 | int sandbox_reset_test_get_devm(struct udevice *dev) |
32 | { | |
33 | struct sandbox_reset_test *sbrt = dev_get_priv(dev); | |
34 | struct reset_ctl *r; | |
35 | ||
36 | r = devm_reset_control_get(dev, "not-a-valid-reset-ctl"); | |
37 | if (!IS_ERR(r)) | |
38 | return -EINVAL; | |
39 | ||
40 | r = devm_reset_control_get_optional(dev, "not-a-valid-reset-ctl"); | |
41 | if (r) | |
42 | return -EINVAL; | |
43 | ||
44 | sbrt->ctlp = devm_reset_control_get(dev, "test"); | |
45 | if (IS_ERR(sbrt->ctlp)) | |
46 | return PTR_ERR(sbrt->ctlp); | |
47 | ||
48 | return 0; | |
49 | } | |
50 | ||
91f5f8b7 NA |
51 | int sandbox_reset_test_get_bulk(struct udevice *dev) |
52 | { | |
53 | struct sandbox_reset_test *sbrt = dev_get_priv(dev); | |
54 | ||
bad24331 | 55 | sbrt->bulkp = &sbrt->bulk; |
91f5f8b7 NA |
56 | return reset_get_bulk(dev, &sbrt->bulk); |
57 | } | |
58 | ||
bad24331 JJH |
59 | int sandbox_reset_test_get_bulk_devm(struct udevice *dev) |
60 | { | |
61 | struct sandbox_reset_test *sbrt = dev_get_priv(dev); | |
62 | struct reset_ctl_bulk *r; | |
63 | ||
64 | r = devm_reset_bulk_get_optional(dev); | |
65 | if (IS_ERR(r)) | |
66 | return PTR_ERR(r); | |
67 | ||
68 | sbrt->bulkp = r; | |
69 | return 0; | |
70 | } | |
71 | ||
4581b717 SW |
72 | int sandbox_reset_test_assert(struct udevice *dev) |
73 | { | |
74 | struct sandbox_reset_test *sbrt = dev_get_priv(dev); | |
75 | ||
bad24331 | 76 | return reset_assert(sbrt->ctlp); |
4581b717 SW |
77 | } |
78 | ||
91f5f8b7 NA |
79 | int sandbox_reset_test_assert_bulk(struct udevice *dev) |
80 | { | |
81 | struct sandbox_reset_test *sbrt = dev_get_priv(dev); | |
82 | ||
bad24331 | 83 | return reset_assert_bulk(sbrt->bulkp); |
91f5f8b7 NA |
84 | } |
85 | ||
4581b717 SW |
86 | int sandbox_reset_test_deassert(struct udevice *dev) |
87 | { | |
88 | struct sandbox_reset_test *sbrt = dev_get_priv(dev); | |
89 | ||
bad24331 | 90 | return reset_deassert(sbrt->ctlp); |
4581b717 SW |
91 | } |
92 | ||
91f5f8b7 NA |
93 | int sandbox_reset_test_deassert_bulk(struct udevice *dev) |
94 | { | |
95 | struct sandbox_reset_test *sbrt = dev_get_priv(dev); | |
96 | ||
bad24331 | 97 | return reset_deassert_bulk(sbrt->bulkp); |
91f5f8b7 NA |
98 | } |
99 | ||
4581b717 SW |
100 | int sandbox_reset_test_free(struct udevice *dev) |
101 | { | |
102 | struct sandbox_reset_test *sbrt = dev_get_priv(dev); | |
103 | ||
bad24331 | 104 | return reset_free(sbrt->ctlp); |
4581b717 SW |
105 | } |
106 | ||
91f5f8b7 NA |
107 | int sandbox_reset_test_release_bulk(struct udevice *dev) |
108 | { | |
109 | struct sandbox_reset_test *sbrt = dev_get_priv(dev); | |
110 | ||
bad24331 | 111 | return reset_release_bulk(sbrt->bulkp); |
91f5f8b7 NA |
112 | } |
113 | ||
4581b717 SW |
114 | static const struct udevice_id sandbox_reset_test_ids[] = { |
115 | { .compatible = "sandbox,reset-ctl-test" }, | |
116 | { } | |
117 | }; | |
118 | ||
119 | U_BOOT_DRIVER(sandbox_reset_test) = { | |
120 | .name = "sandbox_reset_test", | |
121 | .id = UCLASS_MISC, | |
122 | .of_match = sandbox_reset_test_ids, | |
41575d8e | 123 | .priv_auto = sizeof(struct sandbox_reset_test), |
4581b717 | 124 | }; |