[J-u-boot.git] / include / fsl_ddr_dimm_params.h

/*
 * Copyright 2008-2014 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

#ifndef DDR2_DIMM_PARAMS_H
#define DDR2_DIMM_PARAMS_H

#define EDC_DATA_PARITY	1
#define EDC_ECC		2
#define EDC_AC_PARITY	4

/* Parameters for a DDR dimm computed from the SPD */
typedef struct dimm_params_s {

	/* DIMM organization parameters */
	char mpart[19];		/* guaranteed null terminated */

	unsigned int n_ranks;
	unsigned long long rank_density;
	unsigned long long capacity;
	unsigned int data_width;
	unsigned int primary_sdram_width;
	unsigned int ec_sdram_width;
	unsigned int registered_dimm;
	unsigned int device_width;	/* x4, x8, x16 components */

	/* SDRAM device parameters */
	unsigned int n_row_addr;
	unsigned int n_col_addr;
	unsigned int edc_config;	/* 0 = none, 1 = parity, 2 = ECC */
#ifdef CONFIG_SYS_FSL_DDR4
	unsigned int bank_addr_bits;
	unsigned int bank_group_bits;
#else
	unsigned int n_banks_per_sdram_device;
#endif
	unsigned int burst_lengths_bitmask;	/* BL=4 bit 2, BL=8 = bit 3 */
	unsigned int row_density;

	/* used in computing base address of DIMMs */
	unsigned long long base_address;
	/* mirrored DIMMs */
	unsigned int mirrored_dimm;	/* only for ddr3 */

	/* DIMM timing parameters */

	int mtb_ps;	/* medium timebase ps */
	int ftb_10th_ps; /* fine timebase, in 1/10 ps */
	int taa_ps;	/* minimum CAS latency time */
	int tfaw_ps;	/* four active window delay */

	/*
	 * SDRAM clock periods
	 * The range for these are 1000-10000 so a short should be sufficient
	 */
	int tckmin_x_ps;
	int tckmin_x_minus_1_ps;
	int tckmin_x_minus_2_ps;
	int tckmax_ps;

	/* SPD-defined CAS latencies */
	unsigned int caslat_x;
	unsigned int caslat_x_minus_1;
	unsigned int caslat_x_minus_2;

	unsigned int caslat_lowest_derated;	/* Derated CAS latency */

	/* basic timing parameters */
	int trcd_ps;
	int trp_ps;
	int tras_ps;

#ifdef CONFIG_SYS_FSL_DDR4
	int trfc1_ps;
	int trfc2_ps;
	int trfc4_ps;
	int trrds_ps;
	int trrdl_ps;
	int tccdl_ps;
#else
	int twr_ps;	/* maximum = 63750 ps */
	int trfc_ps;	/* max = 255 ns + 256 ns + .75 ns
				       = 511750 ps */
	int trrd_ps;	/* maximum = 63750 ps */
	int twtr_ps;	/* maximum = 63750 ps */
	int trtp_ps;	/* byte 38, spd->trtp */
#endif

	int trc_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */

	int refresh_rate_ps;
	int extended_op_srt;

#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
	int tis_ps;	/* byte 32, spd->ca_setup */
	int tih_ps;	/* byte 33, spd->ca_hold */
	int tds_ps;	/* byte 34, spd->data_setup */
	int tdh_ps;	/* byte 35, spd->data_hold */
	int tdqsq_max_ps;	/* byte 44, spd->tdqsq */
	int tqhs_ps;	/* byte 45, spd->tqhs */
#endif

	/* DDR3 RDIMM */
	unsigned char rcw[16];	/* Register Control Word 0-15 */
#ifdef CONFIG_SYS_FSL_DDR4
	unsigned int dq_mapping[18];
	unsigned int dq_mapping_ors;
#endif
} dimm_params_t;

unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
					 const generic_spd_eeprom_t *spd,
					 dimm_params_t *pdimm,
					 unsigned int dimm_number);

#endif
Commit	Line	Data
58e5e9af	1	/*
34e026f9	2	* Copyright 2008-2014 Freescale Semiconductor, Inc.
58e5e9af	3	*
5b8031cc	4	* SPDX-License-Identifier: GPL-2.0
58e5e9af KG	5	*/
	6
	7	#ifndef DDR2_DIMM_PARAMS_H
	8	#define DDR2_DIMM_PARAMS_H
	9
08b3f759 YS	10	#define EDC_DATA_PARITY 1
	11	#define EDC_ECC 2
	12	#define EDC_AC_PARITY 4
	13
34e026f9	14	/* Parameters for a DDR dimm computed from the SPD */
58e5e9af KG	15	typedef struct dimm_params_s {
	16
	17	/* DIMM organization parameters */
	18	char mpart[19]; /* guaranteed null terminated */
	19
	20	unsigned int n_ranks;
	21	unsigned long long rank_density;
	22	unsigned long long capacity;
	23	unsigned int data_width;
	24	unsigned int primary_sdram_width;
	25	unsigned int ec_sdram_width;
	26	unsigned int registered_dimm;
b61e0615	27	unsigned int device_width; /* x4, x8, x16 components */
58e5e9af KG	28
	29	/* SDRAM device parameters */
	30	unsigned int n_row_addr;
	31	unsigned int n_col_addr;
	32	unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */
34e026f9 YS	33	#ifdef CONFIG_SYS_FSL_DDR4
	34	unsigned int bank_addr_bits;
	35	unsigned int bank_group_bits;
	36	#else
58e5e9af	37	unsigned int n_banks_per_sdram_device;
34e026f9	38	#endif
58e5e9af KG	39	unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */
	40	unsigned int row_density;
	41
	42	/* used in computing base address of DIMMs */
	43	unsigned long long base_address;
c360ceac DL	44	/* mirrored DIMMs */
c360ceac DL	45	unsigned int mirrored_dimm; /* only for ddr3 */
58e5e9af KG	46
	47	/* DIMM timing parameters */
	48
34e026f9 YS	49	int mtb_ps; /* medium timebase ps */
	50	int ftb_10th_ps; /* fine timebase, in 1/10 ps */
	51	int taa_ps; /* minimum CAS latency time */
	52	int tfaw_ps; /* four active window delay */
c360ceac	53
58e5e9af KG	54	/*
	55	* SDRAM clock periods
	56	* The range for these are 1000-10000 so a short should be sufficient
	57	*/
34e026f9 YS	58	int tckmin_x_ps;
	59	int tckmin_x_minus_1_ps;
	60	int tckmin_x_minus_2_ps;
	61	int tckmax_ps;
58e5e9af KG	62
58e5e9af KG	63	/* SPD-defined CAS latencies */
0dd38a35 PJ	64	unsigned int caslat_x;
	65	unsigned int caslat_x_minus_1;
	66	unsigned int caslat_x_minus_2;
58e5e9af KG	67
	68	unsigned int caslat_lowest_derated; /* Derated CAS latency */
	69
	70	/* basic timing parameters */
34e026f9 YS	71	int trcd_ps;
	72	int trp_ps;
	73	int tras_ps;
	74
	75	#ifdef CONFIG_SYS_FSL_DDR4
	76	int trfc1_ps;
	77	int trfc2_ps;
	78	int trfc4_ps;
	79	int trrds_ps;
	80	int trrdl_ps;
	81	int tccdl_ps;
	82	#else
	83	int twr_ps; /* maximum = 63750 ps */
	84	int trfc_ps; /* max = 255 ns + 256 ns + .75 ns
58e5e9af	85	= 511750 ps */
34e026f9 YS	86	int trrd_ps; /* maximum = 63750 ps */
	87	int twtr_ps; /* maximum = 63750 ps */
	88	int trtp_ps; /* byte 38, spd->trtp */
	89	#endif
58e5e9af	90
34e026f9	91	int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
58e5e9af	92
34e026f9 YS	93	int refresh_rate_ps;
34e026f9 YS	94	int extended_op_srt;
58e5e9af	95
34e026f9 YS	96	#if defined(CONFIG_SYS_FSL_DDR1) \|\| defined(CONFIG_SYS_FSL_DDR2)
	97	int tis_ps; /* byte 32, spd->ca_setup */
	98	int tih_ps; /* byte 33, spd->ca_hold */
	99	int tds_ps; /* byte 34, spd->data_setup */
	100	int tdh_ps; /* byte 35, spd->data_hold */
	101	int tdqsq_max_ps; /* byte 44, spd->tdqsq */
	102	int tqhs_ps; /* byte 45, spd->tqhs */
	103	#endif
9490ff48 YS	104
	105	/* DDR3 RDIMM */
	106	unsigned char rcw[16]; /* Register Control Word 0-15 */
34e026f9 YS	107	#ifdef CONFIG_SYS_FSL_DDR4
	108	unsigned int dq_mapping[18];
	109	unsigned int dq_mapping_ors;
	110	#endif
58e5e9af KG	111	} dimm_params_t;
58e5e9af KG	112
03e664d8	113	unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
58e5e9af KG	114	const generic_spd_eeprom_t *spd,
	115	dimm_params_t *pdimm,
	116	unsigned int dimm_number);
	117
	118	#endif