[J-u-boot.git] / drivers / mmc / bfin_sdh.c

/*
 * Driver for Blackfin on-chip SDH controller
 *
 * Copyright (c) 2008-2009 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#include <common.h>
#include <malloc.h>
#include <part.h>
#include <mmc.h>

#include <asm/io.h>
#include <asm/errno.h>
#include <asm/byteorder.h>
#include <asm/blackfin.h>
#include <asm/portmux.h>
#include <asm/mach-common/bits/sdh.h>
#include <asm/mach-common/bits/dma.h>

#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__)
# define bfin_read_SDH_PWR_CTL		bfin_read_RSI_PWR_CONTROL
# define bfin_write_SDH_PWR_CTL		bfin_write_RSI_PWR_CONTROL
# define bfin_read_SDH_CLK_CTL		bfin_read_RSI_CLK_CONTROL
# define bfin_write_SDH_CLK_CTL		bfin_write_RSI_CLK_CONTROL
# define bfin_write_SDH_ARGUMENT	bfin_write_RSI_ARGUMENT
# define bfin_write_SDH_COMMAND		bfin_write_RSI_COMMAND
# define bfin_read_SDH_RESPONSE0	bfin_read_RSI_RESPONSE0
# define bfin_read_SDH_RESPONSE1	bfin_read_RSI_RESPONSE1
# define bfin_read_SDH_RESPONSE2	bfin_read_RSI_RESPONSE2
# define bfin_read_SDH_RESPONSE3	bfin_read_RSI_RESPONSE3
# define bfin_write_SDH_DATA_TIMER	bfin_write_RSI_DATA_TIMER
# define bfin_write_SDH_DATA_LGTH	bfin_write_RSI_DATA_LGTH
# define bfin_read_SDH_DATA_CTL		bfin_read_RSI_DATA_CONTROL
# define bfin_write_SDH_DATA_CTL	bfin_write_RSI_DATA_CONTROL
# define bfin_read_SDH_STATUS		bfin_read_RSI_STATUS
# define bfin_write_SDH_STATUS_CLR 	bfin_write_RSI_STATUSCL
# define bfin_read_SDH_CFG		bfin_read_RSI_CONFIG
# define bfin_write_SDH_CFG		bfin_write_RSI_CONFIG
# define bfin_write_DMA_START_ADDR	bfin_write_DMA4_START_ADDR
# define bfin_write_DMA_X_COUNT		bfin_write_DMA4_X_COUNT
# define bfin_write_DMA_X_MODIFY	bfin_write_DMA4_X_MODIFY
# define bfin_write_DMA_CONFIG		bfin_write_DMA4_CONFIG
# define PORTMUX_PINS \
	{ P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0 }
#elif defined(__ADSPBF54x__)
# define bfin_write_DMA_START_ADDR	bfin_write_DMA22_START_ADDR
# define bfin_write_DMA_X_COUNT		bfin_write_DMA22_X_COUNT
# define bfin_write_DMA_X_MODIFY	bfin_write_DMA22_X_MODIFY
# define bfin_write_DMA_CONFIG		bfin_write_DMA22_CONFIG
# define PORTMUX_PINS \
	{ P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0 }
#else
# error no support for this proc yet
#endif

static int
sdh_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
{
	unsigned int status, timeout;
	int cmd = mmc_cmd->cmdidx;
	int flags = mmc_cmd->resp_type;
	int arg = mmc_cmd->cmdarg;
	int ret;
	u16 sdh_cmd;

	sdh_cmd = cmd | CMD_E;
	if (flags & MMC_RSP_PRESENT)
		sdh_cmd |= CMD_RSP;
	if (flags & MMC_RSP_136)
		sdh_cmd |= CMD_L_RSP;

	bfin_write_SDH_ARGUMENT(arg);
	bfin_write_SDH_COMMAND(sdh_cmd);

	/* wait for a while */
	timeout = 0;
	do {
		if (++timeout > 1000000) {
			status = CMD_TIME_OUT;
			break;
		}
		udelay(1);
		status = bfin_read_SDH_STATUS();
	} while (!(status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT |
		CMD_CRC_FAIL)));

	if (flags & MMC_RSP_PRESENT) {
		mmc_cmd->response[0] = bfin_read_SDH_RESPONSE0();
		if (flags & MMC_RSP_136) {
			mmc_cmd->response[1] = bfin_read_SDH_RESPONSE1();
			mmc_cmd->response[2] = bfin_read_SDH_RESPONSE2();
			mmc_cmd->response[3] = bfin_read_SDH_RESPONSE3();
		}
	}

	if (status & CMD_TIME_OUT)
		ret = TIMEOUT;
	else if (status & CMD_CRC_FAIL && flags & MMC_RSP_CRC)
		ret = COMM_ERR;
	else
		ret = 0;

	bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT |
				CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);

	return ret;
}

/* set data for single block transfer */
static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data)
{
	u16 data_ctl = 0;
	u16 dma_cfg = 0;
	int ret = 0;
	unsigned long data_size = data->blocksize * data->blocks;

	/* Don't support write yet. */
	if (data->flags & MMC_DATA_WRITE)
		return UNUSABLE_ERR;
	data_ctl |= ((ffs(data_size) - 1) << 4);
	data_ctl |= DTX_DIR;
	bfin_write_SDH_DATA_CTL(data_ctl);
	dma_cfg = WDSIZE_32 | RESTART | WNR | DMAEN;

	bfin_write_SDH_DATA_TIMER(-1);

	blackfin_dcache_flush_invalidate_range(data->dest,
			data->dest + data_size);
	/* configure DMA */
	bfin_write_DMA_START_ADDR(data->dest);
	bfin_write_DMA_X_COUNT(data_size / 4);
	bfin_write_DMA_X_MODIFY(4);
	bfin_write_DMA_CONFIG(dma_cfg);
	bfin_write_SDH_DATA_LGTH(data_size);
	/* kick off transfer */
	bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);

	return ret;
}


static int bfin_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd,
		struct mmc_data *data)
{
	u32 status;
	int ret = 0;

	ret = sdh_send_cmd(mmc, cmd);
	if (ret) {
		printf("sending CMD%d failed\n", cmd->cmdidx);
		return ret;
	}
	if (data) {
		ret = sdh_setup_data(mmc, data);
		do {
			udelay(1);
			status = bfin_read_SDH_STATUS();
		} while (!(status & (DAT_BLK_END | DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN)));

		if (status & DAT_TIME_OUT) {
			bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT);
			ret |= TIMEOUT;
		} else if (status & (DAT_CRC_FAIL | RX_OVERRUN)) {
			bfin_write_SDH_STATUS_CLR(DAT_CRC_FAIL_STAT | RX_OVERRUN_STAT);
			ret |= COMM_ERR;
		} else
			bfin_write_SDH_STATUS_CLR(DAT_BLK_END_STAT | DAT_END_STAT);

		if (ret) {
			printf("tranfering data failed\n");
			return ret;
		}
	}
	return 0;
}

static void sdh_set_clk(unsigned long clk)
{
	unsigned long sys_clk;
	unsigned long clk_div;
	u16 clk_ctl = 0;

	clk_ctl = bfin_read_SDH_CLK_CTL();
	if (clk) {
		/* setting SD_CLK */
		sys_clk = get_sclk();
		bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
		if (sys_clk % (2 * clk) == 0)
			clk_div = sys_clk / (2 * clk) - 1;
		else
			clk_div = sys_clk / (2 * clk);

		if (clk_div > 0xff)
			clk_div = 0xff;
		clk_ctl |= (clk_div & 0xff);
		clk_ctl |= CLK_E;
		bfin_write_SDH_CLK_CTL(clk_ctl);
	} else
		bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
}

static void bfin_sdh_set_ios(struct mmc *mmc)
{
	u16 cfg = 0;
	u16 clk_ctl = 0;

	if (mmc->bus_width == 4) {
		cfg = bfin_read_SDH_CFG();
		cfg &= ~0x80;
		cfg |= 0x40;
		bfin_write_SDH_CFG(cfg);
		clk_ctl |= WIDE_BUS;
	}
	bfin_write_SDH_CLK_CTL(clk_ctl);
	sdh_set_clk(mmc->clock);
}

static int bfin_sdh_init(struct mmc *mmc)
{
	const unsigned short pins[] = PORTMUX_PINS;
	u16 pwr_ctl = 0;

	/* Initialize sdh controller */
	peripheral_request_list(pins, "bfin_sdh");
#if defined(__ADSPBF54x__)
	bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
#endif
	bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
	/* Disable card detect pin */
	bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | 0x60);

	pwr_ctl |= ROD_CTL;
	pwr_ctl |= PWR_ON;
	bfin_write_SDH_PWR_CTL(pwr_ctl);
	return 0;
}


int bfin_mmc_init(bd_t *bis)
{
	struct mmc *mmc = NULL;

	mmc = malloc(sizeof(struct mmc));

	if (!mmc)
		return -ENOMEM;
	sprintf(mmc->name, "Blackfin SDH");
	mmc->send_cmd = bfin_sdh_request;
	mmc->set_ios = bfin_sdh_set_ios;
	mmc->init = bfin_sdh_init;
	mmc->getcd = NULL;
	mmc->getwp = NULL;
	mmc->host_caps = MMC_MODE_4BIT;

	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
	mmc->f_max = get_sclk();
	mmc->f_min = mmc->f_max >> 9;

	mmc->b_max = 0;

	mmc_register(mmc);

	return 0;
}
Commit	Line	Data
716ebf43 CC	1	/*
	2	* Driver for Blackfin on-chip SDH controller
	3	*
e54c8209	4	* Copyright (c) 2008-2009 Analog Devices Inc.
716ebf43 CC	5	*
	6	* Licensed under the GPL-2 or later.
	7	*/
	8
	9	#include <common.h>
	10	#include <malloc.h>
	11	#include <part.h>
	12	#include <mmc.h>
	13
	14	#include <asm/io.h>
	15	#include <asm/errno.h>
	16	#include <asm/byteorder.h>
	17	#include <asm/blackfin.h>
a87589fc	18	#include <asm/portmux.h>
716ebf43 CC	19	#include <asm/mach-common/bits/sdh.h>
	20	#include <asm/mach-common/bits/dma.h>
	21
cca07417	22	#if defined(__ADSPBF50x__) \|\| defined(__ADSPBF51x__)
716ebf43 CC	23	# define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CONTROL
	24	# define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CONTROL
	25	# define bfin_read_SDH_CLK_CTL bfin_read_RSI_CLK_CONTROL
	26	# define bfin_write_SDH_CLK_CTL bfin_write_RSI_CLK_CONTROL
	27	# define bfin_write_SDH_ARGUMENT bfin_write_RSI_ARGUMENT
	28	# define bfin_write_SDH_COMMAND bfin_write_RSI_COMMAND
	29	# define bfin_read_SDH_RESPONSE0 bfin_read_RSI_RESPONSE0
	30	# define bfin_read_SDH_RESPONSE1 bfin_read_RSI_RESPONSE1
	31	# define bfin_read_SDH_RESPONSE2 bfin_read_RSI_RESPONSE2
	32	# define bfin_read_SDH_RESPONSE3 bfin_read_RSI_RESPONSE3
	33	# define bfin_write_SDH_DATA_TIMER bfin_write_RSI_DATA_TIMER
	34	# define bfin_write_SDH_DATA_LGTH bfin_write_RSI_DATA_LGTH
	35	# define bfin_read_SDH_DATA_CTL bfin_read_RSI_DATA_CONTROL
	36	# define bfin_write_SDH_DATA_CTL bfin_write_RSI_DATA_CONTROL
	37	# define bfin_read_SDH_STATUS bfin_read_RSI_STATUS
	38	# define bfin_write_SDH_STATUS_CLR bfin_write_RSI_STATUSCL
	39	# define bfin_read_SDH_CFG bfin_read_RSI_CONFIG
	40	# define bfin_write_SDH_CFG bfin_write_RSI_CONFIG
	41	# define bfin_write_DMA_START_ADDR bfin_write_DMA4_START_ADDR
	42	# define bfin_write_DMA_X_COUNT bfin_write_DMA4_X_COUNT
	43	# define bfin_write_DMA_X_MODIFY bfin_write_DMA4_X_MODIFY
	44	# define bfin_write_DMA_CONFIG bfin_write_DMA4_CONFIG
a87589fc MF	45	# define PORTMUX_PINS \
a87589fc MF	46	{ P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0 }
716ebf43 CC	47	#elif defined(__ADSPBF54x__)
	48	# define bfin_write_DMA_START_ADDR bfin_write_DMA22_START_ADDR
	49	# define bfin_write_DMA_X_COUNT bfin_write_DMA22_X_COUNT
	50	# define bfin_write_DMA_X_MODIFY bfin_write_DMA22_X_MODIFY
	51	# define bfin_write_DMA_CONFIG bfin_write_DMA22_CONFIG
a87589fc MF	52	# define PORTMUX_PINS \
a87589fc MF	53	{ P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0 }
716ebf43 CC	54	#else
	55	# error no support for this proc yet
	56	#endif
	57
716ebf43	58	static int
e54c8209	59	sdh_send_cmd(struct mmc mmc, struct mmc_cmd mmc_cmd)
716ebf43	60	{
6815f540	61	unsigned int status, timeout;
e54c8209 CC	62	int cmd = mmc_cmd->cmdidx;
	63	int flags = mmc_cmd->resp_type;
	64	int arg = mmc_cmd->cmdarg;
6815f540 MF	65	int ret;
6815f540 MF	66	u16 sdh_cmd;
716ebf43	67
6815f540	68	sdh_cmd = cmd \| CMD_E;
716ebf43 CC	69	if (flags & MMC_RSP_PRESENT)
716ebf43 CC	70	sdh_cmd \|= CMD_RSP;
716ebf43 CC	71	if (flags & MMC_RSP_136)
	72	sdh_cmd \|= CMD_L_RSP;
	73
	74	bfin_write_SDH_ARGUMENT(arg);
6815f540	75	bfin_write_SDH_COMMAND(sdh_cmd);
716ebf43 CC	76
716ebf43 CC	77	/* wait for a while */
6815f540	78	timeout = 0;
716ebf43	79	do {
6815f540 MF	80	if (++timeout > 1000000) {
	81	status = CMD_TIME_OUT;
	82	break;
	83	}
716ebf43 CC	84	udelay(1);
	85	status = bfin_read_SDH_STATUS();
	86	} while (!(status & (CMD_SENT \| CMD_RESP_END \| CMD_TIME_OUT \|
	87	CMD_CRC_FAIL)));
	88
	89	if (flags & MMC_RSP_PRESENT) {
e54c8209	90	mmc_cmd->response[0] = bfin_read_SDH_RESPONSE0();
716ebf43	91	if (flags & MMC_RSP_136) {
e54c8209 CC	92	mmc_cmd->response[1] = bfin_read_SDH_RESPONSE1();
	93	mmc_cmd->response[2] = bfin_read_SDH_RESPONSE2();
	94	mmc_cmd->response[3] = bfin_read_SDH_RESPONSE3();
716ebf43 CC	95	}
	96	}
	97
e54c8209	98	if (status & CMD_TIME_OUT)
6815f540	99	ret = TIMEOUT;
e54c8209	100	else if (status & CMD_CRC_FAIL && flags & MMC_RSP_CRC)
6815f540 MF	101	ret = COMM_ERR;
	102	else
	103	ret = 0;
e54c8209	104
716ebf43 CC	105	bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT \| CMD_RESP_END_STAT \|
716ebf43 CC	106	CMD_TIMEOUT_STAT \| CMD_CRC_FAIL_STAT);
6815f540	107
716ebf43 CC	108	return ret;
	109	}
	110
e54c8209 CC	111	/* set data for single block transfer */
e54c8209 CC	112	static int sdh_setup_data(struct mmc mmc, struct mmc_data data)
716ebf43	113	{
e54c8209 CC	114	u16 data_ctl = 0;
e54c8209 CC	115	u16 dma_cfg = 0;
716ebf43	116	int ret = 0;
21a50374	117	unsigned long data_size = data->blocksize * data->blocks;
716ebf43	118
e54c8209 CC	119	/* Don't support write yet. */
	120	if (data->flags & MMC_DATA_WRITE)
	121	return UNUSABLE_ERR;
21a50374	122	data_ctl \|= ((ffs(data_size) - 1) << 4);
716ebf43 CC	123	data_ctl \|= DTX_DIR;
716ebf43 CC	124	bfin_write_SDH_DATA_CTL(data_ctl);
e54c8209	125	dma_cfg = WDSIZE_32 \| RESTART \| WNR \| DMAEN;
716ebf43	126
1fd2d792	127	bfin_write_SDH_DATA_TIMER(-1);
716ebf43	128
e54c8209	129	blackfin_dcache_flush_invalidate_range(data->dest,
21a50374	130	data->dest + data_size);
e54c8209 CC	131	/* configure DMA */
e54c8209 CC	132	bfin_write_DMA_START_ADDR(data->dest);
21a50374	133	bfin_write_DMA_X_COUNT(data_size / 4);
e54c8209 CC	134	bfin_write_DMA_X_MODIFY(4);
e54c8209 CC	135	bfin_write_DMA_CONFIG(dma_cfg);
21a50374	136	bfin_write_SDH_DATA_LGTH(data_size);
e54c8209 CC	137	/* kick off transfer */
e54c8209 CC	138	bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() \| DTX_DMA_E \| DTX_E);
716ebf43	139
e54c8209	140	return ret;
716ebf43 CC	141	}
716ebf43 CC	142
e54c8209 CC	143
	144	static int bfin_sdh_request(struct mmc mmc, struct mmc_cmd cmd,
	145	struct mmc_data *data)
716ebf43	146	{
e54c8209 CC	147	u32 status;
e54c8209 CC	148	int ret = 0;
716ebf43	149
e54c8209 CC	150	ret = sdh_send_cmd(mmc, cmd);
	151	if (ret) {
	152	printf("sending CMD%d failed\n", cmd->cmdidx);
	153	return ret;
	154	}
	155	if (data) {
	156	ret = sdh_setup_data(mmc, data);
716ebf43 CC	157	do {
	158	udelay(1);
	159	status = bfin_read_SDH_STATUS();
e54c8209	160	} while (!(status & (DAT_BLK_END \| DAT_END \| DAT_TIME_OUT \| DAT_CRC_FAIL \| RX_OVERRUN)));
716ebf43	161
e54c8209 CC	162	if (status & DAT_TIME_OUT) {
	163	bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT);
	164	ret \|= TIMEOUT;
	165	} else if (status & (DAT_CRC_FAIL \| RX_OVERRUN)) {
	166	bfin_write_SDH_STATUS_CLR(DAT_CRC_FAIL_STAT \| RX_OVERRUN_STAT);
	167	ret \|= COMM_ERR;
	168	} else
716ebf43	169	bfin_write_SDH_STATUS_CLR(DAT_BLK_END_STAT \| DAT_END_STAT);
e54c8209 CC	170
	171	if (ret) {
	172	printf("tranfering data failed\n");
	173	return ret;
716ebf43 CC	174	}
716ebf43 CC	175	}
e54c8209	176	return 0;
716ebf43 CC	177	}
716ebf43 CC	178
e54c8209	179	static void sdh_set_clk(unsigned long clk)
716ebf43	180	{
e54c8209 CC	181	unsigned long sys_clk;
	182	unsigned long clk_div;
	183	u16 clk_ctl = 0;
	184
	185	clk_ctl = bfin_read_SDH_CLK_CTL();
	186	if (clk) {
	187	/* setting SD_CLK */
	188	sys_clk = get_sclk();
	189	bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
	190	if (sys_clk % (2 * clk) == 0)
	191	clk_div = sys_clk / (2 * clk) - 1;
	192	else
	193	clk_div = sys_clk / (2 * clk);
	194
	195	if (clk_div > 0xff)
	196	clk_div = 0xff;
	197	clk_ctl \|= (clk_div & 0xff);
	198	clk_ctl \|= CLK_E;
	199	bfin_write_SDH_CLK_CTL(clk_ctl);
	200	} else
	201	bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
716ebf43 CC	202	}
716ebf43 CC	203
e54c8209	204	static void bfin_sdh_set_ios(struct mmc *mmc)
716ebf43	205	{
e54c8209 CC	206	u16 cfg = 0;
	207	u16 clk_ctl = 0;
	208
	209	if (mmc->bus_width == 4) {
	210	cfg = bfin_read_SDH_CFG();
	211	cfg &= ~0x80;
	212	cfg \|= 0x40;
	213	bfin_write_SDH_CFG(cfg);
	214	clk_ctl \|= WIDE_BUS;
716ebf43	215	}
e54c8209 CC	216	bfin_write_SDH_CLK_CTL(clk_ctl);
e54c8209 CC	217	sdh_set_clk(mmc->clock);
716ebf43 CC	218	}
716ebf43 CC	219
e54c8209	220	static int bfin_sdh_init(struct mmc *mmc)
716ebf43	221	{
a87589fc	222	const unsigned short pins[] = PORTMUX_PINS;
e54c8209	223	u16 pwr_ctl = 0;
a87589fc MF	224
	225	/* Initialize sdh controller */
	226	peripheral_request_list(pins, "bfin_sdh");
716ebf43 CC	227	#if defined(__ADSPBF54x__)
716ebf43 CC	228	bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() \| 0x1);
716ebf43 CC	229	#endif
	230	bfin_write_SDH_CFG(bfin_read_SDH_CFG() \| CLKS_EN);
	231	/* Disable card detect pin */
	232	bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) \| 0x60);
e54c8209	233
716ebf43 CC	234	pwr_ctl \|= ROD_CTL;
	235	pwr_ctl \|= PWR_ON;
	236	bfin_write_SDH_PWR_CTL(pwr_ctl);
716ebf43 CC	237	return 0;
	238	}
	239
e54c8209 CC	240
e54c8209 CC	241	int bfin_mmc_init(bd_t *bis)
716ebf43	242	{
e54c8209 CC	243	struct mmc *mmc = NULL;
	244
	245	mmc = malloc(sizeof(struct mmc));
	246
	247	if (!mmc)
	248	return -ENOMEM;
	249	sprintf(mmc->name, "Blackfin SDH");
	250	mmc->send_cmd = bfin_sdh_request;
	251	mmc->set_ios = bfin_sdh_set_ios;
	252	mmc->init = bfin_sdh_init;
48972d90	253	mmc->getcd = NULL;
d23d8d7e	254	mmc->getwp = NULL;
e54c8209 CC	255	mmc->host_caps = MMC_MODE_4BIT;
	256
	257	mmc->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34;
	258	mmc->f_max = get_sclk();
	259	mmc->f_min = mmc->f_max >> 9;
e54c8209	260
8feafcc4 JR	261	mmc->b_max = 0;
8feafcc4 JR	262
e54c8209 CC	263	mmc_register(mmc);
e54c8209 CC	264
716ebf43 CC	265	return 0;
716ebf43 CC	266	}