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dc9e499c RJ |
1 | Overview |
2 | ======== | |
3 | ||
4 | The overall usage pattern for ECC diagnostic commands is the following: | |
5 | ||
6 | * (injecting errors is initially disabled) | |
7 | ||
8 | * define inject mask (which tells the DDR controller what type of errors | |
9 | we'll be injecting: single/multiple bit etc.) | |
10 | ||
11 | * enable injecting errors - from now on the controller injects errors as | |
12 | indicated in the inject mask | |
13 | ||
14 | IMPORTANT NOTICE: enabling injecting multiple-bit errors is potentially | |
15 | dangerous as such errors are NOT corrected by the controller. Therefore caution | |
16 | should be taken when enabling the injection of multiple-bit errors: it is only | |
17 | safe when used on a carefully selected memory area and used under control of | |
47e8bc84 DL |
18 | the 'ecc testdw' 'ecc testword' command (see example 'Injecting Multiple-Bit |
19 | Errors' below). In particular, when you simply set the multiple-bit errors in | |
20 | inject mask and enable injection, U-Boot is very likely to hang quickly as the | |
21 | errors will be injected when it accesses its code, data etc. | |
d326f4a2 MB |
22 | |
23 | ||
24 | Use cases for DDR 'ecc' command: | |
25 | ================================ | |
26 | ||
27 | Before executing particular tests reset target board or clear status registers: | |
28 | ||
29 | => ecc captureclear | |
30 | => ecc errdetectclr all | |
31 | => ecc sbecnt 0 | |
32 | ||
33 | ||
34 | Injecting Single-Bit Errors | |
35 | --------------------------- | |
36 | ||
37 | 1. Set 1 bit in Data Path Error Inject Mask | |
38 | ||
39 | => ecc injectdatahi 1 | |
40 | ||
41 | 2. Run test over some memory region | |
42 | ||
47e8bc84 | 43 | => ecc testdw 200000 10 |
d326f4a2 MB |
44 | |
45 | 3. Check ECC status | |
46 | ||
47 | => ecc status | |
48 | ... | |
49 | Memory Data Path Error Injection Mask High/Low: 00000001 00000000 | |
50 | ... | |
51 | Memory Single-Bit Error Management (0..255): | |
52 | Single-Bit Error Threshold: 255 | |
53 | Single Bit Error Counter: 16 | |
54 | ... | |
55 | Memory Error Detect: | |
56 | Multiple Memory Errors: 0 | |
57 | Multiple-Bit Error: 0 | |
58 | Single-Bit Error: 0 | |
59 | ... | |
60 | ||
61 | 16 errors were generated, Single-Bit Error flag was not set as Single Bit Error | |
62 | Counter did not reach Single-Bit Error Threshold. | |
63 | ||
47e8bc84 | 64 | 4. Make sure used memory region got re-initialized with 0x0123456789abcdef |
d326f4a2 MB |
65 | |
66 | => md 200000 | |
47e8bc84 DL |
67 | 00200000: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... |
68 | 00200010: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... | |
69 | 00200020: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... | |
70 | 00200030: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... | |
71 | 00200040: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... | |
72 | 00200050: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... | |
73 | 00200060: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... | |
74 | 00200070: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... | |
d326f4a2 MB |
75 | 00200080: deadbeef deadbeef deadbeef deadbeef ................ |
76 | 00200090: deadbeef deadbeef deadbeef deadbeef ................ | |
77 | ||
d326f4a2 MB |
78 | Injecting Multiple-Bit Errors |
79 | ----------------------------- | |
80 | ||
81 | 1. Set more than 1 bit in Data Path Error Inject Mask | |
82 | ||
47e8bc84 DL |
83 | => ecc injectdatahi 1 |
84 | => ecc injectdatalo 1 | |
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85 | |
86 | 2. Run test over some memory region | |
87 | ||
47e8bc84 | 88 | => ecc testword 200000 1 |
d326f4a2 MB |
89 | |
90 | 3. Check ECC status | |
91 | ||
92 | => ecc status | |
93 | ... | |
47e8bc84 | 94 | Memory Data Path Error Injection Mask High/Low: 00000001 00000001 |
d326f4a2 MB |
95 | ... |
96 | Memory Error Detect: | |
47e8bc84 | 97 | Multiple Memory Errors: 0 |
d326f4a2 MB |
98 | Multiple-Bit Error: 1 |
99 | Single-Bit Error: 0 | |
100 | ... | |
101 | ||
47e8bc84 | 102 | The Multiple Memory Errors flags not set and Multiple-Bit Error flags are set. |
d326f4a2 | 103 | |
47e8bc84 | 104 | 4. Make sure used memory region got re-initialized with 0x0123456789abcdef |
d326f4a2 MB |
105 | |
106 | => md 200000 | |
47e8bc84 DL |
107 | 00200000: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... |
108 | 00200010: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... | |
109 | 00200020: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... | |
110 | 00200030: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... | |
111 | 00200040: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... | |
112 | 00200050: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... | |
113 | 00200060: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... | |
114 | 00200070: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... | |
d326f4a2 MB |
115 | 00200080: deadbeef deadbeef deadbeef deadbeef ................ |
116 | 00200090: deadbeef deadbeef deadbeef deadbeef ................ | |
117 | ||
118 | ||
119 | Test Single-Bit Error Counter and Threshold | |
120 | ------------------------------------------- | |
121 | ||
122 | 1. Set 1 bit in Data Path Error Inject Mask | |
123 | ||
124 | => ecc injectdatahi 1 | |
125 | ||
126 | 2. Enable error injection | |
127 | ||
128 | => ecc inject en | |
129 | ||
130 | 3. Let u-boot run for a with Single-Bit error injection enabled | |
131 | ||
132 | 4. Disable error injection | |
133 | ||
134 | => ecc inject dis | |
135 | ||
136 | 4. Check status | |
137 | ||
138 | => ecc status | |
139 | ||
140 | ... | |
141 | Memory Single-Bit Error Management (0..255): | |
142 | Single-Bit Error Threshold: 255 | |
47e8bc84 | 143 | Single Bit Error Counter: 199 |
d326f4a2 MB |
144 | |
145 | Memory Error Detect: | |
146 | Multiple Memory Errors: 1 | |
147 | Multiple-Bit Error: 0 | |
148 | Single-Bit Error: 1 | |
149 | ... | |
150 | ||
151 | Observe that Single-Bit Error is 'on' which means that Single-Bit Error Counter | |
152 | reached Single-Bit Error Threshold. Multiple Memory Errors bit is also 'on', that | |
153 | is Counter reached Threshold more than one time (it wraps back after reaching | |
154 | Threshold). |