[J-u-boot.git] / drivers / spi / zynq_qspi.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2013 Xilinx, Inc.
 * (C) Copyright 2015 Jagan Teki <[email protected]>
 *
 * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
 */

#include <clk.h>
#include <common.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <log.h>
#include <malloc.h>
#include <spi.h>
#include <asm/io.h>
#include <linux/bitops.h>

DECLARE_GLOBAL_DATA_PTR;

/* zynq qspi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
#define ZYNQ_QSPI_CR_IFMODE_MASK	BIT(31)	/* Flash intrface mode*/
#define ZYNQ_QSPI_CR_MSA_MASK		BIT(15)	/* Manual start enb */
#define ZYNQ_QSPI_CR_MCS_MASK		BIT(14)	/* Manual chip select */
#define ZYNQ_QSPI_CR_PCS_MASK		BIT(10)	/* Peri chip select */
#define ZYNQ_QSPI_CR_FW_MASK		GENMASK(7, 6)	/* FIFO width */
#define ZYNQ_QSPI_CR_SS_MASK		GENMASK(13, 10)	/* Slave Select */
#define ZYNQ_QSPI_CR_BAUD_MASK		GENMASK(5, 3)	/* Baud rate div */
#define ZYNQ_QSPI_CR_CPHA_MASK		BIT(2)	/* Clock phase */
#define ZYNQ_QSPI_CR_CPOL_MASK		BIT(1)	/* Clock polarity */
#define ZYNQ_QSPI_CR_MSTREN_MASK	BIT(0)	/* Mode select */
#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK	BIT(4)	/* RX_FIFO_not_empty */
#define ZYNQ_QSPI_IXR_TXOW_MASK		BIT(2)	/* TX_FIFO_not_full */
#define ZYNQ_QSPI_IXR_ALL_MASK		GENMASK(6, 0)	/* All IXR bits */
#define ZYNQ_QSPI_ENR_SPI_EN_MASK	BIT(0)	/* SPI Enable */
#define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK	BIT(31) /* Linear QSPI Mode */

/* zynq qspi Transmit Data Register */
#define ZYNQ_QSPI_TXD_00_00_OFFSET	0x1C	/* Transmit 4-byte inst */
#define ZYNQ_QSPI_TXD_00_01_OFFSET	0x80	/* Transmit 1-byte inst */
#define ZYNQ_QSPI_TXD_00_10_OFFSET	0x84	/* Transmit 2-byte inst */
#define ZYNQ_QSPI_TXD_00_11_OFFSET	0x88	/* Transmit 3-byte inst */

#define ZYNQ_QSPI_TXFIFO_THRESHOLD	1	/* Tx FIFO threshold level*/
#define ZYNQ_QSPI_RXFIFO_THRESHOLD	32	/* Rx FIFO threshold level */

#define ZYNQ_QSPI_CR_BAUD_MAX		8	/* Baud rate divisor max val */
#define ZYNQ_QSPI_CR_BAUD_SHIFT		3	/* Baud rate divisor shift */
#define ZYNQ_QSPI_CR_SS_SHIFT		10	/* Slave select shift */

#define ZYNQ_QSPI_FIFO_DEPTH		63
#define ZYNQ_QSPI_WAIT			(CONFIG_SYS_HZ / 100)	/* 10 ms */

/* zynq qspi register set */
struct zynq_qspi_regs {
	u32 cr;		/* 0x00 */
	u32 isr;	/* 0x04 */
	u32 ier;	/* 0x08 */
	u32 idr;	/* 0x0C */
	u32 imr;	/* 0x10 */
	u32 enr;	/* 0x14 */
	u32 dr;		/* 0x18 */
	u32 txd0r;	/* 0x1C */
	u32 drxr;	/* 0x20 */
	u32 sicr;	/* 0x24 */
	u32 txftr;	/* 0x28 */
	u32 rxftr;	/* 0x2C */
	u32 gpior;	/* 0x30 */
	u32 reserved0[19];
	u32 txd1r;	/* 0x80 */
	u32 txd2r;	/* 0x84 */
	u32 txd3r;	/* 0x88 */
	u32 reserved1[5];
	u32 lqspicfg;	/* 0xA0 */
	u32 lqspists;	/* 0xA4 */
};

/* zynq qspi platform data */
struct zynq_qspi_platdata {
	struct zynq_qspi_regs *regs;
	u32 frequency;          /* input frequency */
	u32 speed_hz;
};

/* zynq qspi priv */
struct zynq_qspi_priv {
	struct zynq_qspi_regs *regs;
	u8 cs;
	u8 mode;
	u8 fifo_depth;
	u32 freq;		/* required frequency */
	const void *tx_buf;
	void *rx_buf;
	unsigned len;
	int bytes_to_transfer;
	int bytes_to_receive;
	unsigned int is_inst;
	unsigned cs_change:1;
};

static int zynq_qspi_of_to_plat(struct udevice *bus)
{
	struct zynq_qspi_platdata *plat = bus->plat;
	const void *blob = gd->fdt_blob;
	int node = dev_of_offset(bus);

	plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
							      node, "reg");

	return 0;
}

/**
 * zynq_qspi_init_hw - Initialize the hardware
 * @priv:	Pointer to the zynq_qspi_priv structure
 *
 * The default settings of the QSPI controller's configurable parameters on
 * reset are
 *	- Master mode
 *	- Baud rate divisor is set to 2
 *	- Threshold value for TX FIFO not full interrupt is set to 1
 *	- Flash memory interface mode enabled
 *	- Size of the word to be transferred as 8 bit
 * This function performs the following actions
 *	- Disable and clear all the interrupts
 *	- Enable manual slave select
 *	- Enable auto start
 *	- Deselect all the chip select lines
 *	- Set the size of the word to be transferred as 32 bit
 *	- Set the little endian mode of TX FIFO and
 *	- Enable the QSPI controller
 */
static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
{
	struct zynq_qspi_regs *regs = priv->regs;
	u32 confr;

	/* Disable QSPI */
	writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);

	/* Disable Interrupts */
	writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->idr);

	/* Clear the TX and RX threshold reg */
	writel(ZYNQ_QSPI_TXFIFO_THRESHOLD, &regs->txftr);
	writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, &regs->rxftr);

	/* Clear the RX FIFO */
	while (readl(&regs->isr) & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)
		readl(&regs->drxr);

	/* Clear Interrupts */
	writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->isr);

	/* Manual slave select and Auto start */
	confr = readl(&regs->cr);
	confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
	confr |= ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK |
		ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK |
		ZYNQ_QSPI_CR_MSTREN_MASK;
	writel(confr, &regs->cr);

	/* Disable the LQSPI feature */
	confr = readl(&regs->lqspicfg);
	confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK;
	writel(confr, &regs->lqspicfg);

	/* Enable SPI */
	writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
}

static int zynq_qspi_probe(struct udevice *bus)
{
	struct zynq_qspi_platdata *plat = dev_get_plat(bus);
	struct zynq_qspi_priv *priv = dev_get_priv(bus);
	struct clk clk;
	unsigned long clock;
	int ret;

	priv->regs = plat->regs;
	priv->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH;

	ret = clk_get_by_name(bus, "ref_clk", &clk);
	if (ret < 0) {
		dev_err(bus, "failed to get clock\n");
		return ret;
	}

	clock = clk_get_rate(&clk);
	if (IS_ERR_VALUE(clock)) {
		dev_err(bus, "failed to get rate\n");
		return clock;
	}

	ret = clk_enable(&clk);
	if (ret && ret != -ENOSYS) {
		dev_err(bus, "failed to enable clock\n");
		return ret;
	}

	/* init the zynq spi hw */
	zynq_qspi_init_hw(priv);

	plat->frequency = clock;
	plat->speed_hz = plat->frequency / 2;

	debug("%s: max-frequency=%d\n", __func__, plat->speed_hz);

	return 0;
}

/**
 * zynq_qspi_read_data - Copy data to RX buffer
 * @priv:	Pointer to the zynq_qspi_priv structure
 * @data:	The 32 bit variable where data is stored
 * @size:	Number of bytes to be copied from data to RX buffer
 */
static void zynq_qspi_read_data(struct zynq_qspi_priv *priv, u32 data, u8 size)
{
	u8 byte3;

	debug("%s: data 0x%04x rx_buf addr: 0x%08x size %d\n", __func__ ,
	      data, (unsigned)(priv->rx_buf), size);

	if (priv->rx_buf) {
		switch (size) {
		case 1:
			*((u8 *)priv->rx_buf) = data;
			priv->rx_buf += 1;
			break;
		case 2:
			*((u16 *)priv->rx_buf) = data;
			priv->rx_buf += 2;
			break;
		case 3:
			*((u16 *)priv->rx_buf) = data;
			priv->rx_buf += 2;
			byte3 = (u8)(data >> 16);
			*((u8 *)priv->rx_buf) = byte3;
			priv->rx_buf += 1;
			break;
		case 4:
			/* Can not assume word aligned buffer */
			memcpy(priv->rx_buf, &data, size);
			priv->rx_buf += 4;
			break;
		default:
			/* This will never execute */
			break;
		}
	}
	priv->bytes_to_receive -= size;
	if (priv->bytes_to_receive < 0)
		priv->bytes_to_receive = 0;
}

/**
 * zynq_qspi_write_data - Copy data from TX buffer
 * @priv:	Pointer to the zynq_qspi_priv structure
 * @data:	Pointer to the 32 bit variable where data is to be copied
 * @size:	Number of bytes to be copied from TX buffer to data
 */
static void zynq_qspi_write_data(struct  zynq_qspi_priv *priv,
		u32 *data, u8 size)
{
	if (priv->tx_buf) {
		switch (size) {
		case 1:
			*data = *((u8 *)priv->tx_buf);
			priv->tx_buf += 1;
			*data |= 0xFFFFFF00;
			break;
		case 2:
			*data = *((u16 *)priv->tx_buf);
			priv->tx_buf += 2;
			*data |= 0xFFFF0000;
			break;
		case 3:
			*data = *((u16 *)priv->tx_buf);
			priv->tx_buf += 2;
			*data |= (*((u8 *)priv->tx_buf) << 16);
			priv->tx_buf += 1;
			*data |= 0xFF000000;
			break;
		case 4:
			/* Can not assume word aligned buffer */
			memcpy(data, priv->tx_buf, size);
			priv->tx_buf += 4;
			break;
		default:
			/* This will never execute */
			break;
		}
	} else {
		*data = 0;
	}

	debug("%s: data 0x%08x tx_buf addr: 0x%08x size %d\n", __func__,
	      *data, (u32)priv->tx_buf, size);

	priv->bytes_to_transfer -= size;
	if (priv->bytes_to_transfer < 0)
		priv->bytes_to_transfer = 0;
}

/**
 * zynq_qspi_chipselect - Select or deselect the chip select line
 * @priv:	Pointer to the zynq_qspi_priv structure
 * @is_on:	Select(1) or deselect (0) the chip select line
 */
static void zynq_qspi_chipselect(struct  zynq_qspi_priv *priv, int is_on)
{
	u32 confr;
	struct zynq_qspi_regs *regs = priv->regs;

	confr = readl(&regs->cr);

	if (is_on) {
		/* Select the slave */
		confr &= ~ZYNQ_QSPI_CR_SS_MASK;
		confr |= (~(1 << priv->cs) << ZYNQ_QSPI_CR_SS_SHIFT) &
					ZYNQ_QSPI_CR_SS_MASK;
	} else
		/* Deselect the slave */
		confr |= ZYNQ_QSPI_CR_SS_MASK;

	writel(confr, &regs->cr);
}

/**
 * zynq_qspi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
 * @priv:	Pointer to the zynq_qspi_priv structure
 * @size:	Number of bytes to be copied to fifo
 */
static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv *priv, u32 size)
{
	u32 data = 0;
	u32 fifocount = 0;
	unsigned len, offset;
	struct zynq_qspi_regs *regs = priv->regs;
	static const unsigned offsets[4] = {
		ZYNQ_QSPI_TXD_00_00_OFFSET, ZYNQ_QSPI_TXD_00_01_OFFSET,
		ZYNQ_QSPI_TXD_00_10_OFFSET, ZYNQ_QSPI_TXD_00_11_OFFSET };

	while ((fifocount < size) &&
			(priv->bytes_to_transfer > 0)) {
		if (priv->bytes_to_transfer >= 4) {
			if (priv->tx_buf) {
				memcpy(&data, priv->tx_buf, 4);
				priv->tx_buf += 4;
			} else {
				data = 0;
			}
			writel(data, &regs->txd0r);
			priv->bytes_to_transfer -= 4;
			fifocount++;
		} else {
			/* Write TXD1, TXD2, TXD3 only if TxFIFO is empty. */
			if (!(readl(&regs->isr)
					& ZYNQ_QSPI_IXR_TXOW_MASK) &&
					!priv->rx_buf)
				return;
			len = priv->bytes_to_transfer;
			zynq_qspi_write_data(priv, &data, len);
			offset = (priv->rx_buf) ? offsets[0] : offsets[len];
			writel(data, &regs->cr + (offset / 4));
		}
	}
}

/**
 * zynq_qspi_irq_poll - Interrupt service routine of the QSPI controller
 * @priv:	Pointer to the zynq_qspi structure
 *
 * This function handles TX empty and Mode Fault interrupts only.
 * On TX empty interrupt this function reads the received data from RX FIFO and
 * fills the TX FIFO if there is any data remaining to be transferred.
 * On Mode Fault interrupt this function indicates that transfer is completed,
 * the SPI subsystem will identify the error as the remaining bytes to be
 * transferred is non-zero.
 *
 * returns:	0 for poll timeout
 *		1 transfer operation complete
 */
static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv)
{
	struct zynq_qspi_regs *regs = priv->regs;
	u32 rxindex = 0;
	u32 rxcount;
	u32 status, timeout;

	/* Poll until any of the interrupt status bits are set */
	timeout = get_timer(0);
	do {
		status = readl(&regs->isr);
	} while ((status == 0) &&
		(get_timer(timeout) < ZYNQ_QSPI_WAIT));

	if (status == 0) {
		printf("zynq_qspi_irq_poll: Timeout!\n");
		return -ETIMEDOUT;
	}

	writel(status, &regs->isr);

	/* Disable all interrupts */
	writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->idr);
	if ((status & ZYNQ_QSPI_IXR_TXOW_MASK) ||
	    (status & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)) {
		/*
		 * This bit is set when Tx FIFO has < THRESHOLD entries. We have
		 * the THRESHOLD value set to 1, so this bit indicates Tx FIFO
		 * is empty
		 */
		rxcount = priv->bytes_to_receive - priv->bytes_to_transfer;
		rxcount = (rxcount % 4) ? ((rxcount/4)+1) : (rxcount/4);
		while ((rxindex < rxcount) &&
				(rxindex < ZYNQ_QSPI_RXFIFO_THRESHOLD)) {
			/* Read out the data from the RX FIFO */
			u32 data;
			data = readl(&regs->drxr);

			if (priv->bytes_to_receive >= 4) {
				if (priv->rx_buf) {
					memcpy(priv->rx_buf, &data, 4);
					priv->rx_buf += 4;
				}
				priv->bytes_to_receive -= 4;
			} else {
				zynq_qspi_read_data(priv, data,
						    priv->bytes_to_receive);
			}
			rxindex++;
		}

		if (priv->bytes_to_transfer) {
			/* There is more data to send */
			zynq_qspi_fill_tx_fifo(priv,
					       ZYNQ_QSPI_RXFIFO_THRESHOLD);

			writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->ier);
		} else {
			/*
			 * If transfer and receive is completed then only send
			 * complete signal
			 */
			if (!priv->bytes_to_receive) {
				/* return operation complete */
				writel(ZYNQ_QSPI_IXR_ALL_MASK,
				       &regs->idr);
				return 1;
			}
		}
	}

	return 0;
}

/**
 * zynq_qspi_start_transfer - Initiates the QSPI transfer
 * @priv:	Pointer to the zynq_qspi_priv structure
 *
 * This function fills the TX FIFO, starts the QSPI transfer, and waits for the
 * transfer to be completed.
 *
 * returns:	Number of bytes transferred in the last transfer
 */
static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv)
{
	u32 data = 0;
	struct zynq_qspi_regs *regs = priv->regs;

	debug("%s: qspi: 0x%08x transfer: 0x%08x len: %d\n", __func__,
	      (u32)priv, (u32)priv, priv->len);

	priv->bytes_to_transfer = priv->len;
	priv->bytes_to_receive = priv->len;

	if (priv->len < 4)
		zynq_qspi_fill_tx_fifo(priv, priv->len);
	else
		zynq_qspi_fill_tx_fifo(priv, priv->fifo_depth);

	writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->ier);

	/* wait for completion */
	do {
		data = zynq_qspi_irq_poll(priv);
	} while (data == 0);

	return (priv->len) - (priv->bytes_to_transfer);
}

static int zynq_qspi_transfer(struct zynq_qspi_priv *priv)
{
	unsigned cs_change = 1;
	int status = 0;

	while (1) {
		/* Select the chip if required */
		if (cs_change)
			zynq_qspi_chipselect(priv, 1);

		cs_change = priv->cs_change;

		if (!priv->tx_buf && !priv->rx_buf && priv->len) {
			status = -1;
			break;
		}

		/* Request the transfer */
		if (priv->len) {
			status = zynq_qspi_start_transfer(priv);
			priv->is_inst = 0;
		}

		if (status != priv->len) {
			if (status > 0)
				status = -EMSGSIZE;
			debug("zynq_qspi_transfer:%d len:%d\n",
			      status, priv->len);
			break;
		}
		status = 0;

		if (cs_change)
			/* Deselect the chip */
			zynq_qspi_chipselect(priv, 0);

		break;
	}

	return status;
}

static int zynq_qspi_claim_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct zynq_qspi_priv *priv = dev_get_priv(bus);
	struct zynq_qspi_regs *regs = priv->regs;

	writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);

	return 0;
}

static int zynq_qspi_release_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct zynq_qspi_priv *priv = dev_get_priv(bus);
	struct zynq_qspi_regs *regs = priv->regs;

	writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);

	return 0;
}

static int zynq_qspi_xfer(struct udevice *dev, unsigned int bitlen,
		const void *dout, void *din, unsigned long flags)
{
	struct udevice *bus = dev->parent;
	struct zynq_qspi_priv *priv = dev_get_priv(bus);
	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);

	priv->cs = slave_plat->cs;
	priv->tx_buf = dout;
	priv->rx_buf = din;
	priv->len = bitlen / 8;

	debug("zynq_qspi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
	      bus->seq, slave_plat->cs, bitlen, priv->len, flags);

	/*
	 * Festering sore.
	 * Assume that the beginning of a transfer with bits to
	 * transmit must contain a device command.
	 */
	if (dout && flags & SPI_XFER_BEGIN)
		priv->is_inst = 1;
	else
		priv->is_inst = 0;

	if (flags & SPI_XFER_END)
		priv->cs_change = 1;
	else
		priv->cs_change = 0;

	zynq_qspi_transfer(priv);

	return 0;
}

static int zynq_qspi_set_speed(struct udevice *bus, uint speed)
{
	struct zynq_qspi_platdata *plat = bus->plat;
	struct zynq_qspi_priv *priv = dev_get_priv(bus);
	struct zynq_qspi_regs *regs = priv->regs;
	uint32_t confr;
	u8 baud_rate_val = 0;

	if (speed > plat->frequency)
		speed = plat->frequency;

	/* Set the clock frequency */
	confr = readl(&regs->cr);
	if (speed == 0) {
		/* Set baudrate x8, if the freq is 0 */
		baud_rate_val = 0x2;
	} else if (plat->speed_hz != speed) {
		while ((baud_rate_val < ZYNQ_QSPI_CR_BAUD_MAX) &&
		       ((plat->frequency /
		       (2 << baud_rate_val)) > speed))
			baud_rate_val++;

		plat->speed_hz = speed / (2 << baud_rate_val);
	}
	confr &= ~ZYNQ_QSPI_CR_BAUD_MASK;
	confr |= (baud_rate_val << ZYNQ_QSPI_CR_BAUD_SHIFT);

	writel(confr, &regs->cr);
	priv->freq = speed;

	debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);

	return 0;
}

static int zynq_qspi_set_mode(struct udevice *bus, uint mode)
{
	struct zynq_qspi_priv *priv = dev_get_priv(bus);
	struct zynq_qspi_regs *regs = priv->regs;
	uint32_t confr;

	/* Set the SPI Clock phase and polarities */
	confr = readl(&regs->cr);
	confr &= ~(ZYNQ_QSPI_CR_CPHA_MASK | ZYNQ_QSPI_CR_CPOL_MASK);

	if (mode & SPI_CPHA)
		confr |= ZYNQ_QSPI_CR_CPHA_MASK;
	if (mode & SPI_CPOL)
		confr |= ZYNQ_QSPI_CR_CPOL_MASK;

	writel(confr, &regs->cr);
	priv->mode = mode;

	debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);

	return 0;
}

static const struct dm_spi_ops zynq_qspi_ops = {
	.claim_bus      = zynq_qspi_claim_bus,
	.release_bus    = zynq_qspi_release_bus,
	.xfer           = zynq_qspi_xfer,
	.set_speed      = zynq_qspi_set_speed,
	.set_mode       = zynq_qspi_set_mode,
};

static const struct udevice_id zynq_qspi_ids[] = {
	{ .compatible = "xlnx,zynq-qspi-1.0" },
	{ }
};

U_BOOT_DRIVER(zynq_qspi) = {
	.name   = "zynq_qspi",
	.id     = UCLASS_SPI,
	.of_match = zynq_qspi_ids,
	.ops    = &zynq_qspi_ops,
	.of_to_plat = zynq_qspi_of_to_plat,
	.plat_auto	= sizeof(struct zynq_qspi_platdata),
	.priv_auto	= sizeof(struct zynq_qspi_priv),
	.probe  = zynq_qspi_probe,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
46d0a991 JT	2	/*
	3	* (C) Copyright 2013 Xilinx, Inc.
	4	* (C) Copyright 2015 Jagan Teki <[email protected]>
	5	*
	6	* Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
46d0a991 JT	7	*/
46d0a991 JT	8
ea836be1	9	#include <clk.h>
46d0a991 JT	10	#include <common.h>
46d0a991 JT	11	#include <dm.h>
ea836be1	12	#include <dm/device_compat.h>
f7ae49fc	13	#include <log.h>
46d0a991 JT	14	#include <malloc.h>
	15	#include <spi.h>
	16	#include <asm/io.h>
cd93d625	17	#include <linux/bitops.h>
46d0a991 JT	18
	19	DECLARE_GLOBAL_DATA_PTR;
	20
	21	/* zynq qspi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
736b4df1 JT	22	#define ZYNQ_QSPI_CR_IFMODE_MASK BIT(31) /* Flash intrface mode*/
	23	#define ZYNQ_QSPI_CR_MSA_MASK BIT(15) /* Manual start enb */
	24	#define ZYNQ_QSPI_CR_MCS_MASK BIT(14) /* Manual chip select */
	25	#define ZYNQ_QSPI_CR_PCS_MASK BIT(10) /* Peri chip select */
9cf2ffb3 JT	26	#define ZYNQ_QSPI_CR_FW_MASK GENMASK(7, 6) /* FIFO width */
	27	#define ZYNQ_QSPI_CR_SS_MASK GENMASK(13, 10) /* Slave Select */
	28	#define ZYNQ_QSPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
736b4df1 JT	29	#define ZYNQ_QSPI_CR_CPHA_MASK BIT(2) /* Clock phase */
	30	#define ZYNQ_QSPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
	31	#define ZYNQ_QSPI_CR_MSTREN_MASK BIT(0) /* Mode select */
	32	#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
	33	#define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
9cf2ffb3	34	#define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
736b4df1	35	#define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
04a44d36	36	#define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK BIT(31) /* Linear QSPI Mode */
46d0a991 JT	37
	38	/* zynq qspi Transmit Data Register */
	39	#define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */
	40	#define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst */
	41	#define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst */
	42	#define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst */
	43
	44	#define ZYNQ_QSPI_TXFIFO_THRESHOLD 1 /* Tx FIFO threshold level*/
	45	#define ZYNQ_QSPI_RXFIFO_THRESHOLD 32 /* Rx FIFO threshold level */
	46
	47	#define ZYNQ_QSPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
	48	#define ZYNQ_QSPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
	49	#define ZYNQ_QSPI_CR_SS_SHIFT 10 /* Slave select shift */
	50
	51	#define ZYNQ_QSPI_FIFO_DEPTH 63
f44bd3bc	52	#define ZYNQ_QSPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */
46d0a991 JT	53
	54	/* zynq qspi register set */
	55	struct zynq_qspi_regs {
	56	u32 cr; /* 0x00 */
	57	u32 isr; /* 0x04 */
	58	u32 ier; /* 0x08 */
	59	u32 idr; /* 0x0C */
	60	u32 imr; /* 0x10 */
	61	u32 enr; /* 0x14 */
	62	u32 dr; /* 0x18 */
	63	u32 txd0r; /* 0x1C */
	64	u32 drxr; /* 0x20 */
	65	u32 sicr; /* 0x24 */
	66	u32 txftr; /* 0x28 */
	67	u32 rxftr; /* 0x2C */
	68	u32 gpior; /* 0x30 */
	69	u32 reserved0[19];
	70	u32 txd1r; /* 0x80 */
	71	u32 txd2r; /* 0x84 */
	72	u32 txd3r; /* 0x88 */
04a44d36 NR	73	u32 reserved1[5];
	74	u32 lqspicfg; /* 0xA0 */
	75	u32 lqspists; /* 0xA4 */
46d0a991 JT	76	};
	77
	78	/* zynq qspi platform data */
	79	struct zynq_qspi_platdata {
	80	struct zynq_qspi_regs *regs;
	81	u32 frequency; /* input frequency */
	82	u32 speed_hz;
	83	};
	84
	85	/* zynq qspi priv */
	86	struct zynq_qspi_priv {
	87	struct zynq_qspi_regs *regs;
	88	u8 cs;
	89	u8 mode;
	90	u8 fifo_depth;
	91	u32 freq; /* required frequency */
	92	const void *tx_buf;
	93	void *rx_buf;
	94	unsigned len;
	95	int bytes_to_transfer;
	96	int bytes_to_receive;
	97	unsigned int is_inst;
	98	unsigned cs_change:1;
	99	};
	100
d1998a9f	101	static int zynq_qspi_of_to_plat(struct udevice *bus)
46d0a991	102	{
caa4daa2	103	struct zynq_qspi_platdata *plat = bus->plat;
46d0a991	104	const void *blob = gd->fdt_blob;
e160f7d4	105	int node = dev_of_offset(bus);
46d0a991 JT	106
	107	plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
	108	node, "reg");
	109
46d0a991 JT	110	return 0;
	111	}
	112
17fbb598 ARS	113	/**
	114	* zynq_qspi_init_hw - Initialize the hardware
	115	* @priv: Pointer to the zynq_qspi_priv structure
	116	*
	117	* The default settings of the QSPI controller's configurable parameters on
	118	* reset are
	119	* - Master mode
	120	* - Baud rate divisor is set to 2
	121	* - Threshold value for TX FIFO not full interrupt is set to 1
	122	* - Flash memory interface mode enabled
	123	* - Size of the word to be transferred as 8 bit
	124	* This function performs the following actions
	125	* - Disable and clear all the interrupts
	126	* - Enable manual slave select
	127	* - Enable auto start
	128	* - Deselect all the chip select lines
	129	* - Set the size of the word to be transferred as 32 bit
	130	* - Set the little endian mode of TX FIFO and
	131	* - Enable the QSPI controller
	132	*/
46d0a991 JT	133	static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
	134	{
	135	struct zynq_qspi_regs *regs = priv->regs;
	136	u32 confr;
	137
	138	/* Disable QSPI */
	139	writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
	140
	141	/* Disable Interrupts */
	142	writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->idr);
	143
	144	/* Clear the TX and RX threshold reg */
	145	writel(ZYNQ_QSPI_TXFIFO_THRESHOLD, &regs->txftr);
	146	writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, &regs->rxftr);
	147
	148	/* Clear the RX FIFO */
	149	while (readl(&regs->isr) & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)
	150	readl(&regs->drxr);
	151
	152	/* Clear Interrupts */
	153	writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->isr);
	154
	155	/* Manual slave select and Auto start */
	156	confr = readl(&regs->cr);
	157	confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
	158	confr \|= ZYNQ_QSPI_CR_IFMODE_MASK \| ZYNQ_QSPI_CR_MCS_MASK \|
	159	ZYNQ_QSPI_CR_PCS_MASK \| ZYNQ_QSPI_CR_FW_MASK \|
	160	ZYNQ_QSPI_CR_MSTREN_MASK;
	161	writel(confr, &regs->cr);
	162
04a44d36 NR	163	/* Disable the LQSPI feature */
	164	confr = readl(&regs->lqspicfg);
	165	confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK;
	166	writel(confr, &regs->lqspicfg);
	167
46d0a991 JT	168	/* Enable SPI */
	169	writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
	170	}
	171
	172	static int zynq_qspi_probe(struct udevice *bus)
	173	{
c69cda25	174	struct zynq_qspi_platdata *plat = dev_get_plat(bus);
46d0a991	175	struct zynq_qspi_priv *priv = dev_get_priv(bus);
ea836be1 KR	176	struct clk clk;
	177	unsigned long clock;
	178	int ret;
46d0a991 JT	179
	180	priv->regs = plat->regs;
	181	priv->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH;
	182
ea836be1 KR	183	ret = clk_get_by_name(bus, "ref_clk", &clk);
	184	if (ret < 0) {
	185	dev_err(bus, "failed to get clock\n");
	186	return ret;
	187	}
	188
	189	clock = clk_get_rate(&clk);
	190	if (IS_ERR_VALUE(clock)) {
	191	dev_err(bus, "failed to get rate\n");
	192	return clock;
	193	}
	194
	195	ret = clk_enable(&clk);
	196	if (ret && ret != -ENOSYS) {
	197	dev_err(bus, "failed to enable clock\n");
	198	return ret;
	199	}
	200
46d0a991 JT	201	/* init the zynq spi hw */
	202	zynq_qspi_init_hw(priv);
	203
ea836be1 KR	204	plat->frequency = clock;
	205	plat->speed_hz = plat->frequency / 2;
	206
	207	debug("%s: max-frequency=%d\n", __func__, plat->speed_hz);
	208
46d0a991 JT	209	return 0;
	210	}
	211
17fbb598	212	/**
46d0a991	213	* zynq_qspi_read_data - Copy data to RX buffer
17fbb598	214	* @priv: Pointer to the zynq_qspi_priv structure
46d0a991 JT	215	* @data: The 32 bit variable where data is stored
	216	* @size: Number of bytes to be copied from data to RX buffer
	217	*/
	218	static void zynq_qspi_read_data(struct zynq_qspi_priv *priv, u32 data, u8 size)
	219	{
	220	u8 byte3;
	221
	222	debug("%s: data 0x%04x rx_buf addr: 0x%08x size %d\n", __func__ ,
	223	data, (unsigned)(priv->rx_buf), size);
	224
	225	if (priv->rx_buf) {
	226	switch (size) {
	227	case 1:
	228	((u8 )priv->rx_buf) = data;
	229	priv->rx_buf += 1;
	230	break;
	231	case 2:
	232	((u16 )priv->rx_buf) = data;
	233	priv->rx_buf += 2;
	234	break;
	235	case 3:
	236	((u16 )priv->rx_buf) = data;
	237	priv->rx_buf += 2;
	238	byte3 = (u8)(data >> 16);
	239	((u8 )priv->rx_buf) = byte3;
	240	priv->rx_buf += 1;
	241	break;
	242	case 4:
	243	/* Can not assume word aligned buffer */
	244	memcpy(priv->rx_buf, &data, size);
	245	priv->rx_buf += 4;
	246	break;
	247	default:
	248	/* This will never execute */
	249	break;
	250	}
	251	}
	252	priv->bytes_to_receive -= size;
	253	if (priv->bytes_to_receive < 0)
	254	priv->bytes_to_receive = 0;
	255	}
	256
17fbb598	257	/**
46d0a991	258	* zynq_qspi_write_data - Copy data from TX buffer
17fbb598	259	* @priv: Pointer to the zynq_qspi_priv structure
46d0a991 JT	260	* @data: Pointer to the 32 bit variable where data is to be copied
	261	* @size: Number of bytes to be copied from TX buffer to data
	262	*/
	263	static void zynq_qspi_write_data(struct zynq_qspi_priv *priv,
	264	u32 *data, u8 size)
	265	{
	266	if (priv->tx_buf) {
	267	switch (size) {
	268	case 1:
	269	data = ((u8 *)priv->tx_buf);
	270	priv->tx_buf += 1;
	271	*data \|= 0xFFFFFF00;
	272	break;
	273	case 2:
	274	data = ((u16 *)priv->tx_buf);
	275	priv->tx_buf += 2;
	276	*data \|= 0xFFFF0000;
	277	break;
	278	case 3:
	279	data = ((u16 *)priv->tx_buf);
	280	priv->tx_buf += 2;
	281	data \|= (((u8 *)priv->tx_buf) << 16);
	282	priv->tx_buf += 1;
	283	*data \|= 0xFF000000;
	284	break;
	285	case 4:
	286	/* Can not assume word aligned buffer */
	287	memcpy(data, priv->tx_buf, size);
	288	priv->tx_buf += 4;
	289	break;
	290	default:
	291	/* This will never execute */
	292	break;
	293	}
	294	} else {
	295	*data = 0;
	296	}
	297
	298	debug("%s: data 0x%08x tx_buf addr: 0x%08x size %d\n", __func__,
	299	*data, (u32)priv->tx_buf, size);
	300
	301	priv->bytes_to_transfer -= size;
	302	if (priv->bytes_to_transfer < 0)
	303	priv->bytes_to_transfer = 0;
	304	}
	305
17fbb598 ARS	306	/**
	307	* zynq_qspi_chipselect - Select or deselect the chip select line
	308	* @priv: Pointer to the zynq_qspi_priv structure
	309	* @is_on: Select(1) or deselect (0) the chip select line
	310	*/
46d0a991 JT	311	static void zynq_qspi_chipselect(struct zynq_qspi_priv *priv, int is_on)
	312	{
	313	u32 confr;
	314	struct zynq_qspi_regs *regs = priv->regs;
	315
	316	confr = readl(&regs->cr);
	317
	318	if (is_on) {
	319	/* Select the slave */
	320	confr &= ~ZYNQ_QSPI_CR_SS_MASK;
	321	confr \|= (~(1 << priv->cs) << ZYNQ_QSPI_CR_SS_SHIFT) &
	322	ZYNQ_QSPI_CR_SS_MASK;
	323	} else
	324	/* Deselect the slave */
	325	confr \|= ZYNQ_QSPI_CR_SS_MASK;
	326
	327	writel(confr, &regs->cr);
	328	}
	329
17fbb598	330	/**
46d0a991	331	* zynq_qspi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
17fbb598 ARS	332	* @priv: Pointer to the zynq_qspi_priv structure
17fbb598 ARS	333	* @size: Number of bytes to be copied to fifo
46d0a991 JT	334	*/
	335	static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv *priv, u32 size)
	336	{
	337	u32 data = 0;
	338	u32 fifocount = 0;
	339	unsigned len, offset;
	340	struct zynq_qspi_regs *regs = priv->regs;
	341	static const unsigned offsets[4] = {
	342	ZYNQ_QSPI_TXD_00_00_OFFSET, ZYNQ_QSPI_TXD_00_01_OFFSET,
	343	ZYNQ_QSPI_TXD_00_10_OFFSET, ZYNQ_QSPI_TXD_00_11_OFFSET };
	344
	345	while ((fifocount < size) &&
	346	(priv->bytes_to_transfer > 0)) {
	347	if (priv->bytes_to_transfer >= 4) {
	348	if (priv->tx_buf) {
	349	memcpy(&data, priv->tx_buf, 4);
	350	priv->tx_buf += 4;
	351	} else {
	352	data = 0;
	353	}
	354	writel(data, &regs->txd0r);
	355	priv->bytes_to_transfer -= 4;
	356	fifocount++;
	357	} else {
	358	/* Write TXD1, TXD2, TXD3 only if TxFIFO is empty. */
	359	if (!(readl(&regs->isr)
	360	& ZYNQ_QSPI_IXR_TXOW_MASK) &&
	361	!priv->rx_buf)
	362	return;
	363	len = priv->bytes_to_transfer;
	364	zynq_qspi_write_data(priv, &data, len);
	365	offset = (priv->rx_buf) ? offsets[0] : offsets[len];
	366	writel(data, &regs->cr + (offset / 4));
	367	}
	368	}
	369	}
	370
17fbb598	371	/**
46d0a991	372	* zynq_qspi_irq_poll - Interrupt service routine of the QSPI controller
17fbb598	373	* @priv: Pointer to the zynq_qspi structure
46d0a991 JT	374	*
	375	* This function handles TX empty and Mode Fault interrupts only.
	376	* On TX empty interrupt this function reads the received data from RX FIFO and
	377	* fills the TX FIFO if there is any data remaining to be transferred.
	378	* On Mode Fault interrupt this function indicates that transfer is completed,
	379	* the SPI subsystem will identify the error as the remaining bytes to be
	380	* transferred is non-zero.
	381	*
	382	* returns: 0 for poll timeout
	383	* 1 transfer operation complete
	384	*/
	385	static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv)
	386	{
	387	struct zynq_qspi_regs *regs = priv->regs;
	388	u32 rxindex = 0;
	389	u32 rxcount;
	390	u32 status, timeout;
	391
	392	/* Poll until any of the interrupt status bits are set */
	393	timeout = get_timer(0);
	394	do {
	395	status = readl(&regs->isr);
	396	} while ((status == 0) &&
f44bd3bc	397	(get_timer(timeout) < ZYNQ_QSPI_WAIT));
46d0a991 JT	398
	399	if (status == 0) {
	400	printf("zynq_qspi_irq_poll: Timeout!\n");
	401	return -ETIMEDOUT;
	402	}
	403
	404	writel(status, &regs->isr);
	405
	406	/* Disable all interrupts */
	407	writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->idr);
	408	if ((status & ZYNQ_QSPI_IXR_TXOW_MASK) \|\|
	409	(status & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)) {
	410	/*
	411	* This bit is set when Tx FIFO has < THRESHOLD entries. We have
	412	* the THRESHOLD value set to 1, so this bit indicates Tx FIFO
	413	* is empty
	414	*/
	415	rxcount = priv->bytes_to_receive - priv->bytes_to_transfer;
	416	rxcount = (rxcount % 4) ? ((rxcount/4)+1) : (rxcount/4);
	417	while ((rxindex < rxcount) &&
	418	(rxindex < ZYNQ_QSPI_RXFIFO_THRESHOLD)) {
	419	/* Read out the data from the RX FIFO */
	420	u32 data;
	421	data = readl(&regs->drxr);
	422
	423	if (priv->bytes_to_receive >= 4) {
	424	if (priv->rx_buf) {
	425	memcpy(priv->rx_buf, &data, 4);
	426	priv->rx_buf += 4;
	427	}
	428	priv->bytes_to_receive -= 4;
	429	} else {
	430	zynq_qspi_read_data(priv, data,
	431	priv->bytes_to_receive);
	432	}
	433	rxindex++;
	434	}
	435
	436	if (priv->bytes_to_transfer) {
	437	/* There is more data to send */
	438	zynq_qspi_fill_tx_fifo(priv,
	439	ZYNQ_QSPI_RXFIFO_THRESHOLD);
	440
	441	writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->ier);
	442	} else {
	443	/*
	444	* If transfer and receive is completed then only send
	445	* complete signal
	446	*/
	447	if (!priv->bytes_to_receive) {
	448	/* return operation complete */
	449	writel(ZYNQ_QSPI_IXR_ALL_MASK,
	450	&regs->idr);
	451	return 1;
	452	}
	453	}
	454	}
	455
	456	return 0;
	457	}
	458
17fbb598	459	/**
46d0a991	460	* zynq_qspi_start_transfer - Initiates the QSPI transfer
17fbb598	461	* @priv: Pointer to the zynq_qspi_priv structure
46d0a991 JT	462	*
	463	* This function fills the TX FIFO, starts the QSPI transfer, and waits for the
	464	* transfer to be completed.
	465	*
	466	* returns: Number of bytes transferred in the last transfer
	467	*/
	468	static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv)
	469	{
	470	u32 data = 0;
	471	struct zynq_qspi_regs *regs = priv->regs;
	472
	473	debug("%s: qspi: 0x%08x transfer: 0x%08x len: %d\n", __func__,
	474	(u32)priv, (u32)priv, priv->len);
	475
	476	priv->bytes_to_transfer = priv->len;
	477	priv->bytes_to_receive = priv->len;
	478
	479	if (priv->len < 4)
	480	zynq_qspi_fill_tx_fifo(priv, priv->len);
	481	else
	482	zynq_qspi_fill_tx_fifo(priv, priv->fifo_depth);
	483
	484	writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->ier);
46d0a991 JT	485
	486	/* wait for completion */
	487	do {
	488	data = zynq_qspi_irq_poll(priv);
	489	} while (data == 0);
	490
	491	return (priv->len) - (priv->bytes_to_transfer);
	492	}
	493
	494	static int zynq_qspi_transfer(struct zynq_qspi_priv *priv)
	495	{
	496	unsigned cs_change = 1;
	497	int status = 0;
	498
	499	while (1) {
	500	/* Select the chip if required */
	501	if (cs_change)
	502	zynq_qspi_chipselect(priv, 1);
	503
	504	cs_change = priv->cs_change;
	505
	506	if (!priv->tx_buf && !priv->rx_buf && priv->len) {
	507	status = -1;
	508	break;
	509	}
	510
	511	/* Request the transfer */
	512	if (priv->len) {
	513	status = zynq_qspi_start_transfer(priv);
	514	priv->is_inst = 0;
	515	}
	516
	517	if (status != priv->len) {
	518	if (status > 0)
	519	status = -EMSGSIZE;
	520	debug("zynq_qspi_transfer:%d len:%d\n",
	521	status, priv->len);
	522	break;
	523	}
	524	status = 0;
	525
	526	if (cs_change)
	527	/* Deselect the chip */
	528	zynq_qspi_chipselect(priv, 0);
	529
	530	break;
	531	}
	532
240cd756	533	return status;
46d0a991 JT	534	}
	535
	536	static int zynq_qspi_claim_bus(struct udevice *dev)
	537	{
	538	struct udevice *bus = dev->parent;
	539	struct zynq_qspi_priv *priv = dev_get_priv(bus);
	540	struct zynq_qspi_regs *regs = priv->regs;
	541
	542	writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
	543
	544	return 0;
	545	}
	546
	547	static int zynq_qspi_release_bus(struct udevice *dev)
	548	{
	549	struct udevice *bus = dev->parent;
	550	struct zynq_qspi_priv *priv = dev_get_priv(bus);
	551	struct zynq_qspi_regs *regs = priv->regs;
	552
	553	writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
	554
	555	return 0;
	556	}
	557
	558	static int zynq_qspi_xfer(struct udevice *dev, unsigned int bitlen,
	559	const void dout, void din, unsigned long flags)
	560	{
	561	struct udevice *bus = dev->parent;
	562	struct zynq_qspi_priv *priv = dev_get_priv(bus);
caa4daa2	563	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);
46d0a991 JT	564
	565	priv->cs = slave_plat->cs;
	566	priv->tx_buf = dout;
	567	priv->rx_buf = din;
	568	priv->len = bitlen / 8;
	569
e5e0d68f	570	debug("zynq_qspi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
46d0a991 JT	571	bus->seq, slave_plat->cs, bitlen, priv->len, flags);
	572
	573	/*
	574	* Festering sore.
	575	* Assume that the beginning of a transfer with bits to
	576	* transmit must contain a device command.
	577	*/
	578	if (dout && flags & SPI_XFER_BEGIN)
	579	priv->is_inst = 1;
	580	else
	581	priv->is_inst = 0;
	582
	583	if (flags & SPI_XFER_END)
	584	priv->cs_change = 1;
	585	else
	586	priv->cs_change = 0;
	587
	588	zynq_qspi_transfer(priv);
	589
	590	return 0;
	591	}
	592
	593	static int zynq_qspi_set_speed(struct udevice *bus, uint speed)
	594	{
caa4daa2	595	struct zynq_qspi_platdata *plat = bus->plat;
46d0a991 JT	596	struct zynq_qspi_priv *priv = dev_get_priv(bus);
	597	struct zynq_qspi_regs *regs = priv->regs;
	598	uint32_t confr;
	599	u8 baud_rate_val = 0;
	600
	601	if (speed > plat->frequency)
	602	speed = plat->frequency;
	603
	604	/* Set the clock frequency */
	605	confr = readl(&regs->cr);
	606	if (speed == 0) {
	607	/* Set baudrate x8, if the freq is 0 */
	608	baud_rate_val = 0x2;
	609	} else if (plat->speed_hz != speed) {
	610	while ((baud_rate_val < ZYNQ_QSPI_CR_BAUD_MAX) &&
	611	((plat->frequency /
	612	(2 << baud_rate_val)) > speed))
	613	baud_rate_val++;
	614
	615	plat->speed_hz = speed / (2 << baud_rate_val);
	616	}
	617	confr &= ~ZYNQ_QSPI_CR_BAUD_MASK;
	618	confr \|= (baud_rate_val << ZYNQ_QSPI_CR_BAUD_SHIFT);
	619
	620	writel(confr, &regs->cr);
	621	priv->freq = speed;
	622
e5e0d68f	623	debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
46d0a991 JT	624
	625	return 0;
	626	}
	627
	628	static int zynq_qspi_set_mode(struct udevice *bus, uint mode)
	629	{
	630	struct zynq_qspi_priv *priv = dev_get_priv(bus);
	631	struct zynq_qspi_regs *regs = priv->regs;
	632	uint32_t confr;
	633
	634	/* Set the SPI Clock phase and polarities */
	635	confr = readl(&regs->cr);
	636	confr &= ~(ZYNQ_QSPI_CR_CPHA_MASK \| ZYNQ_QSPI_CR_CPOL_MASK);
	637
2775e918	638	if (mode & SPI_CPHA)
46d0a991	639	confr \|= ZYNQ_QSPI_CR_CPHA_MASK;
2775e918	640	if (mode & SPI_CPOL)
46d0a991 JT	641	confr \|= ZYNQ_QSPI_CR_CPOL_MASK;
	642
	643	writel(confr, &regs->cr);
	644	priv->mode = mode;
	645
e5e0d68f	646	debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
46d0a991 JT	647
	648	return 0;
	649	}
	650
	651	static const struct dm_spi_ops zynq_qspi_ops = {
	652	.claim_bus = zynq_qspi_claim_bus,
	653	.release_bus = zynq_qspi_release_bus,
	654	.xfer = zynq_qspi_xfer,
	655	.set_speed = zynq_qspi_set_speed,
	656	.set_mode = zynq_qspi_set_mode,
	657	};
	658
	659	static const struct udevice_id zynq_qspi_ids[] = {
	660	{ .compatible = "xlnx,zynq-qspi-1.0" },
	661	{ }
	662	};
	663
	664	U_BOOT_DRIVER(zynq_qspi) = {
	665	.name = "zynq_qspi",
	666	.id = UCLASS_SPI,
	667	.of_match = zynq_qspi_ids,
	668	.ops = &zynq_qspi_ops,
d1998a9f	669	.of_to_plat = zynq_qspi_of_to_plat,
caa4daa2	670	.plat_auto = sizeof(struct zynq_qspi_platdata),
41575d8e	671	.priv_auto = sizeof(struct zynq_qspi_priv),
46d0a991 JT	672	.probe = zynq_qspi_probe,
46d0a991 JT	673	};