[J-u-boot.git] / common / cmd_eeprom.c

/*
 * (C) Copyright 2000, 2001
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * Support for read and write access to EEPROM like memory devices. This
 * includes regular EEPROM as well as  FRAM (ferroelectic nonvolaile RAM).
 * FRAM devices read and write data at bus speed. In particular, there is no
 * write delay. Also, there is no limit imposed on the number of bytes that can
 * be transferred with a single read or write.
 *
 * Use the following configuration options to ensure no unneeded performance
 * degradation (typical for EEPROM) is incured for FRAM memory:
 *
 * #define CONFIG_SYS_I2C_FRAM
 * #undef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
 *
 */

#include <common.h>
#include <config.h>
#include <command.h>
#include <i2c.h>

extern void eeprom_init  (void);
extern int  eeprom_read  (unsigned dev_addr, unsigned offset,
			  uchar *buffer, unsigned cnt);
extern int  eeprom_write (unsigned dev_addr, unsigned offset,
			  uchar *buffer, unsigned cnt);
#if defined(CONFIG_SYS_EEPROM_WREN)
extern int eeprom_write_enable (unsigned dev_addr, int state);
#endif


#if defined(CONFIG_SYS_EEPROM_X40430)
	/* Maximum number of times to poll for acknowledge after write */
#define MAX_ACKNOWLEDGE_POLLS	10
#endif

/* ------------------------------------------------------------------------- */

#if defined(CONFIG_CMD_EEPROM)
static int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	const char *const fmt =
		"\nEEPROM @0x%lX %s: addr %08lx  off %04lx  count %ld ... ";

#if defined(CONFIG_SYS_I2C_MULTI_EEPROMS)
	if (argc == 6) {
		ulong dev_addr = simple_strtoul (argv[2], NULL, 16);
		ulong addr = simple_strtoul (argv[3], NULL, 16);
		ulong off  = simple_strtoul (argv[4], NULL, 16);
		ulong cnt  = simple_strtoul (argv[5], NULL, 16);
#else
	if (argc == 5) {
		ulong dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
		ulong addr = simple_strtoul (argv[2], NULL, 16);
		ulong off  = simple_strtoul (argv[3], NULL, 16);
		ulong cnt  = simple_strtoul (argv[4], NULL, 16);
#endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */

# if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
		eeprom_init ();
# endif /* !CONFIG_SPI */

		if (strcmp (argv[1], "read") == 0) {
			int rcode;

			printf (fmt, dev_addr, argv[1], addr, off, cnt);

			rcode = eeprom_read (dev_addr, off, (uchar *) addr, cnt);

			puts ("done\n");
			return rcode;
		} else if (strcmp (argv[1], "write") == 0) {
			int rcode;

			printf (fmt, dev_addr, argv[1], addr, off, cnt);

			rcode = eeprom_write (dev_addr, off, (uchar *) addr, cnt);

			puts ("done\n");
			return rcode;
		}
	}

	return CMD_RET_USAGE;
}
#endif

/*-----------------------------------------------------------------------
 *
 * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
 *   0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
 *
 * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
 *   0x00000nxx for EEPROM address selectors and page number at n.
 */

#if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
#if !defined(CONFIG_SYS_I2C_EEPROM_ADDR_LEN) || CONFIG_SYS_I2C_EEPROM_ADDR_LEN < 1 || CONFIG_SYS_I2C_EEPROM_ADDR_LEN > 2
#error CONFIG_SYS_I2C_EEPROM_ADDR_LEN must be 1 or 2
#endif
#endif

int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
{
	unsigned end = offset + cnt;
	unsigned blk_off;
	int rcode = 0;

	/* Read data until done or would cross a page boundary.
	 * We must write the address again when changing pages
	 * because the next page may be in a different device.
	 */
	while (offset < end) {
		unsigned alen, len;
#if !defined(CONFIG_SYS_I2C_FRAM)
		unsigned maxlen;
#endif

#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
		uchar addr[2];

		blk_off = offset & 0xFF;	/* block offset */

		addr[0] = offset >> 8;		/* block number */
		addr[1] = blk_off;		/* block offset */
		alen	= 2;
#else
		uchar addr[3];

		blk_off = offset & 0xFF;	/* block offset */

		addr[0] = offset >> 16;		/* block number */
		addr[1] = offset >>  8;		/* upper address octet */
		addr[2] = blk_off;		/* lower address octet */
		alen	= 3;
#endif	/* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */

		addr[0] |= dev_addr;		/* insert device address */

		len = end - offset;

		/*
		 * For a FRAM device there is no limit on the number of the
		 * bytes that can be ccessed with the single read or write
		 * operation.
		 */
#if !defined(CONFIG_SYS_I2C_FRAM)
		maxlen = 0x100 - blk_off;
		if (maxlen > I2C_RXTX_LEN)
			maxlen = I2C_RXTX_LEN;
		if (len > maxlen)
			len = maxlen;
#endif

#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
		spi_read (addr, alen, buffer, len);
#else
#if defined(CONFIG_SYS_I2C_EEPROM_BUS)
		i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
#endif
		if (i2c_read(addr[0], offset, alen - 1, buffer, len))
			rcode = 1;
#endif
		buffer += len;
		offset += len;
	}

	return rcode;
}

/*-----------------------------------------------------------------------
 *
 * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
 *   0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
 *
 * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
 *   0x00000nxx for EEPROM address selectors and page number at n.
 */

int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
{
	unsigned end = offset + cnt;
	unsigned blk_off;
	int rcode = 0;

#if defined(CONFIG_SYS_EEPROM_X40430)
	uchar	contr_r_addr[2];
	uchar	addr_void[2];
	uchar	contr_reg[2];
	uchar	ctrl_reg_v;
	int	i;
#endif

#if defined(CONFIG_SYS_EEPROM_WREN)
	eeprom_write_enable (dev_addr,1);
#endif
	/* Write data until done or would cross a write page boundary.
	 * We must write the address again when changing pages
	 * because the address counter only increments within a page.
	 */

	while (offset < end) {
		unsigned alen, len;
#if !defined(CONFIG_SYS_I2C_FRAM)
		unsigned maxlen;
#endif

#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
		uchar addr[2];

		blk_off = offset & 0xFF;	/* block offset */

		addr[0] = offset >> 8;		/* block number */
		addr[1] = blk_off;		/* block offset */
		alen	= 2;
#else
		uchar addr[3];

		blk_off = offset & 0xFF;	/* block offset */

		addr[0] = offset >> 16;		/* block number */
		addr[1] = offset >>  8;		/* upper address octet */
		addr[2] = blk_off;		/* lower address octet */
		alen	= 3;
#endif	/* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */

		addr[0] |= dev_addr;		/* insert device address */

		len = end - offset;

		/*
		 * For a FRAM device there is no limit on the number of the
		 * bytes that can be accessed with the single read or write
		 * operation.
		 */
#if !defined(CONFIG_SYS_I2C_FRAM)

#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)

#define	EEPROM_PAGE_SIZE	(1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
#define	EEPROM_PAGE_OFFSET(x)	((x) & (EEPROM_PAGE_SIZE - 1))

		maxlen = EEPROM_PAGE_SIZE - EEPROM_PAGE_OFFSET(blk_off);
#else
		maxlen = 0x100 - blk_off;
#endif
		if (maxlen > I2C_RXTX_LEN)
			maxlen = I2C_RXTX_LEN;

		if (len > maxlen)
			len = maxlen;
#endif

#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
		spi_write (addr, alen, buffer, len);
#else
#if defined(CONFIG_SYS_EEPROM_X40430)
		/* Get the value of the control register.
		 * Set current address (internal pointer in the x40430)
		 * to 0x1ff.
		 */
		contr_r_addr[0] = 9;
		contr_r_addr[1] = 0xff;
		addr_void[0]    = 0;
		addr_void[1]    = addr[1];
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
		contr_r_addr[0] |= CONFIG_SYS_I2C_EEPROM_ADDR;
		addr_void[0]    |= CONFIG_SYS_I2C_EEPROM_ADDR;
#endif
		contr_reg[0] = 0xff;
		if (i2c_read (contr_r_addr[0], contr_r_addr[1], 1, contr_reg, 1) != 0) {
			rcode = 1;
		}
		ctrl_reg_v = contr_reg[0];

		/* Are any of the eeprom blocks write protected?
		 */
		if (ctrl_reg_v & 0x18) {
			ctrl_reg_v &= ~0x18;   /* reset block protect bits  */
			ctrl_reg_v |=  0x02;   /* set write enable latch    */
			ctrl_reg_v &= ~0x04;   /* clear RWEL                */

			/* Set write enable latch.
			 */
			contr_reg[0] = 0x02;
			if (i2c_write (contr_r_addr[0], 0xff, 1, contr_reg, 1) != 0) {
				rcode = 1;
			}

			/* Set register write enable latch.
			 */
			contr_reg[0] = 0x06;
			if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
				rcode = 1;
			}

			/* Modify ctrl register.
			 */
			contr_reg[0] = ctrl_reg_v;
			if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
				rcode = 1;
			}

			/* The write (above) is an operation on NV memory.
			 * These can take some time (~5ms), and the device
			 * will not respond to further I2C messages till
			 * it's completed the write.
			 * So poll device for an I2C acknowledge.
			 * When we get one we know we can continue with other
			 * operations.
			 */
			contr_reg[0] = 0;
			for (i = 0; i < MAX_ACKNOWLEDGE_POLLS; i++) {
				if (i2c_read (addr_void[0], addr_void[1], 1, contr_reg, 1) == 0)
					break;	/* got ack */
#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
				udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
#endif
			}
			if (i == MAX_ACKNOWLEDGE_POLLS) {
				puts ("EEPROM poll acknowledge failed\n");
				rcode = 1;
			}
		}

		/* Is the write enable latch on?.
		 */
		else if (!(ctrl_reg_v & 0x02)) {
			/* Set write enable latch.
			 */
			contr_reg[0] = 0x02;
			if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
			       rcode = 1;
			}
		}
		/* Write is enabled ... now write eeprom value.
		 */
#endif
#if defined(CONFIG_SYS_I2C_EEPROM_BUS)
		i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
#endif
		if (i2c_write(addr[0], offset, alen - 1, buffer, len))
			rcode = 1;

#endif
		buffer += len;
		offset += len;

#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
		udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
#endif
	}
#if defined(CONFIG_SYS_EEPROM_WREN)
	eeprom_write_enable (dev_addr,0);
#endif
	return rcode;
}

#if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
int
eeprom_probe (unsigned dev_addr, unsigned offset)
{
	unsigned char chip;

	/* Probe the chip address
	 */
#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
	chip = offset >> 8;		/* block number */
#else
	chip = offset >> 16;		/* block number */
#endif	/* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */

	chip |= dev_addr;		/* insert device address */

	return (i2c_probe (chip));
}
#endif

/*-----------------------------------------------------------------------
 * Set default values
 */
#ifndef	CONFIG_SYS_I2C_SPEED
#define	CONFIG_SYS_I2C_SPEED	50000
#endif

void eeprom_init  (void)
{

#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
	spi_init_f ();
#endif
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
}

/*-----------------------------------------------------------------------
 */

/***************************************************/

#if defined(CONFIG_CMD_EEPROM)

#ifdef CONFIG_SYS_I2C_MULTI_EEPROMS
U_BOOT_CMD(
	eeprom,	6,	1,	do_eeprom,
	"EEPROM sub-system",
	"read  devaddr addr off cnt\n"
	"eeprom write devaddr addr off cnt\n"
	"       - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'"
)
#else /* One EEPROM */
U_BOOT_CMD(
	eeprom,	5,	1,	do_eeprom,
	"EEPROM sub-system",
	"read  addr off cnt\n"
	"eeprom write addr off cnt\n"
	"       - read/write `cnt' bytes at EEPROM offset `off'"
)
#endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */

#endif
Commit	Line	Data
3863585b WD	1	/*
	2	* (C) Copyright 2000, 2001
	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
3863585b WD	6	*/
3863585b WD	7
d4f5c728	8	/*
	9	* Support for read and write access to EEPROM like memory devices. This
	10	* includes regular EEPROM as well as FRAM (ferroelectic nonvolaile RAM).
	11	* FRAM devices read and write data at bus speed. In particular, there is no
e506a006	12	* write delay. Also, there is no limit imposed on the number of bytes that can
d4f5c728	13	* be transferred with a single read or write.
6617aae9	14	*
d4f5c728	15	* Use the following configuration options to ensure no unneeded performance
d4f5c728	16	* degradation (typical for EEPROM) is incured for FRAM memory:
6617aae9	17	*
6d0f6bcf JCPV	18	* #define CONFIG_SYS_I2C_FRAM
6d0f6bcf JCPV	19	* #undef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
d4f5c728	20	*
	21	*/
	22
3863585b WD	23	#include <common.h>
	24	#include <config.h>
	25	#include <command.h>
	26	#include <i2c.h>
	27
3863585b WD	28	extern void eeprom_init (void);
	29	extern int eeprom_read (unsigned dev_addr, unsigned offset,
	30	uchar *buffer, unsigned cnt);
	31	extern int eeprom_write (unsigned dev_addr, unsigned offset,
	32	uchar *buffer, unsigned cnt);
6d0f6bcf	33	#if defined(CONFIG_SYS_EEPROM_WREN)
98f4a3df SR	34	extern int eeprom_write_enable (unsigned dev_addr, int state);
98f4a3df SR	35	#endif
3863585b WD	36
3863585b WD	37
6d0f6bcf	38	#if defined(CONFIG_SYS_EEPROM_X40430)
3863585b WD	39	/* Maximum number of times to poll for acknowledge after write */
	40	#define MAX_ACKNOWLEDGE_POLLS 10
	41	#endif
	42
	43	/* ------------------------------------------------------------------------- */
	44
baa26db4	45	#if defined(CONFIG_CMD_EEPROM)
0e350f81	46	static int do_eeprom(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
3863585b WD	47	{
	48	const char *const fmt =
	49	"\nEEPROM @0x%lX %s: addr %08lx off %04lx count %ld ... ";
	50
6d0f6bcf	51	#if defined(CONFIG_SYS_I2C_MULTI_EEPROMS)
3863585b WD	52	if (argc == 6) {
	53	ulong dev_addr = simple_strtoul (argv[2], NULL, 16);
	54	ulong addr = simple_strtoul (argv[3], NULL, 16);
	55	ulong off = simple_strtoul (argv[4], NULL, 16);
	56	ulong cnt = simple_strtoul (argv[5], NULL, 16);
	57	#else
	58	if (argc == 5) {
6d0f6bcf	59	ulong dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
3863585b WD	60	ulong addr = simple_strtoul (argv[2], NULL, 16);
	61	ulong off = simple_strtoul (argv[3], NULL, 16);
	62	ulong cnt = simple_strtoul (argv[4], NULL, 16);
6d0f6bcf	63	#endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */
3863585b	64
548738b4	65	# if !defined(CONFIG_SPI) \|\| defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
3863585b WD	66	eeprom_init ();
	67	# endif /* !CONFIG_SPI */
	68
	69	if (strcmp (argv[1], "read") == 0) {
	70	int rcode;
	71
	72	printf (fmt, dev_addr, argv[1], addr, off, cnt);
	73
	74	rcode = eeprom_read (dev_addr, off, (uchar *) addr, cnt);
	75
4b9206ed	76	puts ("done\n");
3863585b WD	77	return rcode;
	78	} else if (strcmp (argv[1], "write") == 0) {
	79	int rcode;
	80
	81	printf (fmt, dev_addr, argv[1], addr, off, cnt);
	82
	83	rcode = eeprom_write (dev_addr, off, (uchar *) addr, cnt);
	84
4b9206ed	85	puts ("done\n");
3863585b WD	86	return rcode;
	87	}
	88	}
	89
4c12eeb8	90	return CMD_RET_USAGE;
3863585b	91	}
90253178	92	#endif
3863585b WD	93
	94	/*-----------------------------------------------------------------------
	95	*
6d0f6bcf	96	* for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
3863585b WD	97	* 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
3863585b WD	98	*
6d0f6bcf	99	* for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
3863585b WD	100	* 0x00000nxx for EEPROM address selectors and page number at n.
	101	*/
	102
548738b4	103	#if !defined(CONFIG_SPI) \|\| defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
6d0f6bcf JCPV	104	#if !defined(CONFIG_SYS_I2C_EEPROM_ADDR_LEN) \|\| CONFIG_SYS_I2C_EEPROM_ADDR_LEN < 1 \|\| CONFIG_SYS_I2C_EEPROM_ADDR_LEN > 2
6d0f6bcf JCPV	105	#error CONFIG_SYS_I2C_EEPROM_ADDR_LEN must be 1 or 2
3863585b WD	106	#endif
	107	#endif
	108
	109	int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
	110	{
	111	unsigned end = offset + cnt;
	112	unsigned blk_off;
	113	int rcode = 0;
	114
	115	/* Read data until done or would cross a page boundary.
	116	* We must write the address again when changing pages
	117	* because the next page may be in a different device.
	118	*/
	119	while (offset < end) {
d4f5c728	120	unsigned alen, len;
6d0f6bcf	121	#if !defined(CONFIG_SYS_I2C_FRAM)
d4f5c728	122	unsigned maxlen;
	123	#endif
	124
6d0f6bcf	125	#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
3863585b WD	126	uchar addr[2];
	127
	128	blk_off = offset & 0xFF; /* block offset */
	129
	130	addr[0] = offset >> 8; /* block number */
	131	addr[1] = blk_off; /* block offset */
	132	alen = 2;
	133	#else
	134	uchar addr[3];
	135
	136	blk_off = offset & 0xFF; /* block offset */
	137
	138	addr[0] = offset >> 16; /* block number */
	139	addr[1] = offset >> 8; /* upper address octet */
	140	addr[2] = blk_off; /* lower address octet */
	141	alen = 3;
6d0f6bcf	142	#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
3863585b WD	143
	144	addr[0] \|= dev_addr; /* insert device address */
	145
d4f5c728	146	len = end - offset;
	147
	148	/*
	149	* For a FRAM device there is no limit on the number of the
	150	* bytes that can be ccessed with the single read or write
	151	* operation.
	152	*/
6d0f6bcf	153	#if !defined(CONFIG_SYS_I2C_FRAM)
3863585b WD	154	maxlen = 0x100 - blk_off;
	155	if (maxlen > I2C_RXTX_LEN)
	156	maxlen = I2C_RXTX_LEN;
3863585b WD	157	if (len > maxlen)
3863585b WD	158	len = maxlen;
d4f5c728	159	#endif
d4f5c728	160
548738b4	161	#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
3863585b WD	162	spi_read (addr, alen, buffer, len);
3863585b WD	163	#else
189d257b CG	164	#if defined(CONFIG_SYS_I2C_EEPROM_BUS)
	165	i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
	166	#endif
6ca6d080	167	if (i2c_read(addr[0], offset, alen - 1, buffer, len))
3863585b WD	168	rcode = 1;
	169	#endif
	170	buffer += len;
	171	offset += len;
	172	}
d4f5c728	173
3863585b WD	174	return rcode;
	175	}
	176
	177	/*-----------------------------------------------------------------------
	178	*
6d0f6bcf	179	* for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
3863585b WD	180	* 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
3863585b WD	181	*
6d0f6bcf	182	* for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
3863585b WD	183	* 0x00000nxx for EEPROM address selectors and page number at n.
	184	*/
	185
	186	int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
	187	{
	188	unsigned end = offset + cnt;
	189	unsigned blk_off;
	190	int rcode = 0;
	191
6d0f6bcf	192	#if defined(CONFIG_SYS_EEPROM_X40430)
3863585b WD	193	uchar contr_r_addr[2];
	194	uchar addr_void[2];
	195	uchar contr_reg[2];
	196	uchar ctrl_reg_v;
	197	int i;
	198	#endif
	199
6d0f6bcf	200	#if defined(CONFIG_SYS_EEPROM_WREN)
98f4a3df SR	201	eeprom_write_enable (dev_addr,1);
98f4a3df SR	202	#endif
3863585b WD	203	/* Write data until done or would cross a write page boundary.
	204	* We must write the address again when changing pages
	205	* because the address counter only increments within a page.
	206	*/
	207
	208	while (offset < end) {
d4f5c728	209	unsigned alen, len;
6d0f6bcf	210	#if !defined(CONFIG_SYS_I2C_FRAM)
d4f5c728	211	unsigned maxlen;
	212	#endif
	213
6d0f6bcf	214	#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
3863585b WD	215	uchar addr[2];
	216
	217	blk_off = offset & 0xFF; /* block offset */
	218
	219	addr[0] = offset >> 8; /* block number */
	220	addr[1] = blk_off; /* block offset */
	221	alen = 2;
	222	#else
	223	uchar addr[3];
	224
	225	blk_off = offset & 0xFF; /* block offset */
	226
	227	addr[0] = offset >> 16; /* block number */
	228	addr[1] = offset >> 8; /* upper address octet */
	229	addr[2] = blk_off; /* lower address octet */
	230	alen = 3;
6d0f6bcf	231	#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
3863585b WD	232
	233	addr[0] \|= dev_addr; /* insert device address */
	234
d4f5c728	235	len = end - offset;
	236
	237	/*
	238	* For a FRAM device there is no limit on the number of the
f9a78b8d	239	* bytes that can be accessed with the single read or write
d4f5c728	240	* operation.
d4f5c728	241	*/
6d0f6bcf	242	#if !defined(CONFIG_SYS_I2C_FRAM)
d4f5c728	243
6d0f6bcf	244	#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
3863585b	245
6d0f6bcf	246	#define EEPROM_PAGE_SIZE (1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
3863585b WD	247	#define EEPROM_PAGE_OFFSET(x) ((x) & (EEPROM_PAGE_SIZE - 1))
	248
	249	maxlen = EEPROM_PAGE_SIZE - EEPROM_PAGE_OFFSET(blk_off);
	250	#else
	251	maxlen = 0x100 - blk_off;
	252	#endif
	253	if (maxlen > I2C_RXTX_LEN)
	254	maxlen = I2C_RXTX_LEN;
	255
3863585b WD	256	if (len > maxlen)
3863585b WD	257	len = maxlen;
d4f5c728	258	#endif
d4f5c728	259
548738b4	260	#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
3863585b WD	261	spi_write (addr, alen, buffer, len);
3863585b WD	262	#else
6d0f6bcf	263	#if defined(CONFIG_SYS_EEPROM_X40430)
3863585b WD	264	/* Get the value of the control register.
	265	* Set current address (internal pointer in the x40430)
	266	* to 0x1ff.
	267	*/
	268	contr_r_addr[0] = 9;
	269	contr_r_addr[1] = 0xff;
	270	addr_void[0] = 0;
	271	addr_void[1] = addr[1];
6d0f6bcf JCPV	272	#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
	273	contr_r_addr[0] \|= CONFIG_SYS_I2C_EEPROM_ADDR;
	274	addr_void[0] \|= CONFIG_SYS_I2C_EEPROM_ADDR;
3863585b WD	275	#endif
	276	contr_reg[0] = 0xff;
	277	if (i2c_read (contr_r_addr[0], contr_r_addr[1], 1, contr_reg, 1) != 0) {
	278	rcode = 1;
	279	}
	280	ctrl_reg_v = contr_reg[0];
	281
	282	/* Are any of the eeprom blocks write protected?
	283	*/
	284	if (ctrl_reg_v & 0x18) {
	285	ctrl_reg_v &= ~0x18; /* reset block protect bits */
	286	ctrl_reg_v \|= 0x02; /* set write enable latch */
	287	ctrl_reg_v &= ~0x04; /* clear RWEL */
	288
	289	/* Set write enable latch.
	290	*/
	291	contr_reg[0] = 0x02;
	292	if (i2c_write (contr_r_addr[0], 0xff, 1, contr_reg, 1) != 0) {
	293	rcode = 1;
	294	}
	295
	296	/* Set register write enable latch.
	297	*/
	298	contr_reg[0] = 0x06;
	299	if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
	300	rcode = 1;
	301	}
	302
	303	/* Modify ctrl register.
	304	*/
	305	contr_reg[0] = ctrl_reg_v;
	306	if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
	307	rcode = 1;
	308	}
	309
	310	/* The write (above) is an operation on NV memory.
	311	* These can take some time (~5ms), and the device
	312	* will not respond to further I2C messages till
	313	* it's completed the write.
	314	* So poll device for an I2C acknowledge.
	315	* When we get one we know we can continue with other
	316	* operations.
	317	*/
	318	contr_reg[0] = 0;
	319	for (i = 0; i < MAX_ACKNOWLEDGE_POLLS; i++) {
aacf9a49	320	if (i2c_read (addr_void[0], addr_void[1], 1, contr_reg, 1) == 0)
3863585b	321	break; /* got ack */
6d0f6bcf JCPV	322	#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
6d0f6bcf JCPV	323	udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
3863585b WD	324	#endif
	325	}
	326	if (i == MAX_ACKNOWLEDGE_POLLS) {
4b9206ed	327	puts ("EEPROM poll acknowledge failed\n");
3863585b WD	328	rcode = 1;
	329	}
	330	}
	331
	332	/* Is the write enable latch on?.
	333	*/
	334	else if (!(ctrl_reg_v & 0x02)) {
	335	/* Set write enable latch.
	336	*/
	337	contr_reg[0] = 0x02;
	338	if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
	339	rcode = 1;
	340	}
	341	}
	342	/* Write is enabled ... now write eeprom value.
	343	*/
189d257b CG	344	#endif
	345	#if defined(CONFIG_SYS_I2C_EEPROM_BUS)
	346	i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
3863585b	347	#endif
6ca6d080	348	if (i2c_write(addr[0], offset, alen - 1, buffer, len))
3863585b WD	349	rcode = 1;
	350
	351	#endif
	352	buffer += len;
	353	offset += len;
	354
6d0f6bcf JCPV	355	#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
6d0f6bcf JCPV	356	udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
3863585b WD	357	#endif
3863585b WD	358	}
6d0f6bcf	359	#if defined(CONFIG_SYS_EEPROM_WREN)
98f4a3df SR	360	eeprom_write_enable (dev_addr,0);
98f4a3df SR	361	#endif
3863585b WD	362	return rcode;
	363	}
	364
548738b4	365	#if !defined(CONFIG_SPI) \|\| defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
6dd652fa WD	366	int
	367	eeprom_probe (unsigned dev_addr, unsigned offset)
	368	{
	369	unsigned char chip;
	370
	371	/* Probe the chip address
	372	*/
6d0f6bcf	373	#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
6dd652fa WD	374	chip = offset >> 8; /* block number */
	375	#else
	376	chip = offset >> 16; /* block number */
6d0f6bcf	377	#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
6dd652fa WD	378
	379	chip \|= dev_addr; /* insert device address */
	380
	381	return (i2c_probe (chip));
	382	}
	383	#endif
	384
3863585b WD	385	/*-----------------------------------------------------------------------
	386	* Set default values
	387	*/
6d0f6bcf JCPV	388	#ifndef CONFIG_SYS_I2C_SPEED
6d0f6bcf JCPV	389	#define CONFIG_SYS_I2C_SPEED 50000
3863585b WD	390	#endif
3863585b WD	391
3863585b WD	392	void eeprom_init (void)
3863585b WD	393	{
548738b4 HS	394
548738b4 HS	395	#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
3863585b WD	396	spi_init_f ();
3863585b WD	397	#endif
4bf3a56f VL	398	#if defined(CONFIG_HARD_I2C) \|\| defined(CONFIG_SYS_I2C_SOFT)
4bf3a56f VL	399	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
3863585b WD	400	#endif
3863585b WD	401	}
548738b4	402
3863585b WD	403	/*-----------------------------------------------------------------------
3863585b WD	404	*/
90253178	405
8bde7f77 WD	406	/***************************************************/
8bde7f77 WD	407
baa26db4	408	#if defined(CONFIG_CMD_EEPROM)
8bde7f77	409
6d0f6bcf	410	#ifdef CONFIG_SYS_I2C_MULTI_EEPROMS
0d498393 WD	411	U_BOOT_CMD(
0d498393 WD	412	eeprom, 6, 1, do_eeprom,
2fb2604d	413	"EEPROM sub-system",
8bde7f77 WD	414	"read devaddr addr off cnt\n"
8bde7f77 WD	415	"eeprom write devaddr addr off cnt\n"
a89c33db	416	" - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'"
0e350f81	417	)
8bde7f77	418	#else /* One EEPROM */
0d498393 WD	419	U_BOOT_CMD(
0d498393 WD	420	eeprom, 5, 1, do_eeprom,
2fb2604d	421	"EEPROM sub-system",
8bde7f77 WD	422	"read addr off cnt\n"
8bde7f77 WD	423	"eeprom write addr off cnt\n"
a89c33db	424	" - read/write `cnt' bytes at EEPROM offset `off'"
0e350f81	425	)
6d0f6bcf	426	#endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */
8bde7f77	427
90253178	428	#endif