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83d290c5 1/* SPDX-License-Identifier: GPL-2.0+ */
dde3b70d
SG
2/*
3 * Copyright (c) 2004-2008 Texas Instruments
4 *
5 * (C) Copyright 2002
6 * Gary Jennejohn, DENX Software Engineering, <[email protected]>
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SG
7 */
8
bf433afd 9#include <config.h>
980d6a55 10#include <asm/psci.h>
bf433afd 11
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12OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
13OUTPUT_ARCH(arm)
14ENTRY(_start)
15SECTIONS
16{
c5e954ec 17#if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC)
d47cb0b6 18 /*
c5e954ec
WD
19 * If CONFIG_ARMV7_SECURE_BASE is true, secure code will not
20 * bundle with u-boot, and code offsets are fixed. Secure zone
21 * only needs to be copied from the loading address to
22 * CONFIG_ARMV7_SECURE_BASE, which is the linking and running
23 * address for secure code.
d47cb0b6 24 *
c5e954ec
WD
25 * If CONFIG_ARMV7_SECURE_BASE is undefined, the secure zone will
26 * be included in u-boot address space, and some absolute address
27 * were used in secure code. The absolute addresses of the secure
28 * code also needs to be relocated along with the accompanying u-boot
29 * code.
30 *
31 * So DISCARD is only for CONFIG_ARMV7_SECURE_BASE.
d47cb0b6
PF
32 */
33 /DISCARD/ : { *(.rel._secure*) }
c5e954ec 34#endif
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35 . = 0x00000000;
36
37 . = ALIGN(4);
4ee32ea0 38 __image_copy_start = ADDR(.text);
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39 .text :
40 {
41623c91 41 *(.vectors)
b68d6712 42 CPUDIR/start.o (.text*)
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AG
43 }
44
45 /* This needs to come before *(.text*) */
7828a1ee 46 .efi_runtime : {
c0802104 47 __efi_runtime_start = .;
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48 *(.text.efi_runtime*)
49 *(.rodata.efi_runtime*)
50 *(.data.efi_runtime*)
c0802104 51 __efi_runtime_stop = .;
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AG
52 }
53
54 .text_rest :
55 {
b68d6712 56 *(.text*)
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SG
57 }
58
104d6fb6 59#ifdef CONFIG_ARMV7_NONSEC
bf433afd 60
a1274cc9 61 /* Align the secure section only if we're going to use it in situ */
792b2047 62 .__secure_start
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CYT
63#ifndef CONFIG_ARMV7_SECURE_BASE
64 ALIGN(CONSTANT(COMMONPAGESIZE))
65#endif
792b2047 66 : {
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CYT
67 KEEP(*(.__secure_start))
68 }
69
bf433afd 70#ifndef CONFIG_ARMV7_SECURE_BASE
ae8a922b 71#define __ARMV7_SECURE_BASE
b56e06d3 72#define __ARMV7_PSCI_STACK_IN_RAM
ae8a922b
TR
73#else
74#define __ARMV7_SECURE_BASE CONFIG_ARMV7_SECURE_BASE
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MZ
75#endif
76
ae8a922b 77 .secure_text __ARMV7_SECURE_BASE :
bf433afd
MZ
78 AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
79 {
80 *(._secure.text)
81 }
82
a5aa7ff3
CYT
83 .secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text))
84 {
85 *(._secure.data)
86 }
87
2fe1281c 88#ifdef CONFIG_ARMV7_PSCI
a5aa7ff3 89 .secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data),
980d6a55 90 CONSTANT(COMMONPAGESIZE)) (NOLOAD) :
b56e06d3 91#ifdef __ARMV7_PSCI_STACK_IN_RAM
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92 AT(ADDR(.secure_stack))
93#else
a5aa7ff3 94 AT(LOADADDR(.secure_data) + SIZEOF(.secure_data))
980d6a55
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95#endif
96 {
97 KEEP(*(.__secure_stack_start))
2fe1281c 98
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99 /* Skip addreses for stack */
100 . = . + CONFIG_ARMV7_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE;
2fe1281c 101
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102 /* Align end of stack section to page boundary */
103 . = ALIGN(CONSTANT(COMMONPAGESIZE));
104
105 KEEP(*(.__secure_stack_end))
3eff6818
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106
107#ifdef CONFIG_ARMV7_SECURE_MAX_SIZE
108 /*
109 * We are not checking (__secure_end - __secure_start) here,
110 * as these are the load addresses, and do not include the
111 * stack section. Instead, use the end of the stack section
112 * and the start of the text section.
113 */
114 ASSERT((. - ADDR(.secure_text)) <= CONFIG_ARMV7_SECURE_MAX_SIZE,
115 "Error: secure section exceeds secure memory size");
116#endif
980d6a55
CYT
117 }
118
119#ifndef __ARMV7_PSCI_STACK_IN_RAM
120 /* Reset VMA but don't allocate space if we have secure SRAM */
121 . = LOADADDR(.secure_stack);
2fe1281c
MY
122#endif
123
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124#endif
125
980d6a55 126 .__secure_end : AT(ADDR(.__secure_end)) {
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127 *(.__secure_end)
128 LONG(0x1d1071c); /* Must output something to reset LMA */
129 }
130#endif
131
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SG
132 . = ALIGN(4);
133 .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
134
135 . = ALIGN(4);
136 .data : {
b68d6712 137 *(.data*)
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SG
138 }
139
140 . = ALIGN(4);
141
142 . = .;
dde3b70d 143
55675142 144 . = ALIGN(4);
99e2fbcb
AS
145 __u_boot_list : {
146 KEEP(*(SORT(__u_boot_list*)));
55675142
MV
147 }
148
7828a1ee 149 .efi_runtime_rel : {
6b7f91cd 150 __efi_runtime_rel_start = .;
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151 *(.rel*.efi_runtime)
152 *(.rel*.efi_runtime.*)
6b7f91cd 153 __efi_runtime_rel_stop = .;
50149ea3
AG
154 }
155
83ebd4a6 156 . = ALIGN(4);
4ee32ea0 157 __image_copy_end = .;
dde3b70d 158
7828a1ee
IA
159 /*
160 * if CONFIG_USE_ARCH_MEMSET is not selected __bss_end - __bss_start
161 * needs to be a multiple of 4 and we overlay .bss with .rel.dyn
162 */
742752af
IA
163 .rel.dyn ALIGN(4) : {
164 __rel_dyn_start = .;
dde3b70d 165 *(.rel*)
742752af 166 __rel_dyn_end = .;
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SG
167 }
168
c1eb7a99 169 _end = .;
d0b5d9da 170 _image_binary_end = .;
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SG
171
172 /*
173 * Deprecated: this MMU section is used by pxa at present but
174 * should not be used by new boards/CPUs.
175 */
176 . = ALIGN(4096);
177 .mmutable : {
178 *(.mmutable)
179 }
180
f84a7b8f 181/*
faf396aa
IA
182 * These sections occupy the same memory, but their lifetimes do
183 * not overlap: U-Boot initializes .bss only after applying dynamic
184 * relocations and therefore after it doesn't need .rel.dyn any more.
f84a7b8f 185 */
faf396aa
IA
186 .bss ADDR(.rel.dyn) (OVERLAY): {
187 __bss_start = .;
b68d6712 188 *(.bss*)
faf396aa
IA
189 . = ALIGN(4);
190 __bss_end = .;
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191 }
192
d0b5d9da 193 .dynsym _image_binary_end : { *(.dynsym) }
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AA
194 .dynbss : { *(.dynbss) }
195 .dynstr : { *(.dynstr*) }
196 .dynamic : { *(.dynamic*) }
197 .plt : { *(.plt*) }
198 .interp : { *(.interp*) }
2c67e0e7 199 .gnu.hash : { *(.gnu.hash) }
47ed5dd0
AA
200 .gnu : { *(.gnu*) }
201 .ARM.exidx : { *(.ARM.exidx*) }
b02bfc4d 202 .gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) }
dde3b70d 203}
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