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* Fix NSCU config; add ethernet wakeup code.
[J-u-boot.git] / include / mc9328.h
CommitLineData
2d24a3a7
WD		 1/*
2 * include/mc9328.h
49822e23 3 *
2d24a3a7
WD		 4 * (c) Copyright 2004
5 * Techware Information Technology, Inc.
6 * http://www.techware.com.tw/
7 *
8 * Ming-Len Wu <[email protected]>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
49822e23 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2d24a3a7
WD		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
2d24a3a7
WD		 26#ifndef __MC9328_H__
27#define __MC9328_H__
28
49822e23
WD		 29typedef volatile unsigned long VU32;
30typedef VU32 * P_VU32;
2d24a3a7
WD		 31
32#define __REG(x) (*((volatile u32 *)(x)))
33
2d24a3a7 34/*
49822e23 35 * MX1 Chip selects & internal memory's
2d24a3a7 36 */
49822e23
WD		 37#define MX1_DMI_PHYS 0x00000000 /* double map image */
38#define MX1_BROM_PHYS 0x00100000 /* Bootstrape ROM */
2d24a3a7
WD		 39#define MX1_ESRAM_PHYS 0x00300000 /* Embedded SRAM (128KB)*/
40
49822e23
WD		 41#define MX1_CSD0_PHYS 0x08000000 /* CSD0 64MB (SDRAM) */
42#define MX1_CSD1_PHYS 0x0C000000 /* CSD1 64MB (SDRAM) */
43#define MX1_CS0_PHYS 0x10000000 /* CS0 32MB (Flash) */
44#define MX1_CS1_PHYS 0x12000000 /* CS1 16MB (Flash) */
45#define MX1_CS2_PHYS 0x13000000 /* CS2 16MB (Ext SRAM) */
46#define MX1_CS3_PHYS 0x14000000 /* CS3 16MB (Spare) */
47#define MX1_CS4_PHYS 0x15000000 /* CS4 16MB (Spare) */
48#define MX1_CS5_PHYS 0x16000000 /* CS5 16MB (Spare) */
2d24a3a7
WD		 49
50/*
49822e23 51 * MX1 Watchdog registers
2d24a3a7 52 */
49822e23 53#define MX1_WCR __REG(0x00201000) /* Watchdog Control Register */
2d24a3a7 54#define MX1_WSR __REG(0x00201004) /* Watchdog Service Register */
49822e23 55#define MX1_WSTR __REG(0x00201008) /* Watchdog Status Register */
2d24a3a7
WD		 56
57/*
58 * MX1 Timer registers
59 */
49822e23
WD		 60#define MX1_TCTL1 __REG(0x00202000) /* Timer 1 Control Register */
61#define MX1_TPRER1 __REG(0x00202004) /* Timer 1 Prescaler Register */
62#define MX1_TCMP1 __REG(0x00202008) /* Timer 1 Compare Register */
63#define MX1_TCR1 __REG(0x0020200C) /* Timer 1 Capture Register */
64#define MX1_TCN1 __REG(0x00202010) /* Timer 1 Counter Register */
65#define MX1_TSTAT1 __REG(0x00202014) /* Timer 1 Status Register */
66
67#define MX1_TCTL2 __REG(0x00203000) /* Timer 2 Control Register */
68#define MX1_TPRER2 __REG(0x00203004) /* Timer 2 Prescaler Register */
69#define MX1_TCMP2 __REG(0x00203008) /* Timer 2 Compare Register */
70#define MX1_TCR2 __REG(0x0020300C) /* Timer 2 Capture Register */
71#define MX1_TCN2 __REG(0x00203010) /* Timer 2 Counter Register */
72#define MX1_TSTAT2 __REG(0x00203014) /* Timer 2 Status Register */
2d24a3a7
WD		 73
74/*
75 * MX1 RTC registers
76 */
49822e23
WD		 77#define MX1_HOURMIN __REG(0x00204000) /* RTC Hour & Min Counter Registers */
78#define MX1_SECONDS __REG(0x00204004) /* RTC Seconds Counter Registers */
79#define MX1_ALRM_HM __REG(0x00204008) /* RTC Hour & Min Alarm Registers */
80#define MX1_ALRM_SEC __REG(0x0020400C) /* RTC Seconds Alarm Registers */
81#define MX1_RCCTL __REG(0x00204010) /* RTC Control Registers */
82#define MX1_RTCISR __REG(0x00204014) /* RTC Interrupt Status Registers */
83#define MX1_RTCIENR __REG(0x00204018) /* RTC Interrupt Enable Registers */
84#define MX1_STPWCH __REG(0x0020401C) /* RTC Stopwatch Minutes Registers */
85#define MX1_DAYR __REG(0x00204020) /* RTC Days Counter Registers */
86#define MX1_DAYALARM __REG(0x00204020) /* RTC Day Alarm Registers */
2d24a3a7
WD		 87
88/*
89 * MX1 LCD Controller registers
90 */
49822e23
WD		 91#define MX1_SSA __REG(0x00205000) /* Screen Start Address Register */
92#define MX1_SIZE __REG(0x00205004) /* Size Register */
93#define MX1_VPW __REG(0x00205008) /* Virtual Page Width Register */
94#define MX1_CPOS __REG(0x0020500C) /* LCD Cursor Position Register */
95#define MX1_LCWHB __REG(0x00205010) /* LCD Cursor Width Height & Blink Register */
2d24a3a7 96#define MX1_LCHCC __REG(0x00205014) /* LCD Color Cursor Mapping Register */
49822e23
WD		 97#define MX1_PCR __REG(0x00205018) /* LCD Panel Configuration Register */
98#define MX1_HCR __REG(0x0020501C) /* Horizontal Configuration Register */
99#define MX1_VCR __REG(0x00205020) /* Vertical Configuration Register */
100#define MX1_POS __REG(0x00205024) /* Panning Offset Register */
101#define MX1_LGPMR __REG(0x00205028) /* LCD Gray Palette Mapping Register */
102#define MX1_PWMR __REG(0x0020502C) /* PWM Contrast Control Register */
103#define MX1_DMACR __REG(0x00205030) /* DMA Control Register */
104#define MX1_RMCR __REG(0x00205034) /* Refresh Mode Control Register */
105#define MX1_LCDICR __REG(0x00205038) /* Interrupt Configuration Register */
106#define MX1_LCDISR __REG(0x00205040) /* Interrupt Status Register */
2d24a3a7
WD		 107
108/*
109 * MX1 UART registers
110 */
111
112/* UART 1 */
49822e23
WD		 113#define MX1_URX0D_1 __REG(0x00206000) /* UART 1 Receiver Register 0 */
114#define MX1_URX1D_1 __REG(0x00206004) /* UART 1 Receiver Register 1 */
115#define MX1_URX2D_1 __REG(0x00206008) /* UART 1 Receiver Register 2 */
116#define MX1_URX3D_1 __REG(0x0020600C) /* UART 1 Receiver Register 3 */
117#define MX1_URX4D_1 __REG(0x00206010) /* UART 1 Receiver Register 4 */
118#define MX1_URX5D_1 __REG(0x00206014) /* UART 1 Receiver Register 5 */
119#define MX1_URX6D_1 __REG(0x00206018) /* UART 1 Receiver Register 6 */
120#define MX1_URX7D_1 __REG(0x0020601C) /* UART 1 Receiver Register 7 */
121#define MX1_URX8D_1 __REG(0x00206020) /* UART 1 Receiver Register 8 */
122#define MX1_URX9D_1 __REG(0x00206024) /* UART 1 Receiver Register 9 */
123#define MX1_URX10D_1 __REG(0x00206028) /* UART 1 Receiver Register 10 */
124#define MX1_URX11D_1 __REG(0x0020602C) /* UART 1 Receiver Register 11 */
2d24a3a7
WD		 125#define MX1_URX12D_1 __REG(0x00206030) /* UART 1 Receiver Register 12 */
126#define MX1_URX13D_1 __REG(0x00206034) /* UART 1 Receiver Register 13 */
49822e23 127#define MX1_URX14D_1 __REG(0x00206038) /* UART 1 Receiver Register 14 */
2d24a3a7
WD		 128#define MX1_URX15D_1 __REG(0x0020603c) /* UART 1 Receiver Register 15 */
129
49822e23
WD		 130#define MX1_UTX0D_1 __REG(0x00206040) /* UART 1 Transmitter Register 0 */
131#define MX1_UTX1D_1 __REG(0x00206044) /* UART 1 Transmitter Register 1 */
132#define MX1_UTX2D_1 __REG(0x00206048) /* UART 1 Transmitter Register 2 */
133#define MX1_UTX3D_1 __REG(0x0020604C) /* UART 1 Transmitter Register 3 */
134#define MX1_UTX4D_1 __REG(0x00206050) /* UART 1 Transmitter Register 4 */
135#define MX1_UTX5D_1 __REG(0x00206054) /* UART 1 Transmitter Register 5 */
136#define MX1_UTX6D_1 __REG(0x00206058) /* UART 1 Transmitter Register 6 */
137#define MX1_UTX7D_1 __REG(0x0020605C) /* UART 1 Transmitter Register 7 */
138#define MX1_UTX8D_1 __REG(0x00206060) /* UART 1 Transmitter Register 8 */
139#define MX1_UTX9D_1 __REG(0x00206064) /* UART 1 Transmitter Register 9 */
140#define MX1_UTX10D_1 __REG(0x00206068) /* UART 1 Transmitter Register 10 */
141#define MX1_UTX11D_1 __REG(0x0020606C) /* UART 1 Transmitter Register 11 */
2d24a3a7
WD		 142#define MX1_UTX12D_1 __REG(0x00206060) /* UART 1 Transmitter Register 12 */
143#define MX1_UTX13D_1 __REG(0x00206074) /* UART 1 Transmitter Register 13 */
49822e23 144#define MX1_UTX14D_1 __REG(0x00206078) /* UART 1 Transmitter Register 14 */
2d24a3a7
WD		 145#define MX1_UTX15D_1 __REG(0x0020607c) /* UART 1 Transmitter Register 15 */
146
147#define MX1_UCR1_1 __REG(0x00206080) /* UART 1 Control Register 1 */
148#define MX1_UCR2_1 __REG(0x00206084) /* UART 1 Control Register 2 */
149#define MX1_UCR3_1 __REG(0x00206088) /* UART 1 Control Register 3 */
150#define MX1_UCR4_1 __REG(0x0020608C) /* UART 1 Control Register 4 */
49822e23 151#define MX1_UFCR_1 __REG(0x00206090) /* UART 1 FIFO Control Register */
2d24a3a7
WD		 152#define MX1_USR1_1 __REG(0x00206094) /* UART 1 Status Register 1 */
153#define MX1_USR2_1 __REG(0x00206098) /* UART 1 Status Register 2 */
49822e23
WD		 154#define MX1_UESC_1 __REG(0x0020609C) /* UART 1 Escape Character Register */
155#define MX1_UTIM_1 __REG(0x002060A0) /* UART 1 Escape Timer Register */
156#define MX1_UBIR_1 __REG(0x002060A4) /* UART 1 BRM Incremental Register */
157#define MX1_UBMR_1 __REG(0x002060A8) /* UART 1 BRM Modulator Register */
158#define MX1_UBRC_1 __REG(0x002060AC) /* UART 1 Baud Rate Count Register */
2d24a3a7
WD		 159#define MX1_BIPR1_1 __REG(0x002060B0) /* UART 1 BRM Incremental Preset Register 1 */
160#define MX1_BIPR2_1 __REG(0x002060B4) /* UART 1 BRM Incremental Preset Register 2 */
161#define MX1_BIPR3_1 __REG(0x002060B8) /* UART 1 BRM Incremental Preset Register 3 */
162#define MX1_BIPR4_1 __REG(0x002060BC) /* UART 1 BRM Incremental Preset Register 4 */
163#define MX1_BMPR1_1 __REG(0x002060C0) /* UART 1 BRM Modulator Preset Register 1 */
164#define MX1_BMPR2_1 __REG(0x002060C4) /* UART 1 BRM Modulator Preset Register 2 */
165#define MX1_BMPR3_1 __REG(0x002060C8) /* UART 1 BRM Modulator Preset Register 3 */
166#define MX1_BMPR4_1 __REG(0x002060CC) /* UART 1 BRM Modulator Preset Register 4 */
49822e23 167#define MX1_UTS_1 __REG(0x002060D0) /* UART 1 Test Register 1 */
2d24a3a7
WD		 168
169/* UART 2 */
49822e23
WD		 170#define MX1_URX0D_2 __REG(0x00207000) /* UART 2 Receiver Register 0 */
171#define MX1_URX1D_2 __REG(0x00207004) /* UART 2 Receiver Register 1 */
172#define MX1_URX2D_2 __REG(0x00207008) /* UART 2 Receiver Register 2 */
173#define MX1_URX3D_2 __REG(0x0020700C) /* UART 2 Receiver Register 3 */
174#define MX1_URX4D_2 __REG(0x00207010) /* UART 2 Receiver Register 4 */
175#define MX1_URX5D_2 __REG(0x00207014) /* UART 2 Receiver Register 5 */
176#define MX1_URX6D_2 __REG(0x00207018) /* UART 2 Receiver Register 6 */
177#define MX1_URX7D_2 __REG(0x0020701C) /* UART 2 Receiver Register 7 */
178#define MX1_URX8D_2 __REG(0x00207020) /* UART 2 Receiver Register 8 */
179#define MX1_URX9D_2 __REG(0x00207024) /* UART 2 Receiver Register 9 */
180#define MX1_URX10D_2 __REG(0x00207028) /* UART 2 Receiver Register 10 */
181#define MX1_URX11D_2 __REG(0x0020702C) /* UART 2 Receiver Register 11 */
2d24a3a7
WD		 182#define MX1_URX12D_2 __REG(0x00207030) /* UART 2 Receiver Register 12 */
183#define MX1_URX13D_2 __REG(0x00207034) /* UART 2 Receiver Register 13 */
49822e23 184#define MX1_URX14D_2 __REG(0x00207038) /* UART 2 Receiver Register 14 */
2d24a3a7
WD		 185#define MX1_URX15D_2 __REG(0x0020703c) /* UART 2 Receiver Register 15 */
186
49822e23
WD		 187#define MX1_UTX0D_2 __REG(0x00207040) /* UART 2 Transmitter Register 0 */
188#define MX1_UTX1D_2 __REG(0x00207044) /* UART 2 Transmitter Register 1 */
189#define MX1_UTX2D_2 __REG(0x00207048) /* UART 2 Transmitter Register 2 */
190#define MX1_UTX3D_2 __REG(0x0020704C) /* UART 2 Transmitter Register 3 */
191#define MX1_UTX4D_2 __REG(0x00207050) /* UART 2 Transmitter Register 4 */
192#define MX1_UTX5D_2 __REG(0x00207054) /* UART 2 Transmitter Register 5 */
193#define MX1_UTX6D_2 __REG(0x00207058) /* UART 2 Transmitter Register 6 */
194#define MX1_UTX7D_2 __REG(0x0020705C) /* UART 2 Transmitter Register 7 */
195#define MX1_UTX8D_2 __REG(0x00207060) /* UART 2 Transmitter Register 8 */
196#define MX1_UTX9D_2 __REG(0x00207064) /* UART 2 Transmitter Register 9 */
197#define MX1_UTX10D_2 __REG(0x00207068) /* UART 2 Transmitter Register 10 */
198#define MX1_UTX11D_2 __REG(0x0020706C) /* UART 2 Transmitter Register 11 */
2d24a3a7
WD		 199#define MX1_UTX12D_2 __REG(0x00207060) /* UART 2 Transmitter Register 12 */
200#define MX1_UTX13D_2 __REG(0x00207074) /* UART 2 Transmitter Register 13 */
49822e23 201#define MX1_UTX14D_2 __REG(0x00207078) /* UART 2 Transmitter Register 14 */
2d24a3a7
WD		 202#define MX1_UTX15D_2 __REG(0x0020707c) /* UART 2 Transmitter Register 15 */
203
204#define MX1_UCR1_2 __REG(0x00207080) /* UART 2 Control Register 1 */
205#define MX1_UCR2_2 __REG(0x00207084) /* UART 2 Control Register 2 */
206#define MX1_UCR3_2 __REG(0x00207088) /* UART 2 Control Register 3 */
207#define MX1_UCR4_2 __REG(0x0020708C) /* UART 2 Control Register 4 */
49822e23 208#define MX1_UFCR_2 __REG(0x00207090) /* UART 2 FIFO Control Register */
2d24a3a7
WD		 209#define MX1_USR1_2 __REG(0x00207094) /* UART 2 Status Register 1 */
210#define MX1_USR2_2 __REG(0x00207098) /* UART 2 Status Register 2 */
49822e23
WD		 211#define MX1_UESC_2 __REG(0x0020709C) /* UART 2 Escape Character Register */
212#define MX1_UTIM_2 __REG(0x002070A0) /* UART 2 Escape Timer Register */
213#define MX1_UBIR_2 __REG(0x002070A4) /* UART 2 BRM Incremental Register */
214#define MX1_UBMR_2 __REG(0x002070A8) /* UART 2 BRM Modulator Register */
215#define MX1_UBRC_2 __REG(0x002070AC) /* UART 2 Baud Rate Count Register */
2d24a3a7
WD		 216#define MX1_BIPR1_2 __REG(0x002070B0) /* UART 2 BRM Incremental Preset Register 1 */
217#define MX1_BIPR2_2 __REG(0x002070B4) /* UART 2 BRM Incremental Preset Register 2 */
218#define MX1_BIPR3_2 __REG(0x002070B8) /* UART 2 BRM Incremental Preset Register 3 */
219#define MX1_BIPR4_2 __REG(0x002070BC) /* UART 2 BRM Incremental Preset Register 4 */
220#define MX1_BMPR1_2 __REG(0x002070C0) /* UART 2 BRM Modulator Preset Register 1 */
221#define MX1_BMPR2_2 __REG(0x002070C4) /* UART 2 BRM Modulator Preset Register 2 */
222#define MX1_BMPR3_2 __REG(0x002070C8) /* UART 2 BRM Modulator Preset Register 3 */
223#define MX1_BMPR4_2 __REG(0x002070CC) /* UART 2 BRM Modulator Preset Register 4 */
49822e23 224#define MX1_UTS_2 __REG(0x002070D0) /* UART 2 Test Register 1 */
2d24a3a7
WD		 225
226/*
227 * MX1 PWM registers
228 */
49822e23
WD		 229#define MX1_PWMC __REG(0x00208000) /* PWM Control Register */
230#define MX1_PWMS __REG(0x00208004) /* PWM Sample Register */
231#define MX1_PWMP __REG(0x00208008) /* PWM Period Register */
232#define MX1_PWMCNT __REG(0x0020800C) /* PWM Counter Register */
2d24a3a7
WD		 233
234/*
235 * MX1 DMAC registers
236 */
49822e23
WD		 237#define MX1_DCR __REG(0x00209000) /* DMA Control Register */
238#define MX1_DISR __REG(0x00209004) /* DMA Interrupt Status Register */
239#define MX1_DIMR __REG(0x00209008) /* DMA Interrupt Mask Register */
240#define MX1_DBTOSR __REG(0x0020900C) /* DMA Burst Time-Out Status Register */
241#define MX1_DRTOSR __REG(0x00209010) /* DMA Request Time-Out Status Register */
242#define MX1_DSESR __REG(0x00209014) /* DMA Request Time-Out Status Register */
243#define MX1_DBOSR __REG(0x00209018) /* DMA Buffer Overflow Status Register */
244#define MX1_DBTOCR __REG(0x0020901C) /* DMA Burst Time-Out Control Register */
245
246#define MX1_WSRA __REG(0x00209040) /* DMA W-Size Register A */
247#define MX1_XSRA __REG(0x00209044) /* DMA X-Size Register A */
248#define MX1_YSRA __REG(0x00209048) /* DMA Y-Size Register A */
249
250#define MX1_WSRB __REG(0x0020904C) /* DMA W-Size Register B */
251#define MX1_XSRB __REG(0x00209050) /* DMA X-Size Register B */
252#define MX1_YSRB __REG(0x00209054) /* DMA Y-Size Register B */
2d24a3a7
WD		 253
254/* Channel 0 */
255
256#define MX1_SAR0 __REG(0x00209080) /* Channel 0 Source Address Register */
49822e23
WD		 257#define MX1_DAR0 __REG(0x00209084) /* Channel 0 Destination Address Register */
258#define MX1_CNTR0 __REG(0x00209088) /* Channel 0 Count Register */
259#define MX1_CCR0 __REG(0x0020908C) /* Channel 0 Control Register */
260#define MX1_RSSR0 __REG(0x00209090) /* Channel 0 Request Source Select Register */
261#define MX1_BLR0 __REG(0x00209094) /* Channel 0 Burst Length Register */
262#define MX1_RTOR0 __REG(0x00209098) /* Channel 0 Request Time-Out Register */
263#define MX1_BUCR0 __REG(0x00209098) /* Channel 0 Bus Utilization Control Register */
2d24a3a7
WD		 264
265/* Channel 1 */
266
267#define MX1_SAR1 __REG(0x002090C0) /* Channel 1 Source Address Register */
49822e23
WD		 268#define MX1_DAR1 __REG(0x002090C4) /* Channel 1 Destination Address Register */
269#define MX1_CNTR1 __REG(0x002090C8) /* Channel 1 Count Register */
270#define MX1_CCR1 __REG(0x002090CC) /* Channel 1 Control Register */
271#define MX1_RSSR1 __REG(0x002090D0) /* Channel 1 Request Source Select Register */
272#define MX1_BLR1 __REG(0x002090D4) /* Channel 1 Burst Length Register */
273#define MX1_RTOR1 __REG(0x002090D8) /* Channel 1 Request Time-Out Register */
274#define MX1_BUCR1 __REG(0x002090D8) /* Channel 1 Bus Utilization Control Register */
2d24a3a7
WD		 275
276/* Channel 2 */
277
278#define MX1_SAR2 __REG(0x00209100) /* Channel 2 Source Address Register */
49822e23
WD		 279#define MX1_DAR2 __REG(0x00209104) /* Channel 2 Destination Address Register */
280#define MX1_CNTR2 __REG(0x00209108) /* Channel 2 Count Register */
281#define MX1_CCR2 __REG(0x0020910C) /* Channel 2 Control Register */
282#define MX1_RSSR2 __REG(0x00209110) /* Channel 2 Request Source Select Register */
283#define MX1_BLR2 __REG(0x00209114) /* Channel 2 Burst Length Register */
284#define MX1_RTOR2 __REG(0x00209118) /* Channel 2 Request Time-Out Register */
285#define MX1_BUCR2 __REG(0x00209118) /* Channel 2 Bus Utilization Control Register */
2d24a3a7
WD		 286
287/* Channel 3 */
288
289#define MX1_SAR3 __REG(0x00209140) /* Channel 3 Source Address Register */
49822e23
WD		 290#define MX1_DAR3 __REG(0x00209144) /* Channel 3 Destination Address Register */
291#define MX1_CNTR3 __REG(0x00209148) /* Channel 3 Count Register */
292#define MX1_CCR3 __REG(0x0020914C) /* Channel 3 Control Register */
293#define MX1_RSSR3 __REG(0x00209150) /* Channel 3 Request Source Select Register */
294#define MX1_BLR3 __REG(0x00209154) /* Channel 3 Burst Length Register */
295#define MX1_RTOR3 __REG(0x00209158) /* Channel 3 Request Time-Out Register */
296#define MX1_BUCR3 __REG(0x00209158) /* Channel 3 Bus Utilization Control Register */
2d24a3a7
WD		 297
298/* Channel 4 */
299
300#define MX1_SAR4 __REG(0x00209180) /* Channel 4 Source Address Register */
49822e23
WD		 301#define MX1_DAR4 __REG(0x00209184) /* Channel 4 Destination Address Register */
302#define MX1_CNTR4 __REG(0x00209188) /* Channel 4 Count Register */
303#define MX1_CCR4 __REG(0x0020918C) /* Channel 4 Control Register */
304#define MX1_RSSR4 __REG(0x00209190) /* Channel 4 Request Source Select Register */
305#define MX1_BLR4 __REG(0x00209194) /* Channel 4 Burst Length Register */
306#define MX1_RTOR4 __REG(0x00209198) /* Channel 4 Request Time-Out Register */
307#define MX1_BUCR4 __REG(0x00209198) /* Channel 4 Bus Utilization Control Register */
2d24a3a7
WD		 308
309/* Channel 5 */
310
311#define MX1_SAR5 __REG(0x002091C0) /* Channel 5 Source Address Register */
49822e23
WD		 312#define MX1_DAR5 __REG(0x002091C4) /* Channel 5 Destination Address Register */
313#define MX1_CNTR5 __REG(0x002091C8) /* Channel 5 Count Register */
314#define MX1_CCR5 __REG(0x002091CC) /* Channel 5 Control Register */
315#define MX1_RSSR5 __REG(0x002091D0) /* Channel 5 Request Source Select Register */
316#define MX1_BLR5 __REG(0x002091D4) /* Channel 5 Burst Length Register */
317#define MX1_RTOR5 __REG(0x002091D8) /* Channel 5 Request Time-Out Register */
318#define MX1_BUCR5 __REG(0x002091D8) /* Channel 5 Bus Utilization Control Register */
2d24a3a7
WD		 319
320/* Channel 6 */
321
322#define MX1_SAR6 __REG(0x00209200) /* Channel 6 Source Address Register */
49822e23
WD		 323#define MX1_DAR6 __REG(0x00209204) /* Channel 6 Destination Address Register */
324#define MX1_CNTR6 __REG(0x00209208) /* Channel 6 Count Register */
325#define MX1_CCR6 __REG(0x0020920C) /* Channel 6 Control Register */
326#define MX1_RSSR6 __REG(0x00209210) /* Channel 6 Request Source Select Register */
327#define MX1_BLR6 __REG(0x00209214) /* Channel 6 Burst Length Register */
328#define MX1_RTOR6 __REG(0x00209218) /* Channel 6 Request Time-Out Register */
329#define MX1_BUCR6 __REG(0x00209218) /* Channel 6 Bus Utilization Control Register */
2d24a3a7
WD		 330
331/* Channel 7 */
332
333#define MX1_SAR7 __REG(0x00209240) /* Channel 7 Source Address Register */
49822e23
WD		 334#define MX1_DAR7 __REG(0x00209244) /* Channel 7 Destination Address Register */
335#define MX1_CNTR7 __REG(0x00209248) /* Channel 7 Count Register */
336#define MX1_CCR7 __REG(0x0020924C) /* Channel 7 Control Register */
337#define MX1_RSSR7 __REG(0x00209250) /* Channel 7 Request Source Select Register */
338#define MX1_BLR7 __REG(0x00209254) /* Channel 7 Burst Length Register */
339#define MX1_RTOR7 __REG(0x00209258) /* Channel 7 Request Time-Out Register */
340#define MX1_BUCR7 __REG(0x00209258) /* Channel 7 Bus Utilization Control Register */
2d24a3a7
WD		 341
342/* Channel 8 */
343
344#define MX1_SAR8 __REG(0x00209280) /* Channel 8 Source Address Register */
49822e23
WD		 345#define MX1_DAR8 __REG(0x00209284) /* Channel 8 Destination Address Register */
346#define MX1_CNTR8 __REG(0x00209288) /* Channel 8 Count Register */
347#define MX1_CCR8 __REG(0x0020928C) /* Channel 8 Control Register */
348#define MX1_RSSR8 __REG(0x00209290) /* Channel 8 Request Source Select Register */
349#define MX1_BLR8 __REG(0x00209294) /* Channel 8 Burst Length Register */
350#define MX1_RTOR8 __REG(0x00209298) /* Channel 8 Request Time-Out Register */
351#define MX1_BUCR8 __REG(0x00209298) /* Channel 8 Bus Utilization Control Register */
2d24a3a7
WD		 352
353/* Channel 9 */
354
355#define MX1_SAR9 __REG(0x002092C0) /* Channel 9 Source Address Register */
49822e23
WD		 356#define MX1_DAR9 __REG(0x002092C4) /* Channel 9 Destination Address Register */
357#define MX1_CNTR9 __REG(0x002092C8) /* Channel 9 Count Register */
358#define MX1_CCR9 __REG(0x002092CC) /* Channel 9 Control Register */
359#define MX1_RSSR9 __REG(0x002092D0) /* Channel 9 Request Source Select Register */
360#define MX1_BLR9 __REG(0x002092D4) /* Channel 9 Burst Length Register */
361#define MX1_RTOR9 __REG(0x002092D8) /* Channel 9 Request Time-Out Register */
362#define MX1_BUCR9 __REG(0x002092D8) /* Channel 9 Bus Utilization Control Register */
2d24a3a7
WD		 363
364/* Channel 10 */
365
366#define MX1_SAR10 __REG(0x00209300) /* Channel 10 Source Address Register */
49822e23
WD		 367#define MX1_DAR10 __REG(0x00209304) /* Channel 10 Destination Address Register */
368#define MX1_CNTR10 __REG(0x00209308) /* Channel 10 Count Register */
369#define MX1_CCR10 __REG(0x0020930C) /* Channel 10 Control Register */
370#define MX1_RSSR10 __REG(0x00209310) /* Channel 10 Request Source Select Register */
371#define MX1_BLR10 __REG(0x00209314) /* Channel 10 Burst Length Register */
372#define MX1_RTOR10 __REG(0x00209318) /* Channel 10 Request Time-Out Register */
373#define MX1_BUCR10 __REG(0x00209318) /* Channel 10 Bus Utilization Control Register */
374
375#define MX1_TCR __REG(0x00209340) /* Test Control Register */
376#define MX1_TFIFOAR __REG(0x00209344) /* Test FIFO A Register */
377#define MX1_TDRR __REG(0x00209348) /* Test DMA Request Register */
378#define MX1_TDIPR __REG(0x0020934C) /* Test DMA In Progress Register */
379#define MX1_TFIFOBR __REG(0x00209350) /* Test FIFO B Register */
2d24a3a7
WD		 380
381/*
382 * MX1 SIM registers
383 */
384
49822e23
WD		 385#define MX1_PORT_CNTL __REG(0x00211000) /* Port Control Register */
386#define MX1_CNTL __REG(0x00211004) /* Control Register */
387#define MX1_RCV_THRESHOLD __REG(0x00211008)/* Receive Threshold Register */
388#define MX1_ENABLE __REG(0x0021100C) /* Transmit/Receive Enable Register */
389#define MX1_XMT_STATUS __REG(0x00211010) /* Transmit Status Register */
390#define MX1_RCV_STATUS __REG(0x00211014) /* Receive Status Register */
391#define MX1_SIM_INT_MASK __REG(0x00211018) /* Interrupt Mask Register */
392#define MX1_XMT_BUF __REG(0x0021101C) /* Port Transmit Buffer Register */
393#define MX1_RCV_BUF __REG(0x00211020) /* Receive Buffer Register */
2d24a3a7
WD		 394#define MX1_PORT_DETECT __REG(0x00211024) /* Detect Register */
395#define MX1_XMT_THRESHOLD __REG(0x00211028)/* Transmit Threshold Register */
49822e23
WD		 396#define MX1_GUARD_CNTL __REG(0x0021102C) /* Transmit Guard Control Register */
397#define MX1_OD_CONFIG __REG(0x00211030) /* Open-Drain Configuration Control Register */
2d24a3a7
WD		 398#define MX1_RESET_CNTL __REG(0x00211034) /* Reset Control Register */
399#define MX1_CHAR_WAIT __REG(0x00211038) /* Charactor Wait Timer Register */
49822e23 400#define MX1_GPCNT __REG(0x0021103C) /* General Purpose Counter Register */
2d24a3a7
WD		 401#define MX1_DIVISOR __REG(0x00211040) /* Divisor Register */
402
2d24a3a7
WD		 403/*
404 * MX1 USBD registers
405 */
406
49822e23
WD		 407#define MX1_USB_FRAME __REG(0x00212000) /* USB Frame Number and Match Register */
408#define MX1_USB_SPEC __REG(0x00212004) /* USB Spec & Release Number Register */
409#define MX1_USB_STAT __REG(0x00212008) /* USB Status Register */
410#define MX1_USB_CTRL __REG(0x0021200C) /* USB Control Register */
411#define MX1_USB_DADR __REG(0x00212010) /* USB Descriptor RAM Address Register */
2d24a3a7 412#define MX1_USB_DDAT __REG(0x00212014) /* USB Descriptor RAM/Endpoint buffer Data Register */
49822e23
WD		 413#define MX1_USB_INTR __REG(0x00212018) /* USB Interrupt Status Register */
414#define MX1_USB_MASK __REG(0x0021201C) /* USB Interrupt Mask Register */
415#define MX1_USB_ENAB __REG(0x00212024) /* USB Enable Register */
2d24a3a7
WD		 416
417/* Endpoint 0 */
418#define MX1_USB_EP0_STAT __REG(0x00212030) /* Endpoint 0 Status/Control Register */
419#define MX1_USB_EP0_INTR __REG(0x00212034) /* Endpoint 0 Interrupt Status Register */
49822e23 420#define MX1_USB_EP0_MASK __REG(0x00212038) /* Endpoint 0 Interrupt Mask Register */
2d24a3a7
WD		 421#define MX1_USB_EP0_FDAT __REG(0x0021203C) /* Endpoint 0 FIFO Data Register */
422#define MX1_USB_EP0_FSTAT __REG(0x00212040) /* Endpoint 0 FIFO Status Register */
49822e23 423#define MX1_USB_EP0_FCTRL __REG(0x00212044) /* Endpoint 0 FIFO Control Register */
2d24a3a7
WD		 424#define MX1_USB_EP0_LRFP __REG(0x00212048) /* Endpoint 0 Last Read Frame Pointer Register */
425#define MX1_USB_EP0_LWFP __REG(0x0021204C) /* Endpoint 0 Last Write Frame Pointer Register */
426#define MX1_USB_EP0_FALRM __REG(0x00212050) /* Endpoint 0 FIFO Alarm Register */
427#define MX1_USB_EP0_FRDP __REG(0x00212054) /* Endpoint 0 FIFO Read Pointer Register */
428#define MX1_USB_EP0_FWRP __REG(0x00212058) /* Endpoint 0 FIFO Write Pointer Register */
429
2d24a3a7
WD		 430/* Endpoint 1 */
431#define MX1_USB_EP1_STAT __REG(0x00212060) /* Endpoint 1 Status/Control Register */
432#define MX1_USB_EP1_INTR __REG(0x00212064) /* Endpoint 1 Interrupt Status Register */
49822e23 433#define MX1_USB_EP1_MASK __REG(0x00212068) /* Endpoint 1 Interrupt Mask Register */
2d24a3a7
WD		 434#define MX1_USB_EP1_FDAT __REG(0x0021206C) /* Endpoint 1 FIFO Data Register */
435#define MX1_USB_EP1_FSTAT __REG(0x00212070) /* Endpoint 1 FIFO Status Register */
49822e23 436#define MX1_USB_EP1_FCTRL __REG(0x00212074) /* Endpoint 1 FIFO Control Register */
2d24a3a7
WD		 437#define MX1_USB_EP1_LRFP __REG(0x00212078) /* Endpoint 1 Last Read Frame Pointer Register */
438#define MX1_USB_EP1_LWFP __REG(0x0021207C) /* Endpoint 1 Last Write Frame Pointer Register */
439#define MX1_USB_EP1_FALRM __REG(0x00212080) /* Endpoint 1 FIFO Alarm Register */
440#define MX1_USB_EP1_FRDP __REG(0x00212084) /* Endpoint 1 FIFO Read Pointer Register */
441#define MX1_USB_EP1_FWRP __REG(0x00212088) /* Endpoint 1 FIFO Write Pointer Register */
442
2d24a3a7
WD		 443/* Endpoint 2 */
444#define MX1_USB_EP2_STAT __REG(0x00212090) /* Endpoint 2 Status/Control Register */
445#define MX1_USB_EP2_INTR __REG(0x00212094) /* Endpoint 2 Interrupt Status Register */
49822e23 446#define MX1_USB_EP2_MASK __REG(0x00212098) /* Endpoint 2 Interrupt Mask Register */
2d24a3a7
WD		 447#define MX1_USB_EP2_FDAT __REG(0x0021209C) /* Endpoint 2 FIFO Data Register */
448#define MX1_USB_EP2_FSTAT __REG(0x002120A0) /* Endpoint 2 FIFO Status Register */
49822e23 449#define MX1_USB_EP2_FCTRL __REG(0x002120A4) /* Endpoint 2 FIFO Control Register */
2d24a3a7
WD		 450#define MX1_USB_EP2_LRFP __REG(0x002120A8) /* Endpoint 2 Last Read Frame Pointer Register */
451#define MX1_USB_EP2_LWFP __REG(0x002120AC) /* Endpoint 2 Last Write Frame Pointer Register */
452#define MX1_USB_EP2_FALRM __REG(0x002120B0) /* Endpoint 2 FIFO Alarm Register */
453#define MX1_USB_EP2_FRDP __REG(0x002120B4) /* Endpoint 2 FIFO Read Pointer Register */
454#define MX1_USB_EP2_FWRP __REG(0x002120B8) /* Endpoint 2 FIFO Write Pointer Register */
455
2d24a3a7
WD		 456/* Endpoint 3 */
457#define MX1_USB_EP3_STAT __REG(0x002120C0) /* Endpoint 3 Status/Control Register */
458#define MX1_USB_EP3_INTR __REG(0x002120C4) /* Endpoint 3 Interrupt Status Register */
49822e23 459#define MX1_USB_EP3_MASK __REG(0x002120C8) /* Endpoint 3 Interrupt Mask Register */
2d24a3a7
WD		 460#define MX1_USB_EP3_FDAT __REG(0x002120CC) /* Endpoint 3 FIFO Data Register */
461#define MX1_USB_EP3_FSTAT __REG(0x002120D0) /* Endpoint 3 FIFO Status Register */
49822e23 462#define MX1_USB_EP3_FCTRL __REG(0x002120D4) /* Endpoint 3 FIFO Control Register */
2d24a3a7
WD		 463#define MX1_USB_EP3_LRFP __REG(0x002120D8) /* Endpoint 3 Last Read Frame Pointer Register */
464#define MX1_USB_EP3_LWFP __REG(0x002120DC) /* Endpoint 3 Last Write Frame Pointer Register */
465#define MX1_USB_EP3_FALRM __REG(0x002120E0) /* Endpoint 3 FIFO Alarm Register */
466#define MX1_USB_EP3_FRDP __REG(0x002120E4) /* Endpoint 3 FIFO Read Pointer Register */
467#define MX1_USB_EP3_FWRP __REG(0x002120E8) /* Endpoint 3 FIFO Write Pointer Register */
468
2d24a3a7
WD		 469/* Endpoint 4 */
470#define MX1_USB_EP4_STAT __REG(0x002120F0) /* Endpoint 4 Status/Control Register */
471#define MX1_USB_EP4_INTR __REG(0x002120F4) /* Endpoint 4 Interrupt Status Register */
49822e23 472#define MX1_USB_EP4_MASK __REG(0x002120F8) /* Endpoint 4 Interrupt Mask Register */
2d24a3a7
WD		 473#define MX1_USB_EP4_FDAT __REG(0x002120FC) /* Endpoint 4 FIFO Data Register */
474#define MX1_USB_EP4_FSTAT __REG(0x00212100) /* Endpoint 4 FIFO Status Register */
49822e23 475#define MX1_USB_EP4_FCTRL __REG(0x00212104) /* Endpoint 4 FIFO Control Register */
2d24a3a7
WD		 476#define MX1_USB_EP4_LRFP __REG(0x00212108) /* Endpoint 4 Last Read Frame Pointer Register */
477#define MX1_USB_EP4_LWFP __REG(0x0021210C) /* Endpoint 4 Last Write Frame Pointer Register */
478#define MX1_USB_EP4_FALRM __REG(0x00212110) /* Endpoint 4 FIFO Alarm Register */
479#define MX1_USB_EP4_FRDP __REG(0x00212114) /* Endpoint 4 FIFO Read Pointer Register */
480#define MX1_USB_EP4_FWRP __REG(0x00212118) /* Endpoint 4 FIFO Write Pointer Register */
481
2d24a3a7
WD		 482/* Endpoint 5 */
483#define MX1_USB_EP5_STAT __REG(0x00212120) /* Endpoint 5 Status/Control Register */
484#define MX1_USB_EP5_INTR __REG(0x00212124) /* Endpoint 5 Interrupt Status Register */
49822e23 485#define MX1_USB_EP5_MASK __REG(0x00212128) /* Endpoint 5 Interrupt Mask Register */
2d24a3a7
WD		 486#define MX1_USB_EP5_FDAT __REG(0x0021212C) /* Endpoint 5 FIFO Data Register */
487#define MX1_USB_EP5_FSTAT __REG(0x00212130) /* Endpoint 5 FIFO Status Register */
49822e23 488#define MX1_USB_EP5_FCTRL __REG(0x00212134) /* Endpoint 5 FIFO Control Register */
2d24a3a7
WD		 489#define MX1_USB_EP5_LRFP __REG(0x00212138) /* Endpoint 5 Last Read Frame Pointer Register */
490#define MX1_USB_EP5_LWFP __REG(0x0021213C) /* Endpoint 5 Last Write Frame Pointer Register */
491#define MX1_USB_EP5_FALRM __REG(0x00212140) /* Endpoint 5 FIFO Alarm Register */
492#define MX1_USB_EP5_FRDP __REG(0x00212144) /* Endpoint 5 FIFO Read Pointer Register */
493#define MX1_USB_EP5_FWRP __REG(0x00212148) /* Endpoint 5 FIFO Write Pointer Register */
494
2d24a3a7
WD		 495/*
496 * MX1 SPI 1 registers
497 */
49822e23
WD		 498#define MX1_RXDATAREG1 __REG(0x00213000) /* SPI 1 Rx Data Register */
499#define MX1_TXDATAREG1 __REG(0x00213004) /* SPI 1 Tx Data Register */
500#define MX1_CONTROLREG1 __REG(0x00213008) /* SPI 1 Control Register */
501#define MX1_INTREG1 __REG(0x0021300C) /* SPI 1 Interrupt Control/Status Register */
502#define MX1_TESTREG1 __REG(0x00213010) /* SPI 1 Test Register */
503#define MX1_PERIODREG1 __REG(0x00213014) /* SPI 1 Sample Period Control Register */
504#define MX1_DMAREG1 __REG(0x00213018) /* SPI 1 DMA Control Register */
505#define MX1_RESETREG1 __REG(0x00213018) /* SPI 1 Soft Reset Register */
2d24a3a7
WD		 506
507/*
508 * MX1 MMC/SDHC registers
509 */
49822e23
WD		 510#define MX1_STR_STP_CLK __REG(0x00214000) /* MMC/SD Clock Control Register */
511#define MX1_STATUS __REG(0x00214004) /* MMC/SD Status Register */
512#define MX1_CLK_RATE __REG(0x00214008) /* MMC/SD Clock Rate Register */
2d24a3a7 513#define MX1_CMD_DAT_CONT __REG(0x0021400C) /* MMC/SD Command & Data Control Register */
49822e23 514#define MX1_RES_TO __REG(0x00214010) /* MMC/SD Response Time Out Register */
2d24a3a7
WD		 515#define MX1_READ_TO __REG(0x00214014) /* MMC/SD Read Time Out Register */
516#define MX1_BLK_LEN __REG(0x00214018) /* MMC/SD Block Length Register */
517#define MX1_NOB __REG(0x0021401C) /* MMC/SD Number of Block Register */
518#define MX1_REV_NO __REG(0x00214020) /* MMC/SD Revision Number Register */
519#define MX1_MMC_INT_MASK __REG(0x00214024) /* MMC/SD Interrupt Mask Register */
49822e23
WD		 520#define MX1_CMD __REG(0x00214028) /* MMC/SD Command Number Register */
521#define MX1_ARGH __REG(0x0021402C) /* MMC/SD Higher Argument Register */
522#define MX1_ARGL __REG(0x00214030) /* MMC/SD Lower Argument Register */
523#define MX1_RES_FIFO __REG(0x00214034) /* MMC/SD Response FIFO Register */
2d24a3a7
WD		 524#define MX1_BUFFER_ACCESS __REG(0x00214038) /* MMC/SD Buffer Access Register */
525
2d24a3a7
WD		 526/*
527 * MX1 ASP registers
528 */
49822e23
WD		 529#define MX1_ASP_PADFIFO __REG(0x00215000) /* Pen Sample FIFO */
530#define MX1_ASP_VADFIFO __REG(0x00215004) /* Voice ADC Register */
531#define MX1_ASP_VDAFIFO __REG(0x00215008) /* Voice DAC Register */
532#define MX1_ASP_VADCOEF __REG(0x0021500C) /* Voice ADC FIR Coefficients RAM */
533#define MX1_ASP_ACNTLCR __REG(0x00215010) /* Control Register */
534#define MX1_ASP_PSMPLRG __REG(0x00215014) /* Pen A/D Sample Rate Control Register */
535#define MX1_ASP_ICNTLR __REG(0x00215018) /* Interrupt Control Register */
536#define MX1_ASP_ISTATR __REG(0x0021501C) /* Interrupt/Error Status Register */
537#define MX1_ASP_VADGAIN __REG(0x00215020) /* Voice ADC Control Register */
538#define MX1_ASP_VDAGAIN __REG(0x00215024) /* Voice DAC Control Register */
539#define MX1_ASP_VDACOEF __REG(0x00215028) /* Voice DAC FIR Coefficients RAM */
540#define MX1_ASP_CLKDIV __REG(0x0021502C) /* Clock Divide Register */
541#define MX1_ASP_CMPCNTL __REG(0x0021502C) /* Compare Control Register */
2d24a3a7
WD		 542
543/*
544 * MX1 BTA registers
545 */
546
2d24a3a7
WD		 547/*
548 * MX1 I2C registers
549 */
49822e23
WD		 550#define MX1_IADR __REG(0x00217000) /* I2C Address Register */
551#define MX1_IFDR __REG(0x00217004) /* I2C Frequency Divider Register */
552#define MX1_I2CR __REG(0x00217008) /* I2C Control Register */
553#define MX1_I2CSR __REG(0x0021700C) /* I2C Status Register */
554#define MX1_I2DR __REG(0x00217010) /* I2C Data I/O Register */
2d24a3a7
WD		 555
556/*
557 * MX1 SSI registers
558 */
49822e23
WD		 559#define MX1_STX __REG(0x00218000) /* SSI Transmit Data Register */
560#define MX1_SRX __REG(0x00218004) /* SSI Receive Data Register */
561#define MX1_SCSR __REG(0x00218008) /* SSI Control/Status Register */
562#define MX1_STCR __REG(0x0021800C) /* SSI Transmit Configuration Register */
563#define MX1_SRCR __REG(0x00218010) /* SSI Recieve Configuration Register */
564#define MX1_STCCR __REG(0x00218014) /* SSI Transmit Clock Control Register */
565#define MX1_SRCCR __REG(0x00218018) /* SSI Receive Clock Control Register */
566#define MX1_STSR __REG(0x0021801C) /* SSI Time Slot Register */
567#define MX1_SFCSR __REG(0x00218020) /* SSI FIFO Control/Status Register */
568#define MX1_SOR __REG(0x00218024) /* SSI Option Register */
2d24a3a7
WD		 569
570/*
571 * MX1 SPI 2 registers
572 */
49822e23
WD		 573#define MX1_RXDATAREG2 __REG(0x00219000) /* SPI 2 Rx Data Register */
574#define MX1_TXDATAREG2 __REG(0x00219004) /* SPI 2 Tx Data Register */
575#define MX1_CONTROLREG2 __REG(0x00219008) /* SPI 2 Control Register */
576#define MX1_INTREG2 __REG(0x0021900C) /* SPI 2 Interrupt Control/Status Register */
577#define MX1_TESTREG2 __REG(0x00219010) /* SPI 2 Test Register */
578#define MX1_PERIODREG2 __REG(0x00219014) /* SPI 2 Sample Period Control Register */
579#define MX1_DMAREG2 __REG(0x00219018) /* SPI 2 DMA Control Register */
580#define MX1_RESETREG2 __REG(0x00219018) /* SPI 2 Soft Reset Register */
2d24a3a7
WD		 581
582/*
583 * MX1 MSHC registers
584 */
49822e23
WD		 585#define MX1_MSCMD __REG(0x0021A000) /* Memory Stick Command Register */
586#define MX1_MSCS __REG(0x0021A002) /* Memory Stick Control/Status Register */
587#define MX1_MSTDATA __REG(0x0021A004) /* Memory Stick Transmit FIFO Data Register */
588#define MX1_MSRDATA __REG(0x0021A004) /* Memory Stick Recieve FIFO Data Register */
589#define MX1_MSICS __REG(0x0021A006) /* Memory Stick Interrupt Control/Status Register */
590#define MX1_MSPPCD __REG(0x0021A008) /* Memory Stick Parallel Port Control/Data Register */
591#define MX1_MSC2 __REG(0x0021A00A) /* Memory Stick Control 2 Register */
592#define MX1_MSACD __REG(0x0021A00C) /* Memory Stick Auto Command Register */
593#define MX1_MSFAECS __REG(0x0021A00E) /* Memory Stick FIFO Access Error Control/Status Register */
594#define MX1_MSCLKD __REG(0x0021A010) /* Memory Stick Serial Clock divider Register */
595#define MX1_MSDRQC __REG(0x0021A012) /* Memory Stick DMA Request Control Register */
2d24a3a7
WD		 596
597/*
598 * MX1 PLLCLK registers
599 */
49822e23
WD		 600#define MX1_CSCR __REG(0x0021B000) /* Clock Source Control Register */
601#define MX1_MPCTL0 __REG(0x0021B004) /* MCU PLL Control Register 0 */
2d24a3a7
WD		 602#define MX1_MPCTL1 __REG(0x0021B008) /* MCU PLL & System Clock Control Register 1 */
603#define MX1_UPCTL0 __REG(0x0021B00C) /* USB PLL Control Register 0 */
604#define MX1_UPCTL1 __REG(0x0021B010) /* USB PLL Control Register 1 */
49822e23 605#define MX1_PCDR __REG(0x0021B020) /* Peripheral Clock Divider Register */
2d24a3a7
WD		 606
607/*
608 * MX1 RESET registers
609 */
49822e23 610#define MX1_RSR __REG(0x0021B800) /* Reset Source Register */
2d24a3a7
WD		 611
612/*
613 * MX1 SYS CTRL registers
614 */
49822e23
WD		 615#define MX1_SIDR __REG(0x0021B804) /* Silicon ID Register */
616#define MX1_FMCR __REG(0x0021B808) /* Function MultiPlexing Control Register */
617#define MX1_GPCR __REG(0x0021B80C) /* Global Peripheral Control Register */
2d24a3a7
WD		 618
619/*
620 * MX1 GPIO registers
621 */
622
623/* Port A */
49822e23 624#define MX1_DDIR_A __REG(0x0021C000) /* Port A Data Direction Register */
2d24a3a7
WD		 625#define MX1_OCR1_A __REG(0x0021C004) /* Port A Output Configuration Register 1 */
626#define MX1_OCR2_A __REG(0x0021C008) /* Port A Output Configuration Register 2 */
627#define MX1_ICONFA1_A __REG(0x0021C00C) /* Port A Input Configuration Register A1 */
628#define MX1_ICONFA2_A __REG(0x0021C010) /* Port A Input Configuration Register A2 */
629#define MX1_ICONFB1_A __REG(0x0021C014) /* Port A Input Configuration Register B1 */
630#define MX1_ICONFB2_A __REG(0x0021C018) /* Port A Input Configuration Register B2 */
49822e23
WD		 631#define MX1_DR_A __REG(0x0021C01C) /* Port A Data Register */
632#define MX1_GIUS_A __REG(0x0021C020) /* Port A GPIO In Use Register */
633#define MX1_SSR_A __REG(0x0021C024) /* Port A Sample Status Register */
634#define MX1_ICR1_A __REG(0x0021C028) /* Port A Interrupt Configuration Register 1 */
635#define MX1_ICR2_A __REG(0x0021C02C) /* Port A Interrupt Configuration Register 2 */
2d24a3a7
WD		 636#define MX1_IMR_A __REG(0x0021C030) /* Port A Interrupt Mask Register */
637#define MX1_ISR_A __REG(0x0021C034) /* Port A Interrupt Status Register */
638#define MX1_GPR_A __REG(0x0021C038) /* Port A General Purpose Register */
639#define MX1_SWR_A __REG(0x0021C03C) /* Port A Software Reset Register */
640#define MX1_PUEN_A __REG(0x0021C040) /* Port A Pull Up Enable Register */
641
2d24a3a7 642/* Port B */
49822e23 643#define MX1_DDIR_B __REG(0x0021C100) /* Port B Data Direction Register */
2d24a3a7
WD		 644#define MX1_OCR1_B __REG(0x0021C104) /* Port B Output Configuration Register 1 */
645#define MX1_OCR2_B __REG(0x0021C108) /* Port B Output Configuration Register 2 */
646#define MX1_ICONFA1_B __REG(0x0021C10C) /* Port B Input Configuration Register A1 */
647#define MX1_ICONFA2_B __REG(0x0021C110) /* Port B Input Configuration Register A2 */
648#define MX1_ICONFB1_B __REG(0x0021C114) /* Port B Input Configuration Register B1 */
649#define MX1_ICONFB2_B __REG(0x0021C118) /* Port B Input Configuration Register B2 */
49822e23
WD		 650#define MX1_DR_B __REG(0x0021C11C) /* Port B Data Register */
651#define MX1_GIUS_B __REG(0x0021C120) /* Port B GPIO In Use Register */
652#define MX1_SSR_B __REG(0x0021C124) /* Port B Sample Status Register */
653#define MX1_ICR1_B __REG(0x0021C128) /* Port B Interrupt Configuration Register 1 */
654#define MX1_ICR2_B __REG(0x0021C12C) /* Port B Interrupt Configuration Register 2 */
2d24a3a7
WD		 655#define MX1_IMR_B __REG(0x0021C130) /* Port B Interrupt Mask Register */
656#define MX1_ISR_B __REG(0x0021C134) /* Port B Interrupt Status Register */
657#define MX1_GPR_B __REG(0x0021C138) /* Port B General Purpose Register */
658#define MX1_SWR_B __REG(0x0021C13C) /* Port B Software Reset Register */
659#define MX1_PUEN_B __REG(0x0021C140) /* Port B Pull Up Enable Register */
660
2d24a3a7 661/* Port C */
49822e23 662#define MX1_DDIR_C __REG(0x0021C200) /* Port C Data Direction Register */
2d24a3a7
WD		 663#define MX1_OCR1_C __REG(0x0021C204) /* Port C Output Configuration Register 1 */
664#define MX1_OCR2_C __REG(0x0021C208) /* Port C Output Configuration Register 2 */
665#define MX1_ICONFA1_C __REG(0x0021C20C) /* Port C Input Configuration Register A1 */
666#define MX1_ICONFA2_C __REG(0x0021C210) /* Port C Input Configuration Register A2 */
667#define MX1_ICONFB1_C __REG(0x0021C214) /* Port C Input Configuration Register B1 */
668#define MX1_ICONFB2_C __REG(0x0021C218) /* Port C Input Configuration Register B2 */
49822e23
WD		 669#define MX1_DR_C __REG(0x0021C21C) /* Port C Data Register */
670#define MX1_GIUS_C __REG(0x0021C220) /* Port C GPIO In Use Register */
671#define MX1_SSR_C __REG(0x0021C224) /* Port C Sample Status Register */
672#define MX1_ICR1_C __REG(0x0021C228) /* Port C Interrupt Configuration Register 1 */
673#define MX1_ICR2_C __REG(0x0021C22C) /* Port C Interrupt Configuration Register 2 */
2d24a3a7
WD		 674#define MX1_IMR_C __REG(0x0021C230) /* Port C Interrupt Mask Register */
675#define MX1_ISR_C __REG(0x0021C234) /* Port C Interrupt Status Register */
676#define MX1_GPR_C __REG(0x0021C238) /* Port C General Purpose Register */
677#define MX1_SWR_C __REG(0x0021C23C) /* Port C Software Reset Register */
678#define MX1_PUEN_C __REG(0x0021C240) /* Port C Pull Up Enable Register */
679
2d24a3a7 680/* Port D */
49822e23 681#define MX1_DDIR_D __REG(0x0021C300) /* Port D Data Direction Register */
2d24a3a7
WD		 682#define MX1_OCR1_D __REG(0x0021C304) /* Port D Output Configuration Register 1 */
683#define MX1_OCR2_D __REG(0x0021C308) /* Port D Output Configuration Register 2 */
684#define MX1_ICONFA1_D __REG(0x0021C30C) /* Port D Input Configuration Register A1 */
685#define MX1_ICONFA2_D __REG(0x0021C310) /* Port D Input Configuration Register A2 */
686#define MX1_ICONFB1_D __REG(0x0021C314) /* Port D Input Configuration Register B1 */
687#define MX1_ICONFB2_D __REG(0x0021C318) /* Port D Input Configuration Register B2 */
49822e23
WD		 688#define MX1_DR_D __REG(0x0021C31C) /* Port D Data Register */
689#define MX1_GIUS_D __REG(0x0021C320) /* Port D GPIO In Use Register */
690#define MX1_SSR_D __REG(0x0021C324) /* Port D Sample Status Register */
691#define MX1_ICR1_D __REG(0x0021C328) /* Port D Interrupt Configuration Register 1 */
692#define MX1_ICR2_D __REG(0x0021C32C) /* Port D Interrupt Configuration Register 2 */
2d24a3a7
WD		 693#define MX1_IMR_D __REG(0x0021C330) /* Port D Interrupt Mask Register */
694#define MX1_ISR_D __REG(0x0021C334) /* Port D Interrupt Status Register */
695#define MX1_GPR_D __REG(0x0021C338) /* Port D General Purpose Register */
696#define MX1_SWR_D __REG(0x0021C33C) /* Port D Software Reset Register */
697#define MX1_PUEN_D __REG(0x0021C340) /* Port D Pull Up Enable Register */
698
2d24a3a7
WD		 699/*
700 * MX1 EIM registers
701 */
49822e23
WD		 702#define MX1_CS0U __REG(0x00220000) /* Chip Select 0 Upper Control Register */
703#define MX1_CS0L __REG(0x00220004) /* Chip Select 0 Lower Control Register */
704#define MX1_CS1U __REG(0x00220008) /* Chip Select 1 Upper Control Register */
705#define MX1_CS1L __REG(0x0022000C) /* Chip Select 1 Lower Control Register */
706#define MX1_CS2U __REG(0x00220010) /* Chip Select 2 Upper Control Register */
707#define MX1_CS2L __REG(0x00220014) /* Chip Select 2 Lower Control Register */
708#define MX1_CS3U __REG(0x00220018) /* Chip Select 3 Upper Control Register */
709#define MX1_CS3L __REG(0x0022001C) /* Chip Select 3 Lower Control Register */
710#define MX1_CS4U __REG(0x00220020) /* Chip Select 4 Upper Control Register */
711#define MX1_CS4L __REG(0x00220024) /* Chip Select 4 Lower Control Register */
712#define MX1_CS5U __REG(0x00220028) /* Chip Select 5 Upper Control Register */
713#define MX1_CS5L __REG(0x0022002C) /* Chip Select 5 Lower Control Register */
714#define MX1_WEIM __REG(0x00220030) /* weim cONFIGURATION Register */
2d24a3a7
WD		 715
716/*
717 * MX1 SDRAMC registers
718 */
49822e23
WD		 719#define MX1_SDCTL0 __REG(0x00221000) /* SDRAM 0 Control Register */
720#define MX1_SDCTL1 __REG(0x00221004) /* SDRAM 1 Control Register */
721#define MX1_MISCELLANEOUS __REG(0x00221014) /* Miscellaneous Register */
722#define MX1_SDRST __REG(0x00221018) /* SDRAM Reset Register */
2d24a3a7
WD		 723
724/*
725 * MX1 MMA registers
726 */
49822e23
WD		 727#define MX1_MMA_MAC_MOD __REG(0x00222000) /* MMA MAC Module Register */
728#define MX1_MMA_MAC_CTRL __REG(0x00222004) /* MMA MAC Control Register */
729#define MX1_MMA_MAC_MULT __REG(0x00222008) /* MMA MAC Multiply Counter Register */
730#define MX1_MMA_MAC_ACCU __REG(0x0022200C) /* MMA MAC Accumulate Counter Register */
731#define MX1_MMA_MAC_INTR __REG(0x00222010) /* MMA MAC Interrupt Register */
732#define MX1_MMA_MAC_INTR_MASK __REG(0x00222014) /* MMA MAC Interrupt Mask Register */
733#define MX1_MMA_MAC_FIFO __REG(0x00222018) /* MMA MAC FIFO Register */
734#define MX1_MMA_MAC_FIFO_STAT __REG(0x0022201C) /* MMA MAC FIFO Status Register */
735#define MX1_MMA_MAC_BURST __REG(0x00222020) /* MMA MAC Burst Count Register */
736#define MX1_MMA_MAC_BITSEL __REG(0x00222024) /* MMA MAC Bit Select Register */
2d24a3a7
WD		 737
738#define MX1_MMA_MAC_XBASE __REG(0x00222200) /* MMA MAC X Base Address Register */
49822e23
WD		 739#define MX1_MMA_MAC_XINDEX __REG(0x00222204) /* MMA MAC X Index Register */
740#define MX1_MMA_MAC_XLENGTH __REG(0x00222208) /* MMA MAC X Length Register */
741#define MX1_MMA_MAC_XMODIFY __REG(0x0022220C) /* MMA MAC X Modify Register */
742#define MX1_MMA_MAC_XINCR __REG(0x00222210) /* MMA MAC X Increment Register */
743#define MX1_MMA_MAC_XCOUNT __REG(0x00222214) /* MMA MAC X Count Register */
2d24a3a7
WD		 744
745#define MX1_MMA_MAC_YBASE __REG(0x00222300) /* MMA MAC Y Base Address Register */
49822e23
WD		 746#define MX1_MMA_MAC_YINDEX __REG(0x00222304) /* MMA MAC Y Index Register */
747#define MX1_MMA_MAC_YLENGTH __REG(0x00222308) /* MMA MAC Y Length Register */
748#define MX1_MMA_MAC_YMODIFY __REG(0x0022230C) /* MMA MAC Y Modify Register */
749#define MX1_MMA_MAC_YINCR __REG(0x00222310) /* MMA MAC Y Increment Register */
750#define MX1_MMA_MAC_YCOUNT __REG(0x00222314) /* MMA MAC Y Count Register */
751
752#define MX1_MMA_DCTCTRL __REG(0x00222400) /* DCT/iDCT Control Register */
753#define MX1_MMA_DCTVERSION __REG(0x00222404) /* DCT/iDCT Version Register */
754#define MX1_MMA_DCTIRQENA __REG(0x00222408) /* DCT/iDCT IRQ Enable Register */
755#define MX1_MMA_DCTIRQSTAT __REG(0x0022240C) /* DCT/iDCT IRQ Status Register */
756#define MX1_MMA_DCTSRCDATA __REG(0x00222410) /* DCT/iDCT Source Data Address */
757#define MX1_MMA_DCTDESDATA __REG(0x00222414) /* DCT/iDCT Destination Data Address */
758#define MX1_MMA_DCTXOFF __REG(0x00222418) /* DCT/iDCT X-Offset Address */
759#define MX1_MMA_DCTYOFF __REG(0x0022241C) /* DCT/iDCT Y-Offset Address */
760#define MX1_MMA_DCTXYCNT __REG(0x00222420) /* DCT/iDCT XY Count */
761#define MX1_MMA_DCTSKIP __REG(0x00222424) /* DCT/iDCT Skip Address */
762#define MX1_MMA_DCTFIFO __REG(0x00222500) /* DCT/iDCT Data FIFO */
2d24a3a7
WD		 763
764/*
765 * MX1 AITC registers
766 */
49822e23
WD		 767#define MX1_INTCNTL __REG(0x00223000) /* Interrupt Control Register */
768#define MX1_NIMASK __REG(0x00223004) /* Normal Interrupt Mask Register */
769#define MX1_INTENNUM __REG(0x00223008) /* Interrupt Enable Number Register */
770#define MX1_INTDISNUM __REG(0x0022300C) /* Interrupt Disable Number Register */
771#define MX1_INTENABLEH __REG(0x00223010) /* Interrupt Enable Register High */
772#define MX1_INTENABLEL __REG(0x00223014) /* Interrupt Enable Register Low */
773#define MX1_INTTYPEH __REG(0x00223018) /* Interrupt Type Register High */
774#define MX1_INTTYPEL __REG(0x0022301C) /* Interrupt Type Register Low */
775#define MX1_NIPRIORITY7 __REG(0x00223020) /* Normal Interrupt Priority Level Register 7*/
776#define MX1_NIPRIORITY6 __REG(0x00223024) /* Normal Interrupt Priority Level Register 6*/
777#define MX1_NIPRIORITY5 __REG(0x00223028) /* Normal Interrupt Priority Level Register 5*/
778#define MX1_NIPRIORITY4 __REG(0x0022302C) /* Normal Interrupt Priority Level Register 4*/
779#define MX1_NIPRIORITY3 __REG(0x00223030) /* Normal Interrupt Priority Level Register 3*/
780#define MX1_NIPRIORITY2 __REG(0x00223034) /* Normal Interrupt Priority Level Register 2*/
781#define MX1_NIPRIORITY1 __REG(0x00223038) /* Normal Interrupt Priority Level Register 1*/
782#define MX1_NIPRIORITY0 __REG(0x0022303C) /* Normal Interrupt Priority Level Register 0*/
2d24a3a7
WD		 783#define MX1_NIVECSR __REG(0x00223040) /* Normal Interrupt Vector & Status Register */
784#define MX1_FIVECSR __REG(0x00223044) /* Fast Interrupt Vector & Status Register */
49822e23
WD		 785#define MX1_INTSRCH __REG(0x00223048) /* Interrupt Source Register High */
786#define MX1_INTSRCL __REG(0x0022304C) /* Interrupt Source Register Low */
787#define MX1_INTFRCH __REG(0x00223050) /* Interrupt Force Register High */
788#define MX1_INTFRCL __REG(0x00223054) /* Interrupt Force Register Low */
789#define MX1_NIPNDH __REG(0x00223058) /* Normal Interrupt Pending Register High */
790#define MX1_NIPNDL __REG(0x0022305C) /* Normal Interrupt Pending Register Low */
791#define MX1_FIPNDH __REG(0x00223060) /* Fast Interrupt Pending Register High */
792#define MX1_FIPNDL __REG(0x00223064) /* Fast Interrupt Pending Register Low */
2d24a3a7
WD		 793
794/*
795 * MX1 CSI registers
796 */
49822e23
WD		 797#define MX1_CSICR1 __REG(0x00224000) /* CSI Control Register 1 */
798#define MX1_CSICR2 __REG(0x00224004) /* CSI Control Register 2 */
799#define MX1_CSISR __REG(0x00224008) /* CSI Status Register 1 */
2d24a3a7
WD		 800#define MX1_CSISTATR __REG(0x0022400C) /* CSI Statistic FIFO Register 1 */
801#define MX1_CSIRXR __REG(0x00224010) /* CSI RxFIFO Register 1 */
802
2d24a3a7
WD		 803#endif /* __MC9328_H__ */
804
2d24a3a7 805#if 0
2d24a3a7 806/*
49822e23 807 MX1 dma definition
2d24a3a7
WD		 808*/
809
810#define MAX_DMA_ADDRESS 0xffffffff
811
49822e23 812/*#define MAX_DMA_CHANNELS 0 */
2d24a3a7 813
49822e23 814#define MAX_DMA_CHANNELS 11
2d24a3a7
WD		 815#define MAX_DMA_2D_REGSET 2
816
817/* MX1 DMA module registers' address */
818
49822e23
WD		 819#define MX1_DMA_BASE IO_ADDRESS(0x00209000)
820#define MX1_DMA_DCR (MX1_DMA_BASE + 0x00) /* DMA control register */
821#define MX1_DMA_DISR (MX1_DMA_BASE + 0x04) /* DMA interrupt status register */
822#define MX1_DMA_DIMR (MX1_DMA_BASE + 0x08) /* DMA interrupt mask register */
823#define MX1_DMA_DBTOSR (MX1_DMA_BASE + 0x0C) /* DMA burst time-out status register */
824#define MX1_DMA_DRTOSR (MX1_DMA_BASE + 0x10) /* DMA request time-out status register */
825#define MX1_DMA_DSESR (MX1_DMA_BASE + 0x14) /* DMA transfer error status register */
826#define MX1_DMA_DBOSR (MX1_DMA_BASE + 0x18) /* DMA buffer overflow status register */
827#define MX1_DMA_DBTOCR (MX1_DMA_BASE + 0x1C) /* DMA burst time-out control register */
828#define MX1_DMA_WSRA (MX1_DMA_BASE + 0x40) /* W-size register A */
829#define MX1_DMA_XSRA (MX1_DMA_BASE + 0x44) /* X-size register A */
830#define MX1_DMA_YSRA (MX1_DMA_BASE + 0x48) /* Y-size register A */
831#define MX1_DMA_WSRB (MX1_DMA_BASE + 0x4C) /* W-size register B */
832#define MX1_DMA_XSRB (MX1_DMA_BASE + 0x50) /* X-size register B */
833#define MX1_DMA_YSRB (MX1_DMA_BASE + 0x54) /* Y-size register B */
834
835#define MX1_DMA_SAR0 (MX1_DMA_BASE + 0x80) /* source address register 0 */
836#define MX1_DMA_DAR0 (MX1_DMA_BASE + 0x84) /* destination address register 0 */
837#define MX1_DMA_CNTR0 (MX1_DMA_BASE + 0x88) /* count register 0 */
838#define MX1_DMA_CCR0 (MX1_DMA_BASE + 0x8C) /* channel control register 0 */
839#define MX1_DMA_RSSR0 (MX1_DMA_BASE + 0x90) /* request source select register 0 */
840#define MX1_DMA_BLR0 (MX1_DMA_BASE + 0x94) /* burst length register 0 */
841#define MX1_DMA_RTOR0 (MX1_DMA_BASE + 0x98) /* request time-out register 0 */
842#define MX1_DMA_BUCR0 (MX1_DMA_BASE + 0x98) /* bus utilization control register 0 */
2d24a3a7
WD		 843
844/* register set 1 to 10 are offseted by 0x40 each = 0x10 pointers away */
845
49822e23 846#define DMA_REG_SET_OFS 0x10
2d24a3a7
WD		 847
848/* MX1 DMA module registers */
49822e23
WD		 849#define _reg_DMA_DCR (*((P_VU32)MX1_DMA_DCR))
850#define _reg_DMA_DISR (*((P_VU32)MX1_DMA_DISR))
851#define _reg_DMA_DIMR (*((P_VU32)MX1_DMA_DIMR))
852#define _reg_DMA_DBTOSR (*((P_VU32)MX1_DMA_DBTOSR))
853#define _reg_DMA_DRTOSR (*((P_VU32)MX1_DMA_DRTOSR))
854#define _reg_DMA_DSESR (*((P_VU32)MX1_DMA_DSESR))
855#define _reg_DMA_DBOSR (*((P_VU32)MX1_DMA_DBOSR))
856#define _reg_DMA_DBTOCR (*((P_VU32)MX1_DMA_DBTOCR))
857#define _reg_DMA_WSRA (*((P_VU32)MX1_DMA_WSRA))
858#define _reg_DMA_XSRA (*((P_VU32)MX1_DMA_XSRA))
859#define _reg_DMA_YSRA (*((P_VU32)MX1_DMA_YSRA))
860#define _reg_DMA_WSRB (*((P_VU32)MX1_DMA_WSRB))
861#define _reg_DMA_XSRB (*((P_VU32)MX1_DMA_XSRB))
862#define _reg_DMA_YSRB (*((P_VU32)MX1_DMA_YSRB))
863#define _reg_DMA_SAR0 (*((P_VU32)MX1_DMA_SAR0))
864#define _reg_DMA_DAR0 (*((P_VU32)MX1_DMA_DAR0))
865#define _reg_DMA_CNTR0 (*((P_VU32)MX1_DMA_CNTR0))
866#define _reg_DMA_CCR0 (*((P_VU32)MX1_DMA_CCR0))
867#define _reg_DMA_RSSR0 (*((P_VU32)MX1_DMA_RSSR0))
868#define _reg_DMA_BLR0 (*((P_VU32)MX1_DMA_BLR0))
869#define _reg_DMA_RTOR0 (*((P_VU32)MX1_DMA_RTOR0))
870#define _reg_DMA_BUCR0 (*((P_VU32)MX1_DMA_BUCR0))
2d24a3a7
WD		 871
872/* DMA error type definition */
49822e23
WD		 873#define MX1_DMA_ERR_BTO 0 /* burst time-out */
874#define MX1_DMA_ERR_RTO 1 /* request time-out */
875#define MX1_DMA_ERR_TE 2 /* transfer error */
876#define MX1_DMA_ERR_BO 3 /* buffer overflow */
2d24a3a7
WD		 877
878/* Embedded SRAM */
879
880#define MX1_SRAM_BASE 0x00300000
881#define MX1_SRAM_SIZE 0x00020000
882
49822e23 883#define
2d24a3a7 884
49822e23
WD		 885#define MX1ADS_SFLASH_BASE 0x0C000000
886#define MX1ADS_SFLASH_SIZE SZ_16M
2d24a3a7 887
49822e23
WD		 888#define MX1ADS_IO_BASE 0x00200000
889#define MX1ADS_IO_SIZE SZ_256K
2d24a3a7 890
49822e23
WD		 891#define MX1ADS_VID_BASE 0x00300000
892#define MX1ADS_VID_SIZE 0x26000
2d24a3a7 893
49822e23 894#define MX1ADS_VID_START IO_ADDRESS(MX1ADS_VID_BASE)
2d24a3a7 895
49822e23
WD		 896#define MX1_GPIO_BASE 0x0021C000 /* GPIO */
897#define MX1_EXT_UART_BASE 0x15000000 /* external UART */
898#define MX1_TMR1_BASE 0x00202000 /* Timer1 */
899#define MX1ADS_FLASH_BASE 0x0C000000 /* sync FLASH */
900#define MX1_ESRAM_BASE 0x00300000 /* embedded SRAM */
901#define MX1ADS_SDRAM_DISK_BASE 0x0B000000 /* SDRAM disk base (last 16M of SDRAM) */
2d24a3a7
WD		 902
903/* ------------------------------------------------------------------------
904 * Motorola MX1 system registers
905 * ------------------------------------------------------------------------
906 *
907 */
908
909/*
910 * Register offests.
911 *
912 */
913
49822e23
WD		 914#define MX1ADS_AIPI1_OFFSET 0x00000
915#define MX1ADS_WDT_OFFSET 0x01000
916#define MX1ADS_TIM1_OFFSET 0x02000
917#define MX1ADS_TIM2_OFFSET 0x03000
918#define MX1ADS_RTC_OFFSET 0x04000
919#define MX1ADS_LCDC_OFFSET 0x05000
920#define MX1ADS_UART1_OFFSET 0x06000
921#define MX1ADS_UART2_OFFSET 0x07000
922#define MX1ADS_PWM_OFFSET 0x08000
923#define MX1ADS_DMAC_OFFSET 0x09000
924#define MX1ADS_AIPI2_OFFSET 0x10000
925#define MX1ADS_SIM_OFFSET 0x11000
926#define MX1ADS_USBD_OFFSET 0x12000
927#define MX1ADS_SPI1_OFFSET 0x13000
928#define MX1ADS_MMC_OFFSET 0x14000
929#define MX1ADS_ASP_OFFSET 0x15000
930#define MX1ADS_BTA_OFFSET 0x16000
931#define MX1ADS_I2C_OFFSET 0x17000
932#define MX1ADS_SSI_OFFSET 0x18000
933#define MX1ADS_SPI2_OFFSET 0x19000
934#define MX1ADS_MSHC_OFFSET 0x1A000
935#define MX1ADS_PLL_OFFSET 0x1B000
936#define MX1ADS_GPIO_OFFSET 0x1C000
937#define MX1ADS_EIM_OFFSET 0x20000
938#define MX1ADS_SDRAMC_OFFSET 0x21000
939#define MX1ADS_MMA_OFFSET 0x22000
940#define MX1ADS_AITC_OFFSET 0x23000
941#define MX1ADS_CSI_OFFSET 0x24000
2d24a3a7
WD		 942
943/*
944 * Register BASEs, based on OFFSETs
945 *
946 */
947
49822e23
WD		 948#define MX1ADS_AIPI1_BASE (MX1ADS_AIPI1_OFFSET + MX1ADS_IO_BASE)
949#define MX1ADS_WDT_BASE (MX1ADS_WDT_OFFSET + MX1ADS_IO_BASE)
950#define MX1ADS_TIM1_BASE (MX1ADS_TIM1_OFFSET + MX1ADS_IO_BASE)
951#define MX1ADS_TIM2_BASE (MX1ADS_TIM2_OFFSET + MX1ADS_IO_BASE)
952#define MX1ADS_RTC_BASE (MX1ADS_RTC_OFFSET + MX1ADS_IO_BASE)
953#define MX1ADS_LCDC_BASE (MX1ADS_LCDC_OFFSET + MX1ADS_IO_BASE)
954#define MX1ADS_UART1_BASE (MX1ADS_UART1_OFFSET + MX1ADS_IO_BASE)
955#define MX1ADS_UART2_BASE (MX1ADS_UART2_OFFSET + MX1ADS_IO_BASE)
956#define MX1ADS_PWM_BASE (MX1ADS_PWM_OFFSET + MX1ADS_IO_BASE)
957#define MX1ADS_DMAC_BASE (MX1ADS_DMAC_OFFSET + MX1ADS_IO_BASE)
958#define MX1ADS_AIPI2_BASE (MX1ADS_AIPI2_OFFSET + MX1ADS_IO_BASE)
959#define MX1ADS_SIM_BASE (MX1ADS_SIM_OFFSET + MX1ADS_IO_BASE)
960#define MX1ADS_USBD_BASE (MX1ADS_USBD_OFFSET + MX1ADS_IO_BASE)
961#define MX1ADS_SPI1_BASE (MX1ADS_SPI1_OFFSET + MX1ADS_IO_BASE)
962#define MX1ADS_MMC_BASE (MX1ADS_MMC_OFFSET + MX1ADS_IO_BASE)
963#define MX1ADS_ASP_BASE (MX1ADS_ASP_OFFSET + MX1ADS_IO_BASE)
964#define MX1ADS_BTA_BASE (MX1ADS_BTA_OFFSET + MX1ADS_IO_BASE)
965#define MX1ADS_I2C_BASE (MX1ADS_I2C_OFFSET + MX1ADS_IO_BASE)
966#define MX1ADS_SSI_BASE (MX1ADS_SSI_OFFSET + MX1ADS_IO_BASE)
967#define MX1ADS_SPI2_BASE (MX1ADS_SPI2_OFFSET + MX1ADS_IO_BASE)
968#define MX1ADS_MSHC_BASE (MX1ADS_MSHC_OFFSET + MX1ADS_IO_BASE)
969#define MX1ADS_PLL_BASE (MX1ADS_PLL_OFFSET + MX1ADS_IO_BASE)
970#define MX1ADS_GPIO_BASE (MX1ADS_GPIO_OFFSET + MX1ADS_IO_BASE)
971#define MX1ADS_EIM_BASE (MX1ADS_EIM_OFFSET + MX1ADS_IO_BASE)
972#define MX1ADS_SDRAMC_BASE (MX1ADS_SDRAMC_OFFSET + MX1ADS_IO_BASE)
973#define MX1ADS_MMA_BASE (MX1ADS_MMA_OFFSET + MX1ADS_IO_BASE)
974#define MX1ADS_AITC_BASE (MX1ADS_AITC_OFFSET + MX1ADS_IO_BASE)
975#define MX1ADS_CSI_BASE (MX1ADS_CSI_OFFSET + MX1ADS_IO_BASE)
2d24a3a7
WD		 976
977/*
978 * MX1 Interrupt numbers
979 *
980 */
49822e23
WD		 981#define INT_SOFTINT 0
982#define CSI_INT 6
983#define DSPA_MAC_INT 7
984#define DSPA_INT 8
985#define COMP_INT 9
986#define MSHC_XINT 10
987#define GPIO_INT_PORTA 11
988#define GPIO_INT_PORTB 12
989#define GPIO_INT_PORTC 13
990#define LCDC_INT 14
991#define SIM_INT 15
992#define SIM_DATA_INT 16
993#define RTC_INT 17
994#define RTC_SAMINT 18
995#define UART2_MINT_PFERR 19
996#define UART2_MINT_RTS 20
997#define UART2_MINT_DTR 21
998#define UART2_MINT_UARTC 22
999#define UART2_MINT_TX 23
1000#define UART2_MINT_RX 24
1001#define UART1_MINT_PFERR 25
1002#define UART1_MINT_RTS 26
1003#define UART1_MINT_DTR 27
1004#define UART1_MINT_UARTC 28
1005#define UART1_MINT_TX 29
1006#define UART1_MINT_RX 30
1007#define VOICE_DAC_INT 31
1008#define VOICE_ADC_INT 32
1009#define PEN_DATA_INT 33
1010#define PWM_INT 34
1011#define SDHC_INT 35
1012#define I2C_INT 39
1013#define CSPI_INT 41
1014#define SSI_TX_INT 42
1015#define SSI_TX_ERR_INT 43
1016#define SSI_RX_INT 44
1017#define SSI_RX_ERR_INT 45
1018#define TOUCH_INT 46
1019#define USBD_INT0 47
1020#define USBD_INT1 48
1021#define USBD_INT2 49
1022#define USBD_INT3 50
1023#define USBD_INT4 51
1024#define USBD_INT5 52
1025#define USBD_INT6 53
1026#define BTSYS_INT 55
1027#define BTTIM_INT 56
1028#define BTWUI_INT 57
1029#define TIMER2_INT 58
1030#define TIMER1_INT 59
1031#define DMA_ERR 60
1032#define DMA_INT 61
1033#define GPIO_INT_PORTD 62
1034
1035#define MAXIRQNUM 62
1036#define MAXFIQNUM 62
1037#define MAXSWINUM 62
1038
1039#define TICKS_PER_uSEC 24
2d24a3a7
WD		 1040
1041/*
1042 * These are useconds NOT ticks.
1043 *
1044 */
49822e23
WD		 1045#define mSEC_1 1000
1046#define mSEC_5 (mSEC_1 * 5)
1047#define mSEC_10 (mSEC_1 * 10)
1048#define mSEC_25 (mSEC_1 * 25)
1049#define SEC_1 (mSEC_1 * 1000)
2d24a3a7 1050
49822e23 1051#endif
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