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Move ALLOC_CACHE_ALIGN_BUFFER() to the new memalign.h header
[J-u-boot.git] / drivers / usb / eth / asix.c
CommitLineData
9b70e007
SG		 1/*
2 * Copyright (c) 2011 The Chromium OS Authors.
9b70e007 3 *
14727120
MZ		 4 * Patched for AX88772B by Antmicro Ltd <www.antmicro.com>
5 *
1a459660 6 * SPDX-License-Identifier: GPL-2.0+
9b70e007
SG		 7 */
8
9#include <common.h>
fbc4b8af 10#include <dm.h>
9b70e007 11#include <usb.h>
fbc4b8af 12#include <malloc.h>
cf92e05c 13#include <memalign.h>
9b70e007
SG		 14#include <linux/mii.h>
15#include "usb_ether.h"
9b70e007
SG		 16
17/* ASIX AX8817X based USB 2.0 Ethernet Devices */
18
19#define AX_CMD_SET_SW_MII 0x06
20#define AX_CMD_READ_MII_REG 0x07
21#define AX_CMD_WRITE_MII_REG 0x08
22#define AX_CMD_SET_HW_MII 0x0a
02c8d8cc 23#define AX_CMD_READ_EEPROM 0x0b
9b70e007
SG		 24#define AX_CMD_READ_RX_CTL 0x0f
25#define AX_CMD_WRITE_RX_CTL 0x10
26#define AX_CMD_WRITE_IPG0 0x12
27#define AX_CMD_READ_NODE_ID 0x13
58f8fab8 28#define AX_CMD_WRITE_NODE_ID 0x14
9b70e007
SG		 29#define AX_CMD_READ_PHY_ID 0x19
30#define AX_CMD_WRITE_MEDIUM_MODE 0x1b
31#define AX_CMD_WRITE_GPIOS 0x1f
32#define AX_CMD_SW_RESET 0x20
33#define AX_CMD_SW_PHY_SELECT 0x22
34
35#define AX_SWRESET_CLEAR 0x00
36#define AX_SWRESET_PRTE 0x04
37#define AX_SWRESET_PRL 0x08
38#define AX_SWRESET_IPRL 0x20
39#define AX_SWRESET_IPPD 0x40
40
41#define AX88772_IPG0_DEFAULT 0x15
42#define AX88772_IPG1_DEFAULT 0x0c
43#define AX88772_IPG2_DEFAULT 0x12
44
45/* AX88772 & AX88178 Medium Mode Register */
46#define AX_MEDIUM_PF 0x0080
47#define AX_MEDIUM_JFE 0x0040
48#define AX_MEDIUM_TFC 0x0020
49#define AX_MEDIUM_RFC 0x0010
50#define AX_MEDIUM_ENCK 0x0008
51#define AX_MEDIUM_AC 0x0004
52#define AX_MEDIUM_FD 0x0002
53#define AX_MEDIUM_GM 0x0001
54#define AX_MEDIUM_SM 0x1000
55#define AX_MEDIUM_SBP 0x0800
56#define AX_MEDIUM_PS 0x0200
57#define AX_MEDIUM_RE 0x0100
58
59#define AX88178_MEDIUM_DEFAULT \
60 (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \
61 AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \
62 AX_MEDIUM_RE)
63
64#define AX88772_MEDIUM_DEFAULT \
65 (AX_MEDIUM_FD | AX_MEDIUM_RFC | \
66 AX_MEDIUM_TFC | AX_MEDIUM_PS | \
67 AX_MEDIUM_AC | AX_MEDIUM_RE)
68
69/* AX88772 & AX88178 RX_CTL values */
14727120
MZ		 70#define AX_RX_CTL_RH2M 0x0200 /* 32-bit aligned RX IP header */
71#define AX_RX_CTL_RH1M 0x0100 /* Enable RX header format type 1 */
72#define AX_RX_CTL_SO 0x0080
73#define AX_RX_CTL_AB 0x0008
74#define AX_RX_HEADER_DEFAULT (AX_RX_CTL_RH1M | AX_RX_CTL_RH2M)
9b70e007
SG		 75
76#define AX_DEFAULT_RX_CTL \
77 (AX_RX_CTL_SO | AX_RX_CTL_AB)
78
79/* GPIO 2 toggles */
80#define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */
81#define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */
82#define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */
83
84/* local defines */
85#define ASIX_BASE_NAME "asx"
86#define USB_CTRL_SET_TIMEOUT 5000
87#define USB_CTRL_GET_TIMEOUT 5000
88#define USB_BULK_SEND_TIMEOUT 5000
89#define USB_BULK_RECV_TIMEOUT 5000
90
91#define AX_RX_URB_SIZE 2048
92#define PHY_CONNECT_TIMEOUT 5000
93
58f8fab8
LS		 94/* asix_flags defines */
95#define FLAG_NONE 0
96#define FLAG_TYPE_AX88172 (1U << 0)
97#define FLAG_TYPE_AX88772 (1U << 1)
1dff9d0f
LS		 98#define FLAG_TYPE_AX88772B (1U << 2)
99#define FLAG_EEPROM_MAC (1U << 3) /* initial mac address in eeprom */
58f8fab8 100
14727120
MZ		 101#define ASIX_USB_VENDOR_ID 0x0b95
102#define AX88772B_USB_PRODUCT_ID 0x772b
9b70e007 103
58f8fab8
LS		 104/* driver private */
105struct asix_private {
106 int flags;
fbc4b8af
SG		 107#ifdef CONFIG_DM_ETH
108 struct ueth_data ueth;
109#endif
58f8fab8
LS		 110};
111
fbc4b8af
SG		 112#ifndef CONFIG_DM_ETH
113/* local vars */
114static int curr_eth_dev; /* index for name of next device detected */
115#endif
116
9b70e007
SG		 117/*
118 * Asix infrastructure commands
119 */
120static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
121 u16 size, void *data)
122{
123 int len;
124
125 debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x "
126 "size=%d\n", cmd, value, index, size);
127
128 len = usb_control_msg(
129 dev->pusb_dev,
130 usb_sndctrlpipe(dev->pusb_dev, 0),
131 cmd,
132 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
133 value,
134 index,
135 data,
136 size,
137 USB_CTRL_SET_TIMEOUT);
138
139 return len == size ? 0 : -1;
140}
141
142static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
143 u16 size, void *data)
144{
145 int len;
146
147 debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
148 cmd, value, index, size);
149
150 len = usb_control_msg(
151 dev->pusb_dev,
152 usb_rcvctrlpipe(dev->pusb_dev, 0),
153 cmd,
154 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
155 value,
156 index,
157 data,
158 size,
159 USB_CTRL_GET_TIMEOUT);
160 return len == size ? 0 : -1;
161}
162
163static inline int asix_set_sw_mii(struct ueth_data *dev)
164{
165 int ret;
166
167 ret = asix_write_cmd(dev, AX_CMD_SET_SW_MII, 0x0000, 0, 0, NULL);
168 if (ret < 0)
169 debug("Failed to enable software MII access\n");
170 return ret;
171}
172
173static inline int asix_set_hw_mii(struct ueth_data *dev)
174{
175 int ret;
176
177 ret = asix_write_cmd(dev, AX_CMD_SET_HW_MII, 0x0000, 0, 0, NULL);
178 if (ret < 0)
179 debug("Failed to enable hardware MII access\n");
180 return ret;
181}
182
183static int asix_mdio_read(struct ueth_data *dev, int phy_id, int loc)
184{
c59ab092 185 ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1);
9b70e007
SG		 186
187 asix_set_sw_mii(dev);
c59ab092 188 asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id, (__u16)loc, 2, res);
9b70e007
SG		 189 asix_set_hw_mii(dev);
190
191 debug("asix_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n",
c59ab092 192 phy_id, loc, le16_to_cpu(*res));
9b70e007 193
c59ab092 194 return le16_to_cpu(*res);
9b70e007
SG		 195}
196
197static void
198asix_mdio_write(struct ueth_data *dev, int phy_id, int loc, int val)
199{
c59ab092
MV		 200 ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1);
201 *res = cpu_to_le16(val);
9b70e007
SG		 202
203 debug("asix_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x\n",
204 phy_id, loc, val);
205 asix_set_sw_mii(dev);
c59ab092 206 asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id, (__u16)loc, 2, res);
9b70e007
SG		 207 asix_set_hw_mii(dev);
208}
209
210/*
211 * Asix "high level" commands
212 */
213static int asix_sw_reset(struct ueth_data *dev, u8 flags)
214{
215 int ret;
216
217 ret = asix_write_cmd(dev, AX_CMD_SW_RESET, flags, 0, 0, NULL);
218 if (ret < 0)
219 debug("Failed to send software reset: %02x\n", ret);
220 else
221 udelay(150 * 1000);
222
223 return ret;
224}
225
226static inline int asix_get_phy_addr(struct ueth_data *dev)
227{
c59ab092
MV		 228 ALLOC_CACHE_ALIGN_BUFFER(u8, buf, 2);
229
9b70e007
SG		 230 int ret = asix_read_cmd(dev, AX_CMD_READ_PHY_ID, 0, 0, 2, buf);
231
232 debug("asix_get_phy_addr()\n");
233
234 if (ret < 0) {
235 debug("Error reading PHYID register: %02x\n", ret);
236 goto out;
237 }
0ed1eb6f 238 debug("asix_get_phy_addr() returning 0x%02x%02x\n", buf[0], buf[1]);
9b70e007
SG		 239 ret = buf[1];
240
241out:
242 return ret;
243}
244
245static int asix_write_medium_mode(struct ueth_data *dev, u16 mode)
246{
247 int ret;
248
249 debug("asix_write_medium_mode() - mode = 0x%04x\n", mode);
250 ret = asix_write_cmd(dev, AX_CMD_WRITE_MEDIUM_MODE, mode,
251 0, 0, NULL);
252 if (ret < 0) {
253 debug("Failed to write Medium Mode mode to 0x%04x: %02x\n",
254 mode, ret);
255 }
256 return ret;
257}
258
259static u16 asix_read_rx_ctl(struct ueth_data *dev)
260{
c59ab092
MV		 261 ALLOC_CACHE_ALIGN_BUFFER(__le16, v, 1);
262
263 int ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, 0, 0, 2, v);
9b70e007
SG		 264
265 if (ret < 0)
266 debug("Error reading RX_CTL register: %02x\n", ret);
267 else
c59ab092 268 ret = le16_to_cpu(*v);
9b70e007
SG		 269 return ret;
270}
271
272static int asix_write_rx_ctl(struct ueth_data *dev, u16 mode)
273{
274 int ret;
275
276 debug("asix_write_rx_ctl() - mode = 0x%04x\n", mode);
277 ret = asix_write_cmd(dev, AX_CMD_WRITE_RX_CTL, mode, 0, 0, NULL);
278 if (ret < 0) {
279 debug("Failed to write RX_CTL mode to 0x%04x: %02x\n",
280 mode, ret);
281 }
282 return ret;
283}
284
285static int asix_write_gpio(struct ueth_data *dev, u16 value, int sleep)
286{
287 int ret;
288
289 debug("asix_write_gpio() - value = 0x%04x\n", value);
290 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, value, 0, 0, NULL);
291 if (ret < 0) {
292 debug("Failed to write GPIO value 0x%04x: %02x\n",
293 value, ret);
294 }
295 if (sleep)
296 udelay(sleep * 1000);
297
298 return ret;
299}
300
fbc4b8af 301static int asix_write_hwaddr_common(struct ueth_data *dev, uint8_t *enetaddr)
58f8fab8 302{
58f8fab8
LS		 303 int ret;
304 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN);
305
fbc4b8af 306 memcpy(buf, enetaddr, ETH_ALEN);
58f8fab8
LS		 307
308 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, buf);
309 if (ret < 0)
310 debug("Failed to set MAC address: %02x\n", ret);
311
312 return ret;
313}
314
9b70e007
SG		 315/*
316 * mii commands
317 */
318
319/*
320 * mii_nway_restart - restart NWay (autonegotiation) for this interface
321 *
322 * Returns 0 on success, negative on error.
323 */
324static int mii_nway_restart(struct ueth_data *dev)
325{
326 int bmcr;
327 int r = -1;
328
329 /* if autoneg is off, it's an error */
330 bmcr = asix_mdio_read(dev, dev->phy_id, MII_BMCR);
331
332 if (bmcr & BMCR_ANENABLE) {
333 bmcr |= BMCR_ANRESTART;
334 asix_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr);
335 r = 0;
336 }
337
338 return r;
339}
340
fbc4b8af
SG		 341static int asix_read_mac_common(struct ueth_data *dev,
342 struct asix_private *priv, uint8_t *enetaddr)
02c8d8cc 343{
02c8d8cc 344 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN);
fbc4b8af 345 int i;
02c8d8cc
LS		 346
347 if (priv->flags & FLAG_EEPROM_MAC) {
348 for (i = 0; i < (ETH_ALEN >> 1); i++) {
349 if (asix_read_cmd(dev, AX_CMD_READ_EEPROM,
350 0x04 + i, 0, 2, buf) < 0) {
351 debug("Failed to read SROM address 04h.\n");
352 return -1;
353 }
fbc4b8af 354 memcpy(enetaddr + i * 2, buf, 2);
02c8d8cc
LS		 355 }
356 } else {
357 if (asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf)
358 < 0) {
359 debug("Failed to read MAC address.\n");
360 return -1;
361 }
fbc4b8af 362 memcpy(enetaddr, buf, ETH_ALEN);
02c8d8cc
LS		 363 }
364
365 return 0;
366}
367
5fae53d0 368static int asix_basic_reset(struct ueth_data *dev)
9b70e007
SG		 369{
370 int embd_phy;
9b70e007 371 u16 rx_ctl;
9b70e007
SG		 372
373 if (asix_write_gpio(dev,
374 AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5) < 0)
5fae53d0 375 return -1;
9b70e007
SG		 376
377 /* 0x10 is the phy id of the embedded 10/100 ethernet phy */
378 embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0);
379 if (asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT,
380 embd_phy, 0, 0, NULL) < 0) {
381 debug("Select PHY #1 failed\n");
5fae53d0 382 return -1;
9b70e007
SG		 383 }
384
385 if (asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL) < 0)
5fae53d0 386 return -1;
9b70e007
SG		 387
388 if (asix_sw_reset(dev, AX_SWRESET_CLEAR) < 0)
5fae53d0 389 return -1;
9b70e007
SG		 390
391 if (embd_phy) {
392 if (asix_sw_reset(dev, AX_SWRESET_IPRL) < 0)
5fae53d0 393 return -1;
9b70e007
SG		 394 } else {
395 if (asix_sw_reset(dev, AX_SWRESET_PRTE) < 0)
5fae53d0 396 return -1;
9b70e007
SG		 397 }
398
399 rx_ctl = asix_read_rx_ctl(dev);
400 debug("RX_CTL is 0x%04x after software reset\n", rx_ctl);
401 if (asix_write_rx_ctl(dev, 0x0000) < 0)
5fae53d0 402 return -1;
9b70e007
SG		 403
404 rx_ctl = asix_read_rx_ctl(dev);
405 debug("RX_CTL is 0x%04x setting to 0x0000\n", rx_ctl);
406
9b70e007
SG		 407 dev->phy_id = asix_get_phy_addr(dev);
408 if (dev->phy_id < 0)
409 debug("Failed to read phy id\n");
410
9b70e007
SG		 411 asix_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET);
412 asix_mdio_write(dev, dev->phy_id, MII_ADVERTISE,
413 ADVERTISE_ALL | ADVERTISE_CSMA);
414 mii_nway_restart(dev);
415
416 if (asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT) < 0)
4edcf0a3 417 return -1;
9b70e007
SG		 418
419 if (asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
420 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
421 AX88772_IPG2_DEFAULT, 0, NULL) < 0) {
422 debug("Write IPG,IPG1,IPG2 failed\n");
4edcf0a3 423 return -1;
9b70e007
SG		 424 }
425
4edcf0a3
JW		 426 return 0;
427}
428
14727120 429static int asix_init_common(struct ueth_data *dev, uint8_t *enetaddr)
4edcf0a3 430{
4edcf0a3
JW		 431 int timeout = 0;
432#define TIMEOUT_RESOLUTION 50 /* ms */
433 int link_detected;
14727120 434 u32 ctl = AX_DEFAULT_RX_CTL;
4edcf0a3
JW		 435
436 debug("** %s()\n", __func__);
437
14727120
MZ		 438 if ((dev->pusb_dev->descriptor.idVendor == ASIX_USB_VENDOR_ID) &&
439 (dev->pusb_dev->descriptor.idProduct == AX88772B_USB_PRODUCT_ID))
440 ctl |= AX_RX_HEADER_DEFAULT;
441
442 if (asix_write_rx_ctl(dev, ctl) < 0)
443 goto out_err;
444
445 if (asix_write_hwaddr_common(dev, enetaddr) < 0)
9b70e007
SG		 446 goto out_err;
447
448 do {
449 link_detected = asix_mdio_read(dev, dev->phy_id, MII_BMSR) &
450 BMSR_LSTATUS;
451 if (!link_detected) {
452 if (timeout == 0)
453 printf("Waiting for Ethernet connection... ");
454 udelay(TIMEOUT_RESOLUTION * 1000);
455 timeout += TIMEOUT_RESOLUTION;
456 }
457 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
458 if (link_detected) {
459 if (timeout != 0)
460 printf("done.\n");
461 } else {
462 printf("unable to connect.\n");
463 goto out_err;
464 }
465
14727120
MZ		 466 /*
467 * Wait some more to avoid timeout on first transfer
468 * (e.g. EHCI timed out on TD - token=0x8008d80)
469 */
470 mdelay(25);
471
9b70e007
SG		 472 return 0;
473out_err:
474 return -1;
475}
476
fbc4b8af 477static int asix_send_common(struct ueth_data *dev, void *packet, int length)
9b70e007 478{
9b70e007
SG		 479 int err;
480 u32 packet_len;
481 int actual_len;
c59ab092
MV		 482 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
483 PKTSIZE + sizeof(packet_len));
9b70e007
SG		 484
485 debug("** %s(), len %d\n", __func__, length);
486
487 packet_len = (((length) ^ 0x0000ffff) << 16) + (length);
488 cpu_to_le32s(&packet_len);
489
490 memcpy(msg, &packet_len, sizeof(packet_len));
491 memcpy(msg + sizeof(packet_len), (void *)packet, length);
9b70e007
SG		 492
493 err = usb_bulk_msg(dev->pusb_dev,
494 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
495 (void *)msg,
496 length + sizeof(packet_len),
497 &actual_len,
498 USB_BULK_SEND_TIMEOUT);
4c5998b7 499 debug("Tx: len = %zu, actual = %u, err = %d\n",
9b70e007
SG		 500 length + sizeof(packet_len), actual_len, err);
501
502 return err;
503}
504
fbc4b8af
SG		 505#ifndef CONFIG_DM_ETH
506/*
507 * Asix callbacks
508 */
509static int asix_init(struct eth_device *eth, bd_t *bd)
510{
511 struct ueth_data *dev = (struct ueth_data *)eth->priv;
512
14727120 513 return asix_init_common(dev, eth->enetaddr);
fbc4b8af
SG		 514}
515
516static int asix_send(struct eth_device *eth, void *packet, int length)
517{
518 struct ueth_data *dev = (struct ueth_data *)eth->priv;
519
520 return asix_send_common(dev, packet, length);
521}
522
9b70e007
SG		 523static int asix_recv(struct eth_device *eth)
524{
525 struct ueth_data *dev = (struct ueth_data *)eth->priv;
c59ab092 526 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, AX_RX_URB_SIZE);
9b70e007
SG		 527 unsigned char *buf_ptr;
528 int err;
529 int actual_len;
530 u32 packet_len;
531
532 debug("** %s()\n", __func__);
533
534 err = usb_bulk_msg(dev->pusb_dev,
535 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
536 (void *)recv_buf,
537 AX_RX_URB_SIZE,
538 &actual_len,
539 USB_BULK_RECV_TIMEOUT);
540 debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE,
541 actual_len, err);
542 if (err != 0) {
543 debug("Rx: failed to receive\n");
544 return -1;
545 }
546 if (actual_len > AX_RX_URB_SIZE) {
547 debug("Rx: received too many bytes %d\n", actual_len);
548 return -1;
549 }
550
551 buf_ptr = recv_buf;
552 while (actual_len > 0) {
553 /*
554 * 1st 4 bytes contain the length of the actual data as two
555 * complementary 16-bit words. Extract the length of the data.
556 */
557 if (actual_len < sizeof(packet_len)) {
558 debug("Rx: incomplete packet length\n");
559 return -1;
560 }
561 memcpy(&packet_len, buf_ptr, sizeof(packet_len));
562 le32_to_cpus(&packet_len);
1dff9d0f 563 if (((~packet_len >> 16) & 0x7ff) != (packet_len & 0x7ff)) {
9b70e007 564 debug("Rx: malformed packet length: %#x (%#x:%#x)\n",
1dff9d0f
LS		 565 packet_len, (~packet_len >> 16) & 0x7ff,
566 packet_len & 0x7ff);
9b70e007
SG		 567 return -1;
568 }
1dff9d0f 569 packet_len = packet_len & 0x7ff;
9b70e007
SG		 570 if (packet_len > actual_len - sizeof(packet_len)) {
571 debug("Rx: too large packet: %d\n", packet_len);
572 return -1;
573 }
574
14727120
MZ		 575 if ((dev->pusb_dev->descriptor.idVendor ==
576 ASIX_USB_VENDOR_ID) &&
577 (dev->pusb_dev->descriptor.idProduct ==
578 AX88772B_USB_PRODUCT_ID))
579 buf_ptr += 2;
580
9b70e007 581 /* Notify net stack */
1fd92db8
JH		 582 net_process_received_packet(buf_ptr + sizeof(packet_len),
583 packet_len);
9b70e007
SG		 584
585 /* Adjust for next iteration. Packets are padded to 16-bits */
586 if (packet_len & 1)
587 packet_len++;
588 actual_len -= sizeof(packet_len) + packet_len;
589 buf_ptr += sizeof(packet_len) + packet_len;
590 }
591
592 return err;
593}
594
595static void asix_halt(struct eth_device *eth)
596{
597 debug("** %s()\n", __func__);
598}
599
fbc4b8af
SG		 600static int asix_write_hwaddr(struct eth_device *eth)
601{
602 struct ueth_data *dev = (struct ueth_data *)eth->priv;
603
604 return asix_write_hwaddr_common(dev, eth->enetaddr);
605}
606
9b70e007
SG		 607/*
608 * Asix probing functions
609 */
610void asix_eth_before_probe(void)
611{
612 curr_eth_dev = 0;
613}
614
615struct asix_dongle {
616 unsigned short vendor;
617 unsigned short product;
58f8fab8 618 int flags;
9b70e007
SG		 619};
620
51afc2c6 621static const struct asix_dongle asix_dongles[] = {
58f8fab8
LS		 622 { 0x05ac, 0x1402, FLAG_TYPE_AX88772 }, /* Apple USB Ethernet Adapter */
623 { 0x07d1, 0x3c05, FLAG_TYPE_AX88772 }, /* D-Link DUB-E100 H/W Ver B1 */
befd3872 624 { 0x2001, 0x1a02, FLAG_TYPE_AX88772 }, /* D-Link DUB-E100 H/W Ver C1 */
58f8fab8
LS		 625 /* Cables-to-Go USB Ethernet Adapter */
626 { 0x0b95, 0x772a, FLAG_TYPE_AX88772 },
627 { 0x0b95, 0x7720, FLAG_TYPE_AX88772 }, /* Trendnet TU2-ET100 V3.0R */
628 { 0x0b95, 0x1720, FLAG_TYPE_AX88172 }, /* SMC */
629 { 0x0db0, 0xa877, FLAG_TYPE_AX88772 }, /* MSI - ASIX 88772a */
630 { 0x13b1, 0x0018, FLAG_TYPE_AX88172 }, /* Linksys 200M v2.1 */
631 { 0x1557, 0x7720, FLAG_TYPE_AX88772 }, /* 0Q0 cable ethernet */
632 /* DLink DUB-E100 H/W Ver B1 Alternate */
633 { 0x2001, 0x3c05, FLAG_TYPE_AX88772 },
1dff9d0f
LS		 634 /* ASIX 88772B */
635 { 0x0b95, 0x772b, FLAG_TYPE_AX88772B | FLAG_EEPROM_MAC },
a7f24722 636 { 0x0b95, 0x7e2b, FLAG_TYPE_AX88772B },
58f8fab8 637 { 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */
9b70e007
SG		 638};
639
640/* Probe to see if a new device is actually an asix device */
641int asix_eth_probe(struct usb_device *dev, unsigned int ifnum,
642 struct ueth_data *ss)
643{
644 struct usb_interface *iface;
645 struct usb_interface_descriptor *iface_desc;
1dff9d0f 646 int ep_in_found = 0, ep_out_found = 0;
9b70e007
SG		 647 int i;
648
649 /* let's examine the device now */
650 iface = &dev->config.if_desc[ifnum];
651 iface_desc = &dev->config.if_desc[ifnum].desc;
652
653 for (i = 0; asix_dongles[i].vendor != 0; i++) {
654 if (dev->descriptor.idVendor == asix_dongles[i].vendor &&
655 dev->descriptor.idProduct == asix_dongles[i].product)
656 /* Found a supported dongle */
657 break;
658 }
659
660 if (asix_dongles[i].vendor == 0)
661 return 0;
662
663 memset(ss, 0, sizeof(struct ueth_data));
664
665 /* At this point, we know we've got a live one */
666 debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
667 dev->descriptor.idVendor, dev->descriptor.idProduct);
668
669 /* Initialize the ueth_data structure with some useful info */
670 ss->ifnum = ifnum;
671 ss->pusb_dev = dev;
672 ss->subclass = iface_desc->bInterfaceSubClass;
673 ss->protocol = iface_desc->bInterfaceProtocol;
674
58f8fab8
LS		 675 /* alloc driver private */
676 ss->dev_priv = calloc(1, sizeof(struct asix_private));
677 if (!ss->dev_priv)
678 return 0;
679
680 ((struct asix_private *)ss->dev_priv)->flags = asix_dongles[i].flags;
681
9b70e007
SG		 682 /*
683 * We are expecting a minimum of 3 endpoints - in, out (bulk), and
684 * int. We will ignore any others.
685 */
686 for (i = 0; i < iface_desc->bNumEndpoints; i++) {
687 /* is it an BULK endpoint? */
688 if ((iface->ep_desc[i].bmAttributes &
689 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
1dff9d0f
LS		 690 u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
691 if (ep_addr & USB_DIR_IN) {
692 if (!ep_in_found) {
693 ss->ep_in = ep_addr &
694 USB_ENDPOINT_NUMBER_MASK;
695 ep_in_found = 1;
696 }
697 } else {
698 if (!ep_out_found) {
699 ss->ep_out = ep_addr &
700 USB_ENDPOINT_NUMBER_MASK;
701 ep_out_found = 1;
702 }
703 }
9b70e007
SG		 704 }
705
706 /* is it an interrupt endpoint? */
707 if ((iface->ep_desc[i].bmAttributes &
708 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
709 ss->ep_int = iface->ep_desc[i].bEndpointAddress &
710 USB_ENDPOINT_NUMBER_MASK;
711 ss->irqinterval = iface->ep_desc[i].bInterval;
712 }
713 }
714 debug("Endpoints In %d Out %d Int %d\n",
715 ss->ep_in, ss->ep_out, ss->ep_int);
716
717 /* Do some basic sanity checks, and bail if we find a problem */
718 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
719 !ss->ep_in || !ss->ep_out || !ss->ep_int) {
720 debug("Problems with device\n");
721 return 0;
722 }
723 dev->privptr = (void *)ss;
724 return 1;
725}
726
727int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
728 struct eth_device *eth)
729{
58f8fab8
LS		 730 struct asix_private *priv = (struct asix_private *)ss->dev_priv;
731
9b70e007
SG		 732 if (!eth) {
733 debug("%s: missing parameter.\n", __func__);
734 return 0;
735 }
736 sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++);
737 eth->init = asix_init;
738 eth->send = asix_send;
739 eth->recv = asix_recv;
740 eth->halt = asix_halt;
58f8fab8
LS		 741 if (!(priv->flags & FLAG_TYPE_AX88172))
742 eth->write_hwaddr = asix_write_hwaddr;
9b70e007
SG		 743 eth->priv = ss;
744
5fae53d0
LS		 745 if (asix_basic_reset(ss))
746 return 0;
747
02c8d8cc 748 /* Get the MAC address */
fbc4b8af 749 if (asix_read_mac_common(ss, priv, eth->enetaddr))
02c8d8cc
LS		 750 return 0;
751 debug("MAC %pM\n", eth->enetaddr);
752
9b70e007
SG		 753 return 1;
754}
fbc4b8af
SG		 755#endif
756
757#ifdef CONFIG_DM_ETH
758static int asix_eth_start(struct udevice *dev)
759{
14727120 760 struct eth_pdata *pdata = dev_get_platdata(dev);
fbc4b8af
SG		 761 struct asix_private *priv = dev_get_priv(dev);
762
14727120 763 return asix_init_common(&priv->ueth, pdata->enetaddr);
fbc4b8af
SG		 764}
765
766void asix_eth_stop(struct udevice *dev)
767{
768 debug("** %s()\n", __func__);
769}
770
771int asix_eth_send(struct udevice *dev, void *packet, int length)
772{
773 struct asix_private *priv = dev_get_priv(dev);
774
775 return asix_send_common(&priv->ueth, packet, length);
776}
777
778int asix_eth_recv(struct udevice *dev, int flags, uchar **packetp)
779{
780 struct asix_private *priv = dev_get_priv(dev);
781 struct ueth_data *ueth = &priv->ueth;
782 uint8_t *ptr;
783 int ret, len;
784 u32 packet_len;
785
786 len = usb_ether_get_rx_bytes(ueth, &ptr);
787 debug("%s: first try, len=%d\n", __func__, len);
788 if (!len) {
789 if (!(flags & ETH_RECV_CHECK_DEVICE))
790 return -EAGAIN;
791 ret = usb_ether_receive(ueth, AX_RX_URB_SIZE);
792 if (ret == -EAGAIN)
793 return ret;
794
795 len = usb_ether_get_rx_bytes(ueth, &ptr);
796 debug("%s: second try, len=%d\n", __func__, len);
797 }
798
799 /*
800 * 1st 4 bytes contain the length of the actual data as two
801 * complementary 16-bit words. Extract the length of the data.
802 */
803 if (len < sizeof(packet_len)) {
804 debug("Rx: incomplete packet length\n");
805 goto err;
806 }
807 memcpy(&packet_len, ptr, sizeof(packet_len));
808 le32_to_cpus(&packet_len);
809 if (((~packet_len >> 16) & 0x7ff) != (packet_len & 0x7ff)) {
810 debug("Rx: malformed packet length: %#x (%#x:%#x)\n",
811 packet_len, (~packet_len >> 16) & 0x7ff,
812 packet_len & 0x7ff);
813 goto err;
814 }
815 packet_len = packet_len & 0x7ff;
816 if (packet_len > len - sizeof(packet_len)) {
817 debug("Rx: too large packet: %d\n", packet_len);
818 goto err;
819 }
820
821 *packetp = ptr + sizeof(packet_len);
822 return packet_len;
823
824err:
825 usb_ether_advance_rxbuf(ueth, -1);
826 return -EINVAL;
827}
828
829static int asix_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
830{
831 struct asix_private *priv = dev_get_priv(dev);
832
833 if (packet_len & 1)
834 packet_len++;
835 usb_ether_advance_rxbuf(&priv->ueth, sizeof(u32) + packet_len);
836
837 return 0;
838}
839
840int asix_write_hwaddr(struct udevice *dev)
841{
842 struct eth_pdata *pdata = dev_get_platdata(dev);
843 struct asix_private *priv = dev_get_priv(dev);
844
845 if (priv->flags & FLAG_TYPE_AX88172)
846 return -ENOSYS;
847
848 return asix_write_hwaddr_common(&priv->ueth, pdata->enetaddr);
849}
850
851static int asix_eth_probe(struct udevice *dev)
852{
853 struct eth_pdata *pdata = dev_get_platdata(dev);
854 struct asix_private *priv = dev_get_priv(dev);
855 struct ueth_data *ss = &priv->ueth;
856 int ret;
857
858 priv->flags = dev->driver_data;
859 ret = usb_ether_register(dev, ss, AX_RX_URB_SIZE);
860 if (ret)
861 return ret;
862
863 ret = asix_basic_reset(ss);
864 if (ret)
865 goto err;
866
867 /* Get the MAC address */
868 ret = asix_read_mac_common(ss, priv, pdata->enetaddr);
869 if (ret)
870 goto err;
871 debug("MAC %pM\n", pdata->enetaddr);
872
873 return 0;
874
875err:
876 return usb_ether_deregister(ss);
877}
878
879static const struct eth_ops asix_eth_ops = {
880 .start = asix_eth_start,
881 .send = asix_eth_send,
882 .recv = asix_eth_recv,
883 .free_pkt = asix_free_pkt,
884 .stop = asix_eth_stop,
885 .write_hwaddr = asix_write_hwaddr,
886};
887
888U_BOOT_DRIVER(asix_eth) = {
889 .name = "asix_eth",
890 .id = UCLASS_ETH,
891 .probe = asix_eth_probe,
892 .ops = &asix_eth_ops,
893 .priv_auto_alloc_size = sizeof(struct asix_private),
894 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
895};
896
897static const struct usb_device_id asix_eth_id_table[] = {
898 /* Apple USB Ethernet Adapter */
899 { USB_DEVICE(0x05ac, 0x1402), .driver_info = FLAG_TYPE_AX88772 },
900 /* D-Link DUB-E100 H/W Ver B1 */
901 { USB_DEVICE(0x07d1, 0x3c05), .driver_info = FLAG_TYPE_AX88772 },
902 /* D-Link DUB-E100 H/W Ver C1 */
903 { USB_DEVICE(0x2001, 0x1a02), .driver_info = FLAG_TYPE_AX88772 },
904 /* Cables-to-Go USB Ethernet Adapter */
905 { USB_DEVICE(0x0b95, 0x772a), .driver_info = FLAG_TYPE_AX88772 },
906 /* Trendnet TU2-ET100 V3.0R */
907 { USB_DEVICE(0x0b95, 0x7720), .driver_info = FLAG_TYPE_AX88772 },
908 /* SMC */
909 { USB_DEVICE(0x0b95, 0x1720), .driver_info = FLAG_TYPE_AX88172 },
910 /* MSI - ASIX 88772a */
911 { USB_DEVICE(0x0db0, 0xa877), .driver_info = FLAG_TYPE_AX88772 },
912 /* Linksys 200M v2.1 */
913 { USB_DEVICE(0x13b1, 0x0018), .driver_info = FLAG_TYPE_AX88172 },
914 /* 0Q0 cable ethernet */
915 { USB_DEVICE(0x1557, 0x7720), .driver_info = FLAG_TYPE_AX88772 },
916 /* DLink DUB-E100 H/W Ver B1 Alternate */
917 { USB_DEVICE(0x2001, 0x3c05), .driver_info = FLAG_TYPE_AX88772 },
918 /* ASIX 88772B */
919 { USB_DEVICE(0x0b95, 0x772b),
920 .driver_info = FLAG_TYPE_AX88772B | FLAG_EEPROM_MAC },
921 { USB_DEVICE(0x0b95, 0x7e2b), .driver_info = FLAG_TYPE_AX88772B },
922 { } /* Terminating entry */
923};
924
925U_BOOT_USB_DEVICE(asix_eth, asix_eth_id_table);
926#endif
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