[J-u-boot.git] / board / gen860t / ioport.c

/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc8xx.h>
#include <asm/8xx_immap.h>
#include "ioport.h"

#if 0
#define IOPORT_DEBUG
#endif

#ifdef  IOPORT_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif

/*
 * The ioport configuration table.
 */
const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = {
    /*
	 * Port A configuration
	 * Pin	Signal					Type	Active	Initial state
	 * PA7	fpgaProgramLowOut		Out		Low			High
	 * PA1	fpgaCoreVoltageFailLow	In		Low			N/A
	 */
    {	/*	    conf ppar psor pdir podr pdat pint	   function		*/
	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /* No pin			*/
	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /* No pin			*/
	/* PA15 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PA14 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PA13 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PA12 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PA11 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PA10 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PA9  */ { 1,   0,   0,   1,   0,   0,   0 }, /* grn bicolor LED 1*/
	/* PA8  */ { 1,   0,   0,   1,   0,   0,   0 }, /* red bicolor LED 1*/
	/* PA7  */ { 1,   0,   0,   1,   0,   1,   0 }, /* fpgaProgramLow	*/
	/* PA6  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PA5  */ { 1,   0,   0,   1,   0,   0,   0 }, /* grn bicolor LED 0*/
	/* PA4  */ { 1,   0,   0,   1,   0,   0,   0 }, /* red bicolor LED 0*/
	/* PA3  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PA2  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
#if !defined(CONFIG_SC)
	/* PA1  */ { 1,   0,   0,   0,   0,   0,   0 }, /*	fpgaCoreVoltageFail*/
#else
	/* PA1  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
#endif
	/* PA0  */ { 0,   0,   0,   0,   0,   0,   0 }  /*	*/
    },

	/*
	 * Port B configuration
	 * Pin		Signal			Type		Active		Initial state
	 * PB14		docBusyLowIn	In			Low			X
	 * PB15		gpio1Sig		Out			High		Low
	 * PB16		fpgaDoneBi		In			High		X
	 * PB17		swBitOkLowOut	Out			Low			High
	 * PB19		speakerVolSig	Out/Hi-Z	High/Low	High (Hi-Z)
	 * PB22		fpgaInitLowBi	In			Low			X
	 * PB23		batteryOkSig	In			High		X
	 * PB31		pulseCatcherClr	Out			High		0
	 */
	{	/*	    conf ppar psor pdir podr pdat pint	  function			*/
#if !defined(CONFIG_SC)
	/* PB31 */ { 0,	  0,   0,   0,   0,   0,   0 }, /*	*/
#else
	/* PB31 */ { 1,   0,   0,   1,   0,   0,   0 }, /* pulseCatcherClr	*/
#endif
	/* PB30 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PB29 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PB28 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PB27 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PB26 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PB25 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PB24 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
#if !defined(CONFIG_SC)
	/* PB23 */ { 1,   0,   0,   0,   0,   0,   0 }, /* batteryOk		*/
#else
	/* PB23 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
#endif
	/* PB22 */ { 1,   0,   0,   0,   0,   0,   0 }, /* fpgaInitLowBi	*/
	/* PB21 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PB20 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
#if !defined(CONFIG_SC)
	/* PB19 */ { 1,   0,   0,   1,   1,   1,   0 }, /* speakerVol		*/
#else
	/* PB19 */ { 0,   0,   0,   1,   1,   1,   0 }, /*	*/
#endif
	/* PB18 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PB17 */ { 1,   0,   0,   1,   0,   1,   0 }, /* swBitOkLow		*/
	/* PB16 */ { 1,   0,   0,   0,   0,   0,   0 }, /* fpgaDone			*/
	/* PB15 */ { 1,   0,   0,   1,   0,   0,   0 }, /* gpio1			*/
#if !defined(CONFIG_SC)
	/* PB14 */ { 1,   0,   0,   0,   0,   0,   0 }  /* docBusyLow		*/
#else
	/* PB14 */ { 0,   0,   0,   0,   0,   0,   0 }  /*	*/
#endif
	},

	/*
	 * Port C configuration
	 * Pin		Signal				Type	Active		Initial state
	 * PC4		i2cBus1EnSig		Out		High		High
	 * PC5		i2cBus2EnSig		Out		High		High
	 * PC6		gpio0Sig			Out		High		Low
	 * PC8		i2cBus3EnSig		Out		High		High
	 * PC10		i2cBus4EnSig		Out		High		High
	 * PC11		fpgaResetLowOut		Out		Low			High
	 * PC12		systemBitOkIn		In		High		X
	 * PC15		selfDreqLow			In		Low			X
	 */
	{	/*	    conf ppar psor pdir podr pdat pint	  function			*/
	/* N/A	*/ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* N/A	*/ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PC15 */ { 1,   0,   0,   0,   0,   0,   0 }, /* selfDreqLowIn	*/
	/* PC14 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PC13 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
#if !defined(CONFIG_SC)
	/* PC12 */ { 1,   0,   0,   0,   0,   0,   0 }, /* systemBitOkIn	*/
#else
	/* PC12 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
#endif
	/* PC11 */ { 1,   0,   0,   1,   0,   1,   0 }, /* fpgaResetLowOut	*/
#if !defined(CONFIG_SC)
	/* PC10 */ { 1,   0,   0,   1,   0,   1,   0 }, /* i2cBus4EnSig		*/
#else
	/* PC10 */ { 0,   0,   0,   1,   0,   1,   0 }, /*	*/
#endif
	/* PC9  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
#if !defined(CONFIG_SC)
	/* PC8  */ { 1,   0,   0,   1,   0,   1,   0 }, /* i2cBus3EnSig		*/
#else
	/* PC8  */ { 0,   0,   0,   1,   0,   1,   0 }, /*	*/
#endif
	/* PC7  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PC6  */ { 1,   0,   0,   1,   0,   1,   0 }, /* gpio0			*/
#if !defined(CONFIG_SC)
	/* PC5  */ { 1,   0,   0,   1,   0,   1,   0 }, /* i2cBus2EnSig		*/
	/* PC4  */ { 1,   0,   0,   1,   0,   1,   0 }, /* i2cBus1EnSig		*/
#else
	/* PC5  */ { 0,   0,   0,   1,   0,   1,   0 }, /*	*/
	/* PC4  */ { 0,   0,   0,   1,   0,   1,   0 }, /*	*/
#endif
	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }  /*	*/
	},

	/*
	 * Port D configuration
	 */
	{	/*	    conf ppar psor pdir podr pdat pint	   function			*/
	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PD15 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PD14 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PD13 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PD12 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PD11 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PD10 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PD9  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PD8  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PD7  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PD6  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PD5  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PD4  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* PD3  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }  /*	*/
	}
};

/*
 * Configure the MPC8XX I/O ports per the ioport configuration table
 * (taken from ./arch/powerpc/cpu/mpc8260/cpu_init.c)
 */
void config_mpc8xx_ioports (volatile immap_t * immr)
{
	int portnum;

	for (portnum = 0; portnum < NUM_PORTS; portnum++) {
		uint pmsk = 0, ppar = 0, psor = 0, pdir = 0;
		uint podr = 0, pdat = 0, pint = 0;
		uint msk = 1;
		mpc8xx_iop_conf_t *iopc =
			(mpc8xx_iop_conf_t *) & iop_conf_tab[portnum][0];
		mpc8xx_iop_conf_t *eiopc = iopc + PORT_BITS;

		/*
		 * For all ports except port B, ignore the two don't care entries
		 * in the configuration tables.
		 */
		if (portnum != 1) {
			iopc = (mpc8xx_iop_conf_t *) &
				iop_conf_tab[portnum][2];
		}

		/*
		 * NOTE: index 0 refers to pin 17, index 17 refers to pin 0
		 */
		while (iopc < eiopc) {
			if (iopc->conf) {
				pmsk |= msk;
				if (iopc->ppar)
					ppar |= msk;
				if (iopc->psor)
					psor |= msk;
				if (iopc->pdir)
					pdir |= msk;
				if (iopc->podr)
					podr |= msk;
				if (iopc->pdat)
					pdat |= msk;
				if (iopc->pint)
					pint |= msk;
			}
			msk <<= 1;
			iopc++;
		}

		PRINTF ("%s:%d:\n  portnum=%d ", __FUNCTION__, __LINE__,
			portnum);
#ifdef IOPORT_DEBUG
		switch (portnum) {
		case 0:
			printf ("(A)\n");
			break;
		case 1:
			printf ("(B)\n");
			break;
		case 2:
			printf ("(C)\n");
			break;
		case 3:
			printf ("(D)\n");
			break;
		default:
			printf ("(?)\n");
			break;
		}
#endif
		PRINTF ("  ppar=0x%.8x  pdir=0x%.8x  podr=0x%.8x\n"
			"  pdat=0x%.8x  psor=0x%.8x  pint=0x%.8x  pmsk=0x%.8x\n",
			ppar, pdir, podr, pdat, psor, pint, pmsk);

		/*
		 * Have to handle the ioports on a port-by-port basis since there
		 * are three different flavors.
		 */
		if (pmsk != 0) {
			uint tpmsk = ~pmsk;

			if (0 == portnum) {	/* port A */
				immr->im_ioport.iop_papar &= tpmsk;
				immr->im_ioport.iop_padat =
					(immr->im_ioport.
					 iop_padat & tpmsk) | pdat;
				immr->im_ioport.iop_padir =
					(immr->im_ioport.
					 iop_padir & tpmsk) | pdir;
				immr->im_ioport.iop_paodr =
					(immr->im_ioport.
					 iop_paodr & tpmsk) | podr;
				immr->im_ioport.iop_papar |= ppar;
			} else if (1 == portnum) {	/* port B */
				immr->im_cpm.cp_pbpar &= tpmsk;
				immr->im_cpm.cp_pbdat =
					(immr->im_cpm.
					 cp_pbdat & tpmsk) | pdat;
				immr->im_cpm.cp_pbdir =
					(immr->im_cpm.
					 cp_pbdir & tpmsk) | pdir;
				immr->im_cpm.cp_pbodr =
					(immr->im_cpm.
					 cp_pbodr & tpmsk) | podr;
				immr->im_cpm.cp_pbpar |= ppar;
			} else if (2 == portnum) {	/* port C */
				immr->im_ioport.iop_pcpar &= tpmsk;
				immr->im_ioport.iop_pcdat =
					(immr->im_ioport.
					 iop_pcdat & tpmsk) | pdat;
				immr->im_ioport.iop_pcdir =
					(immr->im_ioport.
					 iop_pcdir & tpmsk) | pdir;
				immr->im_ioport.iop_pcint =
					(immr->im_ioport.
					 iop_pcint & tpmsk) | pint;
				immr->im_ioport.iop_pcso =
					(immr->im_ioport.
					 iop_pcso & tpmsk) | psor;
				immr->im_ioport.iop_pcpar |= ppar;
			} else if (3 == portnum) {	/* port D */
				immr->im_ioport.iop_pdpar &= tpmsk;
				immr->im_ioport.iop_pddat =
					(immr->im_ioport.
					 iop_pddat & tpmsk) | pdat;
				immr->im_ioport.iop_pddir =
					(immr->im_ioport.
					 iop_pddir & tpmsk) | pdir;
				immr->im_ioport.iop_pdpar |= ppar;
			}
		}
	}

	PRINTF ("%s:%d: Port A:\n  papar=0x%.4x  padir=0x%.4x"
		"  paodr=0x%.4x\n  padat=0x%.4x\n", __FUNCTION__, __LINE__,
		immr->im_ioport.iop_papar, immr->im_ioport.iop_padir,
		immr->im_ioport.iop_paodr, immr->im_ioport.iop_padat);
	PRINTF ("%s:%d: Port B:\n  pbpar=0x%.8x  pbdir=0x%.8x"
		"  pbodr=0x%.8x\n  pbdat=0x%.8x\n", __FUNCTION__, __LINE__,
		immr->im_cpm.cp_pbpar, immr->im_cpm.cp_pbdir,
		immr->im_cpm.cp_pbodr, immr->im_cpm.cp_pbdat);
	PRINTF ("%s:%d: Port C:\n  pcpar=0x%.4x  pcdir=0x%.4x"
		"  pcdat=0x%.4x\n  pcso=0x%.4x  pcint=0x%.4x\n  ",
		__FUNCTION__, __LINE__, immr->im_ioport.iop_pcpar,
		immr->im_ioport.iop_pcdir, immr->im_ioport.iop_pcdat,
		immr->im_ioport.iop_pcso, immr->im_ioport.iop_pcint);
	PRINTF ("%s:%d: Port D:\n  pdpar=0x%.4x  pddir=0x%.4x"
		"  pddat=0x%.4x\n", __FUNCTION__, __LINE__,
		immr->im_ioport.iop_pdpar, immr->im_ioport.iop_pddir,
		immr->im_ioport.iop_pddat);
}
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2000
	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <mpc8xx.h>
	26	#include <asm/8xx_immap.h>
	27	#include "ioport.h"
	28
	29	#if 0
	30	#define IOPORT_DEBUG
	31	#endif
	32
	33	#ifdef IOPORT_DEBUG
	34	#define PRINTF(fmt,args...) printf (fmt ,##args)
	35	#else
	36	#define PRINTF(fmt,args...)
	37	#endif
	38
	39	/*
	40	* The ioport configuration table.
	41	*/
	42	const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = {
	43	/*
	44	* Port A configuration
7aa78614	45	* Pin Signal Type Active Initial state
53677ef1 WD	46	* PA7 fpgaProgramLowOut Out Low High
53677ef1 WD	47	* PA1 fpgaCoreVoltageFailLow In Low N/A
c609719b	48	*/
53677ef1	49	{ /* conf ppar psor pdir podr pdat pint function */
c609719b WD	50	/* N/A / { 0, 0, 0, 0, 0, 0, 0 }, / No pin */
	51	/* N/A / { 0, 0, 0, 0, 0, 0, 0 }, / No pin */
	52	/* PA15 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	53	/* PA14 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	54	/* PA13 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	55	/* PA12 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	56	/* PA11 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	57	/* PA10 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	58	/* PA9 / { 1, 0, 0, 1, 0, 0, 0 }, / grn bicolor LED 1*/
	59	/* PA8 / { 1, 0, 0, 1, 0, 0, 0 }, / red bicolor LED 1*/
	60	/* PA7 / { 1, 0, 0, 1, 0, 1, 0 }, / fpgaProgramLow */
	61	/* PA6 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	62	/* PA5 / { 1, 0, 0, 1, 0, 0, 0 }, / grn bicolor LED 0*/
	63	/* PA4 / { 1, 0, 0, 1, 0, 0, 0 }, / red bicolor LED 0*/
	64	/* PA3 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	65	/* PA2 / { 0, 0, 0, 0, 0, 0, 0 }, / */
7aa78614 WD	66	#if !defined(CONFIG_SC)
	67	/* PA1 / { 1, 0, 0, 0, 0, 0, 0 }, / fpgaCoreVoltageFail*/
	68	#else
c609719b	69	/* PA1 / { 0, 0, 0, 0, 0, 0, 0 }, / */
7aa78614	70	#endif
c609719b WD	71	/* PA0 / { 0, 0, 0, 0, 0, 0, 0 } / */
	72	},
	73
	74	/*
7aa78614	75	* Port B configuration
c609719b WD	76	* Pin Signal Type Active Initial state
	77	* PB14 docBusyLowIn In Low X
	78	* PB15 gpio1Sig Out High Low
	79	* PB16 fpgaDoneBi In High X
7aa78614	80	* PB17 swBitOkLowOut Out Low High
c609719b WD	81	* PB19 speakerVolSig Out/Hi-Z High/Low High (Hi-Z)
	82	* PB22 fpgaInitLowBi In Low X
	83	* PB23 batteryOkSig In High X
7aa78614 WD	84	* PB31 pulseCatcherClr Out High 0
7aa78614 WD	85	*/
53677ef1	86	{ /* conf ppar psor pdir podr pdat pint function */
7aa78614 WD	87	#if !defined(CONFIG_SC)
	88	/* PB31 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	89	#else
	90	/* PB31 / { 1, 0, 0, 1, 0, 0, 0 }, / pulseCatcherClr */
	91	#endif
c609719b WD	92	/* PB30 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	93	/* PB29 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	94	/* PB28 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	95	/* PB27 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	96	/* PB26 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	97	/* PB25 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	98	/* PB24 / { 0, 0, 0, 0, 0, 0, 0 }, / */
7aa78614	99	#if !defined(CONFIG_SC)
c609719b	100	/* PB23 / { 1, 0, 0, 0, 0, 0, 0 }, / batteryOk */
7aa78614 WD	101	#else
	102	/* PB23 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	103	#endif
c609719b WD	104	/* PB22 / { 1, 0, 0, 0, 0, 0, 0 }, / fpgaInitLowBi */
	105	/* PB21 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	106	/* PB20 / { 0, 0, 0, 0, 0, 0, 0 }, / */
7aa78614	107	#if !defined(CONFIG_SC)
c609719b	108	/* PB19 / { 1, 0, 0, 1, 1, 1, 0 }, / speakerVol */
7aa78614 WD	109	#else
	110	/* PB19 / { 0, 0, 0, 1, 1, 1, 0 }, / */
	111	#endif
c609719b	112	/* PB18 / { 0, 0, 0, 0, 0, 0, 0 }, / */
7aa78614	113	/* PB17 / { 1, 0, 0, 1, 0, 1, 0 }, / swBitOkLow */
c609719b WD	114	/* PB16 / { 1, 0, 0, 0, 0, 0, 0 }, / fpgaDone */
c609719b WD	115	/* PB15 / { 1, 0, 0, 1, 0, 0, 0 }, / gpio1 */
7aa78614	116	#if !defined(CONFIG_SC)
c609719b	117	/* PB14 / { 1, 0, 0, 0, 0, 0, 0 } / docBusyLow */
7aa78614	118	#else
53677ef1	119	/* PB14 / { 0, 0, 0, 0, 0, 0, 0 } / */
7aa78614 WD	120	#endif
7aa78614 WD	121	},
c609719b WD	122
c609719b WD	123	/*
7aa78614	124	* Port C configuration
c609719b WD	125	* Pin Signal Type Active Initial state
	126	* PC4 i2cBus1EnSig Out High High
	127	* PC5 i2cBus2EnSig Out High High
	128	* PC6 gpio0Sig Out High Low
	129	* PC8 i2cBus3EnSig Out High High
	130	* PC10 i2cBus4EnSig Out High High
	131	* PC11 fpgaResetLowOut Out Low High
	132	* PC12 systemBitOkIn In High X
	133	* PC15 selfDreqLow In Low X
	134	*/
53677ef1	135	{ /* conf ppar psor pdir podr pdat pint function */
c609719b WD	136	/* N/A / { 0, 0, 0, 0, 0, 0, 0 }, / */
	137	/* N/A / { 0, 0, 0, 0, 0, 0, 0 }, / */
	138	/* PC15 / { 1, 0, 0, 0, 0, 0, 0 }, / selfDreqLowIn */
	139	/* PC14 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	140	/* PC13 / { 0, 0, 0, 0, 0, 0, 0 }, / */
7aa78614	141	#if !defined(CONFIG_SC)
c609719b	142	/* PC12 / { 1, 0, 0, 0, 0, 0, 0 }, / systemBitOkIn */
7aa78614	143	#else
53677ef1	144	/* PC12 / { 0, 0, 0, 0, 0, 0, 0 }, / */
7aa78614	145	#endif
c609719b	146	/* PC11 / { 1, 0, 0, 1, 0, 1, 0 }, / fpgaResetLowOut */
7aa78614	147	#if !defined(CONFIG_SC)
c609719b	148	/* PC10 / { 1, 0, 0, 1, 0, 1, 0 }, / i2cBus4EnSig */
7aa78614 WD	149	#else
	150	/* PC10 / { 0, 0, 0, 1, 0, 1, 0 }, / */
	151	#endif
c609719b	152	/* PC9 / { 0, 0, 0, 0, 0, 0, 0 }, / */
7aa78614	153	#if !defined(CONFIG_SC)
c609719b	154	/* PC8 / { 1, 0, 0, 1, 0, 1, 0 }, / i2cBus3EnSig */
7aa78614 WD	155	#else
	156	/* PC8 / { 0, 0, 0, 1, 0, 1, 0 }, / */
	157	#endif
c609719b WD	158	/* PC7 / { 0, 0, 0, 0, 0, 0, 0 }, / */
c609719b WD	159	/* PC6 / { 1, 0, 0, 1, 0, 1, 0 }, / gpio0 */
7aa78614	160	#if !defined(CONFIG_SC)
c609719b WD	161	/* PC5 / { 1, 0, 0, 1, 0, 1, 0 }, / i2cBus2EnSig */
c609719b WD	162	/* PC4 / { 1, 0, 0, 1, 0, 1, 0 }, / i2cBus1EnSig */
7aa78614 WD	163	#else
	164	/* PC5 / { 0, 0, 0, 1, 0, 1, 0 }, / */
	165	/* PC4 / { 0, 0, 0, 1, 0, 1, 0 }, / */
	166	#endif
c609719b WD	167	/* N/A / { 0, 0, 0, 0, 0, 0, 0 }, / */
	168	/* N/A / { 0, 0, 0, 0, 0, 0, 0 }, / */
	169	/* N/A / { 0, 0, 0, 0, 0, 0, 0 }, / */
	170	/* N/A / { 0, 0, 0, 0, 0, 0, 0 } / */
7aa78614	171	},
c609719b	172
7aa78614 WD	173	/*
	174	* Port D configuration
	175	*/
53677ef1	176	{ /* conf ppar psor pdir podr pdat pint function */
c609719b WD	177	/* N/A / { 0, 0, 0, 0, 0, 0, 0 }, / */
	178	/* N/A / { 0, 0, 0, 0, 0, 0, 0 }, / */
	179	/* PD15 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	180	/* PD14 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	181	/* PD13 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	182	/* PD12 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	183	/* PD11 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	184	/* PD10 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	185	/* PD9 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	186	/* PD8 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	187	/* PD7 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	188	/* PD6 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	189	/* PD5 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	190	/* PD4 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	191	/* PD3 / { 0, 0, 0, 0, 0, 0, 0 }, / */
	192	/* N/A / { 0, 0, 0, 0, 0, 0, 0 }, / */
	193	/* N/A / { 0, 0, 0, 0, 0, 0, 0 }, / */
	194	/* N/A / { 0, 0, 0, 0, 0, 0, 0 } / */
7aa78614	195	}
c609719b WD	196	};
	197
	198	/*
	199	* Configure the MPC8XX I/O ports per the ioport configuration table
a47a12be	200	* (taken from ./arch/powerpc/cpu/mpc8260/cpu_init.c)
c609719b	201	*/
bf9e3b38	202	void config_mpc8xx_ioports (volatile immap_t * immr)
c609719b	203	{
bf9e3b38	204	int portnum;
c609719b	205
bf9e3b38	206	for (portnum = 0; portnum < NUM_PORTS; portnum++) {
c609719b WD	207	uint pmsk = 0, ppar = 0, psor = 0, pdir = 0;
	208	uint podr = 0, pdat = 0, pint = 0;
	209	uint msk = 1;
bf9e3b38 WD	210	mpc8xx_iop_conf_t *iopc =
bf9e3b38 WD	211	(mpc8xx_iop_conf_t *) & iop_conf_tab[portnum][0];
c609719b WD	212	mpc8xx_iop_conf_t *eiopc = iopc + PORT_BITS;
	213
	214	/*
	215	* For all ports except port B, ignore the two don't care entries
	216	* in the configuration tables.
	217	*/
	218	if (portnum != 1) {
bf9e3b38 WD	219	iopc = (mpc8xx_iop_conf_t *) &
bf9e3b38 WD	220	iop_conf_tab[portnum][2];
c609719b WD	221	}
	222
	223	/*
	224	* NOTE: index 0 refers to pin 17, index 17 refers to pin 0
	225	*/
	226	while (iopc < eiopc) {
bf9e3b38	227	if (iopc->conf) {
c609719b	228	pmsk \|= msk;
bf9e3b38 WD	229	if (iopc->ppar)
	230	ppar \|= msk;
	231	if (iopc->psor)
	232	psor \|= msk;
	233	if (iopc->pdir)
	234	pdir \|= msk;
	235	if (iopc->podr)
	236	podr \|= msk;
	237	if (iopc->pdat)
	238	pdat \|= msk;
	239	if (iopc->pint)
	240	pint \|= msk;
	241	}
	242	msk <<= 1;
	243	iopc++;
c609719b WD	244	}
c609719b WD	245
bf9e3b38 WD	246	PRINTF ("%s:%d:\n portnum=%d ", __FUNCTION__, __LINE__,
bf9e3b38 WD	247	portnum);
c609719b	248	#ifdef IOPORT_DEBUG
bf9e3b38 WD	249	switch (portnum) {
	250	case 0:
	251	printf ("(A)\n");
	252	break;
	253	case 1:
	254	printf ("(B)\n");
	255	break;
	256	case 2:
	257	printf ("(C)\n");
	258	break;
	259	case 3:
	260	printf ("(D)\n");
	261	break;
	262	default:
	263	printf ("(?)\n");
	264	break;
c609719b WD	265	}
c609719b WD	266	#endif
bf9e3b38 WD	267	PRINTF (" ppar=0x%.8x pdir=0x%.8x podr=0x%.8x\n"
	268	" pdat=0x%.8x psor=0x%.8x pint=0x%.8x pmsk=0x%.8x\n",
	269	ppar, pdir, podr, pdat, psor, pint, pmsk);
c609719b WD	270
	271	/*
	272	* Have to handle the ioports on a port-by-port basis since there
	273	* are three different flavors.
	274	*/
	275	if (pmsk != 0) {
bf9e3b38	276	uint tpmsk = ~pmsk;
c609719b	277
bf9e3b38 WD	278	if (0 == portnum) { /* port A */
	279	immr->im_ioport.iop_papar &= tpmsk;
	280	immr->im_ioport.iop_padat =
	281	(immr->im_ioport.
	282	iop_padat & tpmsk) \| pdat;
	283	immr->im_ioport.iop_padir =
	284	(immr->im_ioport.
	285	iop_padir & tpmsk) \| pdir;
	286	immr->im_ioport.iop_paodr =
	287	(immr->im_ioport.
	288	iop_paodr & tpmsk) \| podr;
	289	immr->im_ioport.iop_papar \|= ppar;
	290	} else if (1 == portnum) { /* port B */
	291	immr->im_cpm.cp_pbpar &= tpmsk;
	292	immr->im_cpm.cp_pbdat =
	293	(immr->im_cpm.
	294	cp_pbdat & tpmsk) \| pdat;
	295	immr->im_cpm.cp_pbdir =
	296	(immr->im_cpm.
	297	cp_pbdir & tpmsk) \| pdir;
	298	immr->im_cpm.cp_pbodr =
	299	(immr->im_cpm.
	300	cp_pbodr & tpmsk) \| podr;
	301	immr->im_cpm.cp_pbpar \|= ppar;
	302	} else if (2 == portnum) { /* port C */
	303	immr->im_ioport.iop_pcpar &= tpmsk;
	304	immr->im_ioport.iop_pcdat =
	305	(immr->im_ioport.
	306	iop_pcdat & tpmsk) \| pdat;
	307	immr->im_ioport.iop_pcdir =
	308	(immr->im_ioport.
	309	iop_pcdir & tpmsk) \| pdir;
	310	immr->im_ioport.iop_pcint =
	311	(immr->im_ioport.
	312	iop_pcint & tpmsk) \| pint;
	313	immr->im_ioport.iop_pcso =
	314	(immr->im_ioport.
	315	iop_pcso & tpmsk) \| psor;
	316	immr->im_ioport.iop_pcpar \|= ppar;
	317	} else if (3 == portnum) { /* port D */
	318	immr->im_ioport.iop_pdpar &= tpmsk;
	319	immr->im_ioport.iop_pddat =
	320	(immr->im_ioport.
	321	iop_pddat & tpmsk) \| pdat;
	322	immr->im_ioport.iop_pddir =
	323	(immr->im_ioport.
	324	iop_pddir & tpmsk) \| pdir;
	325	immr->im_ioport.iop_pdpar \|= ppar;
c609719b WD	326	}
c609719b WD	327	}
bf9e3b38	328	}
c609719b	329
bf9e3b38 WD	330	PRINTF ("%s:%d: Port A:\n papar=0x%.4x padir=0x%.4x"
	331	" paodr=0x%.4x\n padat=0x%.4x\n", __FUNCTION__, __LINE__,
	332	immr->im_ioport.iop_papar, immr->im_ioport.iop_padir,
	333	immr->im_ioport.iop_paodr, immr->im_ioport.iop_padat);
	334	PRINTF ("%s:%d: Port B:\n pbpar=0x%.8x pbdir=0x%.8x"
	335	" pbodr=0x%.8x\n pbdat=0x%.8x\n", __FUNCTION__, __LINE__,
	336	immr->im_cpm.cp_pbpar, immr->im_cpm.cp_pbdir,
	337	immr->im_cpm.cp_pbodr, immr->im_cpm.cp_pbdat);
	338	PRINTF ("%s:%d: Port C:\n pcpar=0x%.4x pcdir=0x%.4x"
	339	" pcdat=0x%.4x\n pcso=0x%.4x pcint=0x%.4x\n ",
	340	__FUNCTION__, __LINE__, immr->im_ioport.iop_pcpar,
	341	immr->im_ioport.iop_pcdir, immr->im_ioport.iop_pcdat,
	342	immr->im_ioport.iop_pcso, immr->im_ioport.iop_pcint);
	343	PRINTF ("%s:%d: Port D:\n pdpar=0x%.4x pddir=0x%.4x"
	344	" pddat=0x%.4x\n", __FUNCTION__, __LINE__,
	345	immr->im_ioport.iop_pdpar, immr->im_ioport.iop_pddir,
	346	immr->im_ioport.iop_pddat);
c609719b	347	}