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Merge branch 'master' of git://git.denx.de/u-boot-socfpga
[J-u-boot.git] / drivers / ata / sata_mv.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
169789dc
TK		 2/*
3 * Copyright (C) Excito Elektronik i Skåne AB, 2010.
4 * Author: Tor Krill <[email protected]>
5 *
0506620f 6 * Copyright (C) 2015, 2019 Stefan Roese <[email protected]>
169789dc
TK		 7 */
8
9/*
10 * This driver supports the SATA controller of some Mavell SoC's.
11 * Here a (most likely incomplete) list of the supported SoC's:
12 * - Kirkwood
13 * - Armada 370
14 * - Armada XP
15 *
16 * This driver implementation is an alternative to the already available
17 * driver via the "ide" commands interface (drivers/block/mvsata_ide.c).
18 * But this driver only supports PIO mode and as this new driver also
19 * supports transfer via DMA, its much faster.
20 *
21 * Please note, that the newer SoC's (e.g. Armada 38x) are not supported
22 * by this driver. As they have an AHCI compatible SATA controller
23 * integrated.
24 */
25
26/*
27 * TODO:
28 * Better error recovery
29 * No support for using PRDs (Thus max 64KB transfers)
30 * No NCQ support
31 * No port multiplier support
32 */
33
34#include <common.h>
0506620f 35#include <ahci.h>
1eb69ae4 36#include <cpu_func.h>
0506620f
SR		 37#include <dm.h>
38#include <dm/device-internal.h>
39#include <dm/lists.h>
169789dc
TK		 40#include <fis.h>
41#include <libata.h>
42#include <malloc.h>
43#include <sata.h>
1221ce45 44#include <linux/errno.h>
169789dc
TK		 45#include <asm/io.h>
46#include <linux/mbus.h>
47
6d294971 48#include <asm/arch/soc.h>
169789dc 49#if defined(CONFIG_KIRKWOOD)
169789dc
TK		 50#define SATAHC_BASE KW_SATA_BASE
51#else
169789dc
TK		 52#define SATAHC_BASE MVEBU_AXP_SATA_BASE
53#endif
54
55#define SATA0_BASE (SATAHC_BASE + 0x2000)
56#define SATA1_BASE (SATAHC_BASE + 0x4000)
57
58/* EDMA registers */
59#define EDMA_CFG 0x000
60#define EDMA_CFG_NCQ (1 << 5)
61#define EDMA_CFG_EQUE (1 << 9)
62#define EDMA_TIMER 0x004
63#define EDMA_IECR 0x008
64#define EDMA_IEMR 0x00c
65#define EDMA_RQBA_HI 0x010
66#define EDMA_RQIPR 0x014
67#define EDMA_RQIPR_IPMASK (0x1f << 5)
68#define EDMA_RQIPR_IPSHIFT 5
69#define EDMA_RQOPR 0x018
70#define EDMA_RQOPR_OPMASK (0x1f << 5)
71#define EDMA_RQOPR_OPSHIFT 5
72#define EDMA_RSBA_HI 0x01c
73#define EDMA_RSIPR 0x020
74#define EDMA_RSIPR_IPMASK (0x1f << 3)
75#define EDMA_RSIPR_IPSHIFT 3
76#define EDMA_RSOPR 0x024
77#define EDMA_RSOPR_OPMASK (0x1f << 3)
78#define EDMA_RSOPR_OPSHIFT 3
79#define EDMA_CMD 0x028
80#define EDMA_CMD_ENEDMA (0x01 << 0)
81#define EDMA_CMD_DISEDMA (0x01 << 1)
82#define EDMA_CMD_ATARST (0x01 << 2)
83#define EDMA_CMD_FREEZE (0x01 << 4)
84#define EDMA_TEST_CTL 0x02c
85#define EDMA_STATUS 0x030
86#define EDMA_IORTO 0x034
87#define EDMA_CDTR 0x040
88#define EDMA_HLTCND 0x060
89#define EDMA_NTSR 0x094
90
91/* Basic DMA registers */
92#define BDMA_CMD 0x224
93#define BDMA_STATUS 0x228
94#define BDMA_DTLB 0x22c
95#define BDMA_DTHB 0x230
96#define BDMA_DRL 0x234
97#define BDMA_DRH 0x238
98
99/* SATA Interface registers */
100#define SIR_ICFG 0x050
101#define SIR_CFG_GEN2EN (0x1 << 7)
102#define SIR_PLL_CFG 0x054
103#define SIR_SSTATUS 0x300
104#define SSTATUS_DET_MASK (0x0f << 0)
105#define SIR_SERROR 0x304
106#define SIR_SCONTROL 0x308
107#define SIR_SCONTROL_DETEN (0x01 << 0)
108#define SIR_LTMODE 0x30c
109#define SIR_LTMODE_NELBE (0x01 << 7)
110#define SIR_PHYMODE3 0x310
111#define SIR_PHYMODE4 0x314
112#define SIR_PHYMODE1 0x32c
113#define SIR_PHYMODE2 0x330
114#define SIR_BIST_CTRL 0x334
115#define SIR_BIST_DW1 0x338
116#define SIR_BIST_DW2 0x33c
117#define SIR_SERR_IRQ_MASK 0x340
118#define SIR_SATA_IFCTRL 0x344
119#define SIR_SATA_TESTCTRL 0x348
120#define SIR_SATA_IFSTATUS 0x34c
121#define SIR_VEND_UNIQ 0x35c
122#define SIR_FIS_CFG 0x360
123#define SIR_FIS_IRQ_CAUSE 0x364
124#define SIR_FIS_IRQ_MASK 0x368
125#define SIR_FIS_DWORD0 0x370
126#define SIR_FIS_DWORD1 0x374
127#define SIR_FIS_DWORD2 0x378
128#define SIR_FIS_DWORD3 0x37c
129#define SIR_FIS_DWORD4 0x380
130#define SIR_FIS_DWORD5 0x384
131#define SIR_FIS_DWORD6 0x388
132#define SIR_PHYM9_GEN2 0x398
133#define SIR_PHYM9_GEN1 0x39c
134#define SIR_PHY_CFG 0x3a0
135#define SIR_PHYCTL 0x3a4
136#define SIR_PHYM10 0x3a8
137#define SIR_PHYM12 0x3b0
138
139/* Shadow registers */
140#define PIO_DATA 0x100
141#define PIO_ERR_FEATURES 0x104
142#define PIO_SECTOR_COUNT 0x108
143#define PIO_LBA_LOW 0x10c
144#define PIO_LBA_MID 0x110
145#define PIO_LBA_HI 0x114
146#define PIO_DEVICE 0x118
147#define PIO_CMD_STATUS 0x11c
148#define PIO_STATUS_ERR (0x01 << 0)
149#define PIO_STATUS_DRQ (0x01 << 3)
150#define PIO_STATUS_DF (0x01 << 5)
151#define PIO_STATUS_DRDY (0x01 << 6)
152#define PIO_STATUS_BSY (0x01 << 7)
153#define PIO_CTRL_ALTSTAT 0x120
154
155/* SATAHC arbiter registers */
156#define SATAHC_CFG 0x000
157#define SATAHC_RQOP 0x004
158#define SATAHC_RQIP 0x008
159#define SATAHC_ICT 0x00c
160#define SATAHC_ITT 0x010
161#define SATAHC_ICR 0x014
162#define SATAHC_ICR_PORT0 (0x01 << 0)
163#define SATAHC_ICR_PORT1 (0x01 << 1)
164#define SATAHC_MIC 0x020
165#define SATAHC_MIM 0x024
166#define SATAHC_LED_CFG 0x02c
167
168#define REQUEST_QUEUE_SIZE 32
169#define RESPONSE_QUEUE_SIZE REQUEST_QUEUE_SIZE
170
171struct crqb {
172 u32 dtb_low; /* DW0 */
173 u32 dtb_high; /* DW1 */
174 u32 control_flags; /* DW2 */
175 u32 drb_count; /* DW3 */
176 u32 ata_cmd_feat; /* DW4 */
177 u32 ata_addr; /* DW5 */
178 u32 ata_addr_exp; /* DW6 */
179 u32 ata_sect_count; /* DW7 */
180};
181
182#define CRQB_ALIGN 0x400
183
184#define CRQB_CNTRLFLAGS_DIR (0x01 << 0)
185#define CRQB_CNTRLFLAGS_DQTAGMASK (0x1f << 1)
186#define CRQB_CNTRLFLAGS_DQTAGSHIFT 1
187#define CRQB_CNTRLFLAGS_PMPORTMASK (0x0f << 12)
188#define CRQB_CNTRLFLAGS_PMPORTSHIFT 12
189#define CRQB_CNTRLFLAGS_PRDMODE (0x01 << 16)
190#define CRQB_CNTRLFLAGS_HQTAGMASK (0x1f << 17)
191#define CRQB_CNTRLFLAGS_HQTAGSHIFT 17
192
193#define CRQB_CMDFEAT_CMDMASK (0xff << 16)
194#define CRQB_CMDFEAT_CMDSHIFT 16
195#define CRQB_CMDFEAT_FEATMASK (0xff << 16)
196#define CRQB_CMDFEAT_FEATSHIFT 24
197
198#define CRQB_ADDR_LBA_LOWMASK (0xff << 0)
199#define CRQB_ADDR_LBA_LOWSHIFT 0
200#define CRQB_ADDR_LBA_MIDMASK (0xff << 8)
201#define CRQB_ADDR_LBA_MIDSHIFT 8
202#define CRQB_ADDR_LBA_HIGHMASK (0xff << 16)
203#define CRQB_ADDR_LBA_HIGHSHIFT 16
204#define CRQB_ADDR_DEVICE_MASK (0xff << 24)
205#define CRQB_ADDR_DEVICE_SHIFT 24
206
207#define CRQB_ADDR_LBA_LOW_EXP_MASK (0xff << 0)
208#define CRQB_ADDR_LBA_LOW_EXP_SHIFT 0
209#define CRQB_ADDR_LBA_MID_EXP_MASK (0xff << 8)
210#define CRQB_ADDR_LBA_MID_EXP_SHIFT 8
211#define CRQB_ADDR_LBA_HIGH_EXP_MASK (0xff << 16)
212#define CRQB_ADDR_LBA_HIGH_EXP_SHIFT 16
213#define CRQB_ADDR_FEATURE_EXP_MASK (0xff << 24)
214#define CRQB_ADDR_FEATURE_EXP_SHIFT 24
215
216#define CRQB_SECTCOUNT_COUNT_MASK (0xff << 0)
217#define CRQB_SECTCOUNT_COUNT_SHIFT 0
218#define CRQB_SECTCOUNT_COUNT_EXP_MASK (0xff << 8)
219#define CRQB_SECTCOUNT_COUNT_EXP_SHIFT 8
220
6d294971
MW		 221#define MVSATA_WIN_CONTROL(w) (SATAHC_BASE + 0x30 + ((w) << 4))
222#define MVSATA_WIN_BASE(w) (SATAHC_BASE + 0x34 + ((w) << 4))
169789dc
TK		 223
224struct eprd {
225 u32 phyaddr_low;
226 u32 bytecount_eot;
227 u32 phyaddr_hi;
228 u32 reserved;
229};
230
231#define EPRD_PHYADDR_MASK 0xfffffffe
232#define EPRD_BYTECOUNT_MASK 0x0000ffff
233#define EPRD_EOT (0x01 << 31)
234
235struct crpb {
236 u32 id;
237 u32 flags;
238 u32 timestamp;
239};
240
241#define CRPB_ALIGN 0x100
242
243#define READ_CMD 0
244#define WRITE_CMD 1
245
246/*
247 * Since we don't use PRDs yet max transfer size
248 * is 64KB
249 */
250#define MV_ATA_MAX_SECTORS (65535 / ATA_SECT_SIZE)
251
252/* Keep track if hw is initialized or not */
253static u32 hw_init;
254
255struct mv_priv {
256 char name[12];
257 u32 link;
258 u32 regbase;
259 u32 queue_depth;
260 u16 pio;
261 u16 mwdma;
262 u16 udma;
0506620f 263 int dev_nr;
169789dc
TK		 264
265 void *crqb_alloc;
266 struct crqb *request;
267
268 void *crpb_alloc;
269 struct crpb *response;
270};
271
272static int ata_wait_register(u32 *addr, u32 mask, u32 val, u32 timeout_msec)
273{
274 ulong start;
275
276 start = get_timer(0);
277 do {
278 if ((in_le32(addr) & mask) == val)
279 return 0;
280 } while (get_timer(start) < timeout_msec);
281
282 return -ETIMEDOUT;
283}
284
285/* Cut from sata_mv in linux kernel */
0506620f 286static int mv_stop_edma_engine(struct udevice *dev, int port)
169789dc 287{
0506620f 288 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 289 int i;
290
291 /* Disable eDMA. The disable bit auto clears. */
292 out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_DISEDMA);
293
294 /* Wait for the chip to confirm eDMA is off. */
295 for (i = 10000; i > 0; i--) {
296 u32 reg = in_le32(priv->regbase + EDMA_CMD);
297 if (!(reg & EDMA_CMD_ENEDMA)) {
298 debug("EDMA stop on port %d succesful\n", port);
299 return 0;
300 }
301 udelay(10);
302 }
303 debug("EDMA stop on port %d failed\n", port);
304 return -1;
305}
306
0506620f 307static int mv_start_edma_engine(struct udevice *dev, int port)
169789dc 308{
0506620f 309 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 310 u32 tmp;
311
312 /* Check preconditions */
313 tmp = in_le32(priv->regbase + SIR_SSTATUS);
314 if ((tmp & SSTATUS_DET_MASK) != 0x03) {
315 printf("Device error on port: %d\n", port);
316 return -1;
317 }
318
319 tmp = in_le32(priv->regbase + PIO_CMD_STATUS);
320 if (tmp & (ATA_BUSY | ATA_DRQ)) {
321 printf("Device not ready on port: %d\n", port);
322 return -1;
323 }
324
325 /* Clear interrupt cause */
326 out_le32(priv->regbase + EDMA_IECR, 0x0);
327
328 tmp = in_le32(SATAHC_BASE + SATAHC_ICR);
329 tmp &= ~(port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1);
330 out_le32(SATAHC_BASE + SATAHC_ICR, tmp);
331
332 /* Configure edma operation */
333 tmp = in_le32(priv->regbase + EDMA_CFG);
334 tmp &= ~EDMA_CFG_NCQ; /* No NCQ */
335 tmp &= ~EDMA_CFG_EQUE; /* Dont queue operations */
336 out_le32(priv->regbase + EDMA_CFG, tmp);
337
338 out_le32(priv->regbase + SIR_FIS_IRQ_CAUSE, 0x0);
339
340 /* Configure fis, set all to no-wait for now */
341 out_le32(priv->regbase + SIR_FIS_CFG, 0x0);
342
343 /* Setup request queue */
344 out_le32(priv->regbase + EDMA_RQBA_HI, 0x0);
345 out_le32(priv->regbase + EDMA_RQIPR, priv->request);
346 out_le32(priv->regbase + EDMA_RQOPR, 0x0);
347
348 /* Setup response queue */
349 out_le32(priv->regbase + EDMA_RSBA_HI, 0x0);
350 out_le32(priv->regbase + EDMA_RSOPR, priv->response);
351 out_le32(priv->regbase + EDMA_RSIPR, 0x0);
352
353 /* Start edma */
354 out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ENEDMA);
355
356 return 0;
357}
358
0506620f 359static int mv_reset_channel(struct udevice *dev, int port)
169789dc 360{
0506620f 361 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 362
363 /* Make sure edma is stopped */
0506620f 364 mv_stop_edma_engine(dev, port);
169789dc
TK		 365
366 out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ATARST);
367 udelay(25); /* allow reset propagation */
368 out_le32(priv->regbase + EDMA_CMD, 0);
369 mdelay(10);
370
371 return 0;
372}
373
0506620f 374static void mv_reset_port(struct udevice *dev, int port)
169789dc 375{
0506620f 376 struct mv_priv *priv = dev_get_platdata(dev);
169789dc 377
0506620f 378 mv_reset_channel(dev, port);
169789dc
TK		 379
380 out_le32(priv->regbase + EDMA_CMD, 0x0);
381 out_le32(priv->regbase + EDMA_CFG, 0x101f);
382 out_le32(priv->regbase + EDMA_IECR, 0x0);
383 out_le32(priv->regbase + EDMA_IEMR, 0x0);
384 out_le32(priv->regbase + EDMA_RQBA_HI, 0x0);
385 out_le32(priv->regbase + EDMA_RQIPR, 0x0);
386 out_le32(priv->regbase + EDMA_RQOPR, 0x0);
387 out_le32(priv->regbase + EDMA_RSBA_HI, 0x0);
388 out_le32(priv->regbase + EDMA_RSIPR, 0x0);
389 out_le32(priv->regbase + EDMA_RSOPR, 0x0);
390 out_le32(priv->regbase + EDMA_IORTO, 0xfa);
391}
392
393static void mv_reset_one_hc(void)
394{
395 out_le32(SATAHC_BASE + SATAHC_ICT, 0x00);
396 out_le32(SATAHC_BASE + SATAHC_ITT, 0x00);
397 out_le32(SATAHC_BASE + SATAHC_ICR, 0x00);
398}
399
0506620f 400static int probe_port(struct udevice *dev, int port)
169789dc 401{
0506620f 402 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 403 int tries, tries2, set15 = 0;
404 u32 tmp;
405
406 debug("Probe port: %d\n", port);
407
408 for (tries = 0; tries < 2; tries++) {
409 /* Clear SError */
410 out_le32(priv->regbase + SIR_SERROR, 0x0);
411
412 /* trigger com-init */
413 tmp = in_le32(priv->regbase + SIR_SCONTROL);
414 tmp = (tmp & 0x0f0) | 0x300 | SIR_SCONTROL_DETEN;
415 out_le32(priv->regbase + SIR_SCONTROL, tmp);
416
417 mdelay(1);
418
419 tmp = in_le32(priv->regbase + SIR_SCONTROL);
420 tries2 = 5;
421 do {
422 tmp = (tmp & 0x0f0) | 0x300;
423 out_le32(priv->regbase + SIR_SCONTROL, tmp);
424 mdelay(10);
425 tmp = in_le32(priv->regbase + SIR_SCONTROL);
426 } while ((tmp & 0xf0f) != 0x300 && tries2--);
427
428 mdelay(10);
429
430 for (tries2 = 0; tries2 < 200; tries2++) {
431 tmp = in_le32(priv->regbase + SIR_SSTATUS);
432 if ((tmp & SSTATUS_DET_MASK) == 0x03) {
433 debug("Found device on port\n");
434 return 0;
435 }
436 mdelay(1);
437 }
438
439 if ((tmp & SSTATUS_DET_MASK) == 0) {
440 debug("No device attached on port %d\n", port);
441 return -ENODEV;
442 }
443
444 if (!set15) {
445 /* Try on 1.5Gb/S */
446 debug("Try 1.5Gb link\n");
447 set15 = 1;
448 out_le32(priv->regbase + SIR_SCONTROL, 0x304);
449
450 tmp = in_le32(priv->regbase + SIR_ICFG);
451 tmp &= ~SIR_CFG_GEN2EN;
452 out_le32(priv->regbase + SIR_ICFG, tmp);
453
0506620f 454 mv_reset_channel(dev, port);
169789dc
TK		 455 }
456 }
457
458 debug("Failed to probe port\n");
459 return -1;
460}
461
462/* Get request queue in pointer */
0506620f 463static int get_reqip(struct udevice *dev, int port)
169789dc 464{
0506620f 465 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 466 u32 tmp;
467
468 tmp = in_le32(priv->regbase + EDMA_RQIPR) & EDMA_RQIPR_IPMASK;
469 tmp = tmp >> EDMA_RQIPR_IPSHIFT;
470
471 return tmp;
472}
473
0506620f 474static void set_reqip(struct udevice *dev, int port, int reqin)
169789dc 475{
0506620f 476 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 477 u32 tmp;
478
479 tmp = in_le32(priv->regbase + EDMA_RQIPR) & ~EDMA_RQIPR_IPMASK;
480 tmp |= ((reqin << EDMA_RQIPR_IPSHIFT) & EDMA_RQIPR_IPMASK);
481 out_le32(priv->regbase + EDMA_RQIPR, tmp);
482}
483
484/* Get next available slot, ignoring possible overwrite */
0506620f 485static int get_next_reqip(struct udevice *dev, int port)
169789dc 486{
0506620f 487 int slot = get_reqip(dev, port);
169789dc
TK		 488 slot = (slot + 1) % REQUEST_QUEUE_SIZE;
489 return slot;
490}
491
492/* Get response queue in pointer */
0506620f 493static int get_rspip(struct udevice *dev, int port)
169789dc 494{
0506620f 495 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 496 u32 tmp;
497
498 tmp = in_le32(priv->regbase + EDMA_RSIPR) & EDMA_RSIPR_IPMASK;
499 tmp = tmp >> EDMA_RSIPR_IPSHIFT;
500
501 return tmp;
502}
503
504/* Get response queue out pointer */
0506620f 505static int get_rspop(struct udevice *dev, int port)
169789dc 506{
0506620f 507 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 508 u32 tmp;
509
510 tmp = in_le32(priv->regbase + EDMA_RSOPR) & EDMA_RSOPR_OPMASK;
511 tmp = tmp >> EDMA_RSOPR_OPSHIFT;
512 return tmp;
513}
514
515/* Get next response queue pointer */
0506620f 516static int get_next_rspop(struct udevice *dev, int port)
169789dc 517{
0506620f 518 return (get_rspop(dev, port) + 1) % RESPONSE_QUEUE_SIZE;
169789dc
TK		 519}
520
521/* Set response queue pointer */
0506620f 522static void set_rspop(struct udevice *dev, int port, int reqin)
169789dc 523{
0506620f 524 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 525 u32 tmp;
526
527 tmp = in_le32(priv->regbase + EDMA_RSOPR) & ~EDMA_RSOPR_OPMASK;
528 tmp |= ((reqin << EDMA_RSOPR_OPSHIFT) & EDMA_RSOPR_OPMASK);
529
530 out_le32(priv->regbase + EDMA_RSOPR, tmp);
531}
532
0506620f
SR		 533static int wait_dma_completion(struct udevice *dev, int port, int index,
534 u32 timeout_msec)
169789dc
TK		 535{
536 u32 tmp, res;
537
538 tmp = port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1;
539 res = ata_wait_register((u32 *)(SATAHC_BASE + SATAHC_ICR), tmp,
540 tmp, timeout_msec);
541 if (res)
542 printf("Failed to wait for completion on port %d\n", port);
543
544 return res;
545}
546
0506620f 547static void process_responses(struct udevice *dev, int port)
169789dc
TK		 548{
549#ifdef DEBUG
0506620f 550 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 551#endif
552 u32 tmp;
0506620f 553 u32 outind = get_rspop(dev, port);
169789dc
TK		 554
555 /* Ack interrupts */
556 tmp = in_le32(SATAHC_BASE + SATAHC_ICR);
557 if (port == 0)
558 tmp &= ~(BIT(0) | BIT(8));
559 else
560 tmp &= ~(BIT(1) | BIT(9));
561 tmp &= ~(BIT(4));
562 out_le32(SATAHC_BASE + SATAHC_ICR, tmp);
563
0506620f 564 while (get_rspip(dev, port) != outind) {
169789dc
TK		 565#ifdef DEBUG
566 debug("Response index %d flags %08x on port %d\n", outind,
567 priv->response[outind].flags, port);
568#endif
0506620f
SR		 569 outind = get_next_rspop(dev, port);
570 set_rspop(dev, port, outind);
169789dc
TK		 571 }
572}
573
0506620f
SR		 574static int mv_ata_exec_ata_cmd(struct udevice *dev, int port,
575 struct sata_fis_h2d *cfis,
169789dc
TK		 576 u8 *buffer, u32 len, u32 iswrite)
577{
0506620f 578 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 579 struct crqb *req;
580 int slot;
5102af4d 581 u32 start;
169789dc
TK		 582
583 if (len >= 64 * 1024) {
584 printf("We only support <64K transfers for now\n");
585 return -1;
586 }
587
588 /* Initialize request */
0506620f 589 slot = get_reqip(dev, port);
169789dc
TK		 590 memset(&priv->request[slot], 0, sizeof(struct crqb));
591 req = &priv->request[slot];
592
593 req->dtb_low = (u32)buffer;
594
595 /* Dont use PRDs */
596 req->control_flags = CRQB_CNTRLFLAGS_PRDMODE;
597 req->control_flags |= iswrite ? 0 : CRQB_CNTRLFLAGS_DIR;
598 req->control_flags |=
599 ((cfis->pm_port_c << CRQB_CNTRLFLAGS_PMPORTSHIFT)
600 & CRQB_CNTRLFLAGS_PMPORTMASK);
601
602 req->drb_count = len;
603
604 req->ata_cmd_feat = (cfis->command << CRQB_CMDFEAT_CMDSHIFT) &
605 CRQB_CMDFEAT_CMDMASK;
606 req->ata_cmd_feat |= (cfis->features << CRQB_CMDFEAT_FEATSHIFT) &
607 CRQB_CMDFEAT_FEATMASK;
608
609 req->ata_addr = (cfis->lba_low << CRQB_ADDR_LBA_LOWSHIFT) &
610 CRQB_ADDR_LBA_LOWMASK;
611 req->ata_addr |= (cfis->lba_mid << CRQB_ADDR_LBA_MIDSHIFT) &
612 CRQB_ADDR_LBA_MIDMASK;
613 req->ata_addr |= (cfis->lba_high << CRQB_ADDR_LBA_HIGHSHIFT) &
614 CRQB_ADDR_LBA_HIGHMASK;
615 req->ata_addr |= (cfis->device << CRQB_ADDR_DEVICE_SHIFT) &
616 CRQB_ADDR_DEVICE_MASK;
617
618 req->ata_addr_exp = (cfis->lba_low_exp << CRQB_ADDR_LBA_LOW_EXP_SHIFT) &
619 CRQB_ADDR_LBA_LOW_EXP_MASK;
620 req->ata_addr_exp |=
621 (cfis->lba_mid_exp << CRQB_ADDR_LBA_MID_EXP_SHIFT) &
622 CRQB_ADDR_LBA_MID_EXP_MASK;
623 req->ata_addr_exp |=
624 (cfis->lba_high_exp << CRQB_ADDR_LBA_HIGH_EXP_SHIFT) &
625 CRQB_ADDR_LBA_HIGH_EXP_MASK;
626 req->ata_addr_exp |=
627 (cfis->features_exp << CRQB_ADDR_FEATURE_EXP_SHIFT) &
628 CRQB_ADDR_FEATURE_EXP_MASK;
629
630 req->ata_sect_count =
631 (cfis->sector_count << CRQB_SECTCOUNT_COUNT_SHIFT) &
632 CRQB_SECTCOUNT_COUNT_MASK;
633 req->ata_sect_count |=
634 (cfis->sector_count_exp << CRQB_SECTCOUNT_COUNT_EXP_SHIFT) &
635 CRQB_SECTCOUNT_COUNT_EXP_MASK;
636
637 /* Flush data */
5102af4d
SR		 638 start = (u32)req & ~(ARCH_DMA_MINALIGN - 1);
639 flush_dcache_range(start,
640 start + ALIGN(sizeof(*req), ARCH_DMA_MINALIGN));
169789dc
TK		 641
642 /* Trigger operation */
0506620f
SR		 643 slot = get_next_reqip(dev, port);
644 set_reqip(dev, port, slot);
169789dc
TK		 645
646 /* Wait for completion */
0506620f 647 if (wait_dma_completion(dev, port, slot, 10000)) {
169789dc
TK		 648 printf("ATA operation timed out\n");
649 return -1;
650 }
651
0506620f 652 process_responses(dev, port);
169789dc
TK		 653
654 /* Invalidate data on read */
5102af4d
SR		 655 if (buffer && len) {
656 start = (u32)buffer & ~(ARCH_DMA_MINALIGN - 1);
657 invalidate_dcache_range(start,
658 start + ALIGN(len, ARCH_DMA_MINALIGN));
659 }
169789dc
TK		 660
661 return len;
662}
663
0506620f
SR		 664static u32 mv_sata_rw_cmd_ext(struct udevice *dev, int port, lbaint_t start,
665 u32 blkcnt,
169789dc
TK		 666 u8 *buffer, int is_write)
667{
668 struct sata_fis_h2d cfis;
669 u32 res;
670 u64 block;
671
672 block = (u64)start;
673
674 memset(&cfis, 0, sizeof(struct sata_fis_h2d));
675
676 cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
677 cfis.command = (is_write) ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
678
679 cfis.lba_high_exp = (block >> 40) & 0xff;
680 cfis.lba_mid_exp = (block >> 32) & 0xff;
681 cfis.lba_low_exp = (block >> 24) & 0xff;
682 cfis.lba_high = (block >> 16) & 0xff;
683 cfis.lba_mid = (block >> 8) & 0xff;
684 cfis.lba_low = block & 0xff;
685 cfis.device = ATA_LBA;
686 cfis.sector_count_exp = (blkcnt >> 8) & 0xff;
687 cfis.sector_count = blkcnt & 0xff;
688
0506620f
SR		 689 res = mv_ata_exec_ata_cmd(dev, port, &cfis, buffer,
690 ATA_SECT_SIZE * blkcnt, is_write);
169789dc
TK		 691
692 return res >= 0 ? blkcnt : res;
693}
694
0506620f
SR		 695static u32 mv_sata_rw_cmd(struct udevice *dev, int port, lbaint_t start,
696 u32 blkcnt, u8 *buffer, int is_write)
169789dc
TK		 697{
698 struct sata_fis_h2d cfis;
699 lbaint_t block;
700 u32 res;
701
702 block = start;
703
704 memset(&cfis, 0, sizeof(struct sata_fis_h2d));
705
706 cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
707 cfis.command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
708 cfis.device = ATA_LBA;
709
710 cfis.device |= (block >> 24) & 0xf;
711 cfis.lba_high = (block >> 16) & 0xff;
712 cfis.lba_mid = (block >> 8) & 0xff;
713 cfis.lba_low = block & 0xff;
714 cfis.sector_count = (u8)(blkcnt & 0xff);
715
0506620f
SR		 716 res = mv_ata_exec_ata_cmd(dev, port, &cfis, buffer,
717 ATA_SECT_SIZE * blkcnt, is_write);
169789dc
TK		 718
719 return res >= 0 ? blkcnt : res;
720}
721
0506620f
SR		 722static u32 ata_low_level_rw(struct udevice *dev, int port, lbaint_t blknr,
723 lbaint_t blkcnt, void *buffer, int is_write)
169789dc 724{
0506620f 725 struct blk_desc *desc = dev_get_uclass_platdata(dev);
169789dc
TK		 726 lbaint_t start, blks;
727 u8 *addr;
728 int max_blks;
729
cfdf632c 730 debug("%s: " LBAFU " " LBAFU "\n", __func__, blknr, blkcnt);
169789dc
TK		 731
732 start = blknr;
733 blks = blkcnt;
734 addr = (u8 *)buffer;
735
736 max_blks = MV_ATA_MAX_SECTORS;
737 do {
738 if (blks > max_blks) {
0506620f
SR		 739 if (desc->lba48) {
740 mv_sata_rw_cmd_ext(dev, port, start, max_blks,
741 addr, is_write);
169789dc 742 } else {
0506620f
SR		 743 mv_sata_rw_cmd(dev, port, start, max_blks,
744 addr, is_write);
169789dc
TK		 745 }
746 start += max_blks;
747 blks -= max_blks;
748 addr += ATA_SECT_SIZE * max_blks;
749 } else {
0506620f
SR		 750 if (desc->lba48) {
751 mv_sata_rw_cmd_ext(dev, port, start, blks, addr,
169789dc
TK		 752 is_write);
753 } else {
0506620f 754 mv_sata_rw_cmd(dev, port, start, blks, addr,
169789dc
TK		 755 is_write);
756 }
757 start += blks;
758 blks = 0;
759 addr += ATA_SECT_SIZE * blks;
760 }
761 } while (blks != 0);
762
763 return blkcnt;
764}
765
0506620f 766static int mv_ata_exec_ata_cmd_nondma(struct udevice *dev, int port,
169789dc
TK		 767 struct sata_fis_h2d *cfis, u8 *buffer,
768 u32 len, u32 iswrite)
769{
0506620f 770 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 771 int i;
772 u16 *tp;
773
774 debug("%s\n", __func__);
775
776 out_le32(priv->regbase + PIO_SECTOR_COUNT, cfis->sector_count);
777 out_le32(priv->regbase + PIO_LBA_HI, cfis->lba_high);
778 out_le32(priv->regbase + PIO_LBA_MID, cfis->lba_mid);
779 out_le32(priv->regbase + PIO_LBA_LOW, cfis->lba_low);
780 out_le32(priv->regbase + PIO_ERR_FEATURES, cfis->features);
781 out_le32(priv->regbase + PIO_DEVICE, cfis->device);
782 out_le32(priv->regbase + PIO_CMD_STATUS, cfis->command);
783
784 if (ata_wait_register((u32 *)(priv->regbase + PIO_CMD_STATUS),
785 ATA_BUSY, 0x0, 10000)) {
786 debug("Failed to wait for completion\n");
787 return -1;
788 }
789
790 if (len > 0) {
791 tp = (u16 *)buffer;
792 for (i = 0; i < len / 2; i++) {
793 if (iswrite)
794 out_le16(priv->regbase + PIO_DATA, *tp++);
795 else
796 *tp++ = in_le16(priv->regbase + PIO_DATA);
797 }
798 }
799
800 return len;
801}
802
0506620f 803static int mv_sata_identify(struct udevice *dev, int port, u16 *id)
169789dc
TK		 804{
805 struct sata_fis_h2d h2d;
806
807 memset(&h2d, 0, sizeof(struct sata_fis_h2d));
808
809 h2d.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
810 h2d.command = ATA_CMD_ID_ATA;
811
812 /* Give device time to get operational */
813 mdelay(10);
814
0506620f 815 return mv_ata_exec_ata_cmd_nondma(dev, port, &h2d, (u8 *)id,
169789dc
TK		 816 ATA_ID_WORDS * 2, READ_CMD);
817}
818
0506620f 819static void mv_sata_xfer_mode(struct udevice *dev, int port, u16 *id)
169789dc 820{
0506620f 821 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 822
823 priv->pio = id[ATA_ID_PIO_MODES];
824 priv->mwdma = id[ATA_ID_MWDMA_MODES];
825 priv->udma = id[ATA_ID_UDMA_MODES];
826 debug("pio %04x, mwdma %04x, udma %04x\n", priv->pio, priv->mwdma,
827 priv->udma);
828}
829
0506620f 830static void mv_sata_set_features(struct udevice *dev, int port)
169789dc 831{
0506620f 832 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 833 struct sata_fis_h2d cfis;
834 u8 udma_cap;
835
836 memset(&cfis, 0, sizeof(struct sata_fis_h2d));
837
838 cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
839 cfis.command = ATA_CMD_SET_FEATURES;
840 cfis.features = SETFEATURES_XFER;
841
842 /* First check the device capablity */
843 udma_cap = (u8) (priv->udma & 0xff);
844
845 if (udma_cap == ATA_UDMA6)
846 cfis.sector_count = XFER_UDMA_6;
847 if (udma_cap == ATA_UDMA5)
848 cfis.sector_count = XFER_UDMA_5;
849 if (udma_cap == ATA_UDMA4)
850 cfis.sector_count = XFER_UDMA_4;
851 if (udma_cap == ATA_UDMA3)
852 cfis.sector_count = XFER_UDMA_3;
853
0506620f 854 mv_ata_exec_ata_cmd_nondma(dev, port, &cfis, NULL, 0, READ_CMD);
169789dc
TK		 855}
856
857/*
858 * Initialize SATA memory windows
859 */
860static void mvsata_ide_conf_mbus_windows(void)
861{
862 const struct mbus_dram_target_info *dram;
863 int i;
864
865 dram = mvebu_mbus_dram_info();
866
867 /* Disable windows, Set Size/Base to 0 */
868 for (i = 0; i < 4; i++) {
869 writel(0, MVSATA_WIN_CONTROL(i));
870 writel(0, MVSATA_WIN_BASE(i));
871 }
872
873 for (i = 0; i < dram->num_cs; i++) {
874 const struct mbus_dram_window *cs = dram->cs + i;
875 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
876 (dram->mbus_dram_target_id << 4) | 1,
877 MVSATA_WIN_CONTROL(i));
878 writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i));
879 }
880}
881
0506620f 882static int sata_mv_init_sata(struct udevice *dev, int port)
169789dc 883{
0506620f 884 struct mv_priv *priv = dev_get_platdata(dev);
169789dc 885
0506620f 886 debug("Initialize sata dev: %d\n", port);
169789dc 887
0506620f
SR		 888 if (port < 0 || port >= CONFIG_SYS_SATA_MAX_DEVICE) {
889 printf("Invalid sata device %d\n", port);
169789dc
TK		 890 return -1;
891 }
892
169789dc
TK		 893 /* Allocate and align request buffer */
894 priv->crqb_alloc = malloc(sizeof(struct crqb) * REQUEST_QUEUE_SIZE +
895 CRQB_ALIGN);
896 if (!priv->crqb_alloc) {
897 printf("Unable to allocate memory for request queue\n");
898 return -ENOMEM;
899 }
900 memset(priv->crqb_alloc, 0,
901 sizeof(struct crqb) * REQUEST_QUEUE_SIZE + CRQB_ALIGN);
902 priv->request = (struct crqb *)(((u32) priv->crqb_alloc + CRQB_ALIGN) &
903 ~(CRQB_ALIGN - 1));
904
905 /* Allocate and align response buffer */
906 priv->crpb_alloc = malloc(sizeof(struct crpb) * REQUEST_QUEUE_SIZE +
907 CRPB_ALIGN);
908 if (!priv->crpb_alloc) {
909 printf("Unable to allocate memory for response queue\n");
910 return -ENOMEM;
911 }
912 memset(priv->crpb_alloc, 0,
913 sizeof(struct crpb) * REQUEST_QUEUE_SIZE + CRPB_ALIGN);
914 priv->response = (struct crpb *)(((u32) priv->crpb_alloc + CRPB_ALIGN) &
915 ~(CRPB_ALIGN - 1));
916
0506620f 917 sprintf(priv->name, "SATA%d", port);
169789dc 918
0506620f 919 priv->regbase = port == 0 ? SATA0_BASE : SATA1_BASE;
169789dc
TK		 920
921 if (!hw_init) {
922 debug("Initialize sata hw\n");
923 hw_init = 1;
924 mv_reset_one_hc();
925 mvsata_ide_conf_mbus_windows();
926 }
927
0506620f 928 mv_reset_port(dev, port);
169789dc 929
0506620f 930 if (probe_port(dev, port)) {
169789dc
TK		 931 priv->link = 0;
932 return -ENODEV;
933 }
934 priv->link = 1;
935
936 return 0;
937}
938
0506620f 939static int sata_mv_scan_sata(struct udevice *dev, int port)
169789dc 940{
0506620f
SR		 941 struct blk_desc *desc = dev_get_uclass_platdata(dev);
942 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 943 unsigned char serial[ATA_ID_SERNO_LEN + 1];
944 unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
945 unsigned char product[ATA_ID_PROD_LEN + 1];
946 u64 n_sectors;
947 u16 *id;
169789dc
TK		 948
949 if (!priv->link)
950 return -ENODEV;
951
952 id = (u16 *)malloc(ATA_ID_WORDS * 2);
953 if (!id) {
954 printf("Failed to malloc id data\n");
955 return -ENOMEM;
956 }
957
0506620f 958 mv_sata_identify(dev, port, id);
169789dc
TK		 959 ata_swap_buf_le16(id, ATA_ID_WORDS);
960#ifdef DEBUG
961 ata_dump_id(id);
962#endif
963
964 /* Serial number */
965 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
0506620f 966 memcpy(desc->product, serial, sizeof(serial));
169789dc
TK		 967
968 /* Firmware version */
969 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
0506620f 970 memcpy(desc->revision, firmware, sizeof(firmware));
169789dc
TK		 971
972 /* Product model */
973 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
0506620f 974 memcpy(desc->vendor, product, sizeof(product));
169789dc
TK		 975
976 /* Total sectors */
977 n_sectors = ata_id_n_sectors(id);
0506620f 978 desc->lba = n_sectors;
169789dc
TK		 979
980 /* Check if support LBA48 */
981 if (ata_id_has_lba48(id)) {
0506620f 982 desc->lba48 = 1;
169789dc
TK		 983 debug("Device support LBA48\n");
984 }
985
986 /* Get the NCQ queue depth from device */
987 priv->queue_depth = ata_id_queue_depth(id);
988
989 /* Get the xfer mode from device */
0506620f 990 mv_sata_xfer_mode(dev, port, id);
169789dc
TK		 991
992 /* Set the xfer mode to highest speed */
0506620f 993 mv_sata_set_features(dev, port);
169789dc
TK		 994
995 /* Start up */
0506620f 996 mv_start_edma_engine(dev, port);
169789dc
TK		 997
998 return 0;
999}
0506620f
SR		 1000
1001static ulong sata_mv_read(struct udevice *blk, lbaint_t blknr,
1002 lbaint_t blkcnt, void *buffer)
1003{
1004 struct mv_priv *priv = dev_get_platdata(blk);
1005
1006 return ata_low_level_rw(blk, priv->dev_nr, blknr, blkcnt,
1007 buffer, READ_CMD);
1008}
1009
1010static ulong sata_mv_write(struct udevice *blk, lbaint_t blknr,
1011 lbaint_t blkcnt, const void *buffer)
1012{
1013 struct mv_priv *priv = dev_get_platdata(blk);
1014
1015 return ata_low_level_rw(blk, priv->dev_nr, blknr, blkcnt,
1016 (void *)buffer, WRITE_CMD);
1017}
1018
1019static const struct blk_ops sata_mv_blk_ops = {
1020 .read = sata_mv_read,
1021 .write = sata_mv_write,
1022};
1023
1024U_BOOT_DRIVER(sata_mv_driver) = {
1025 .name = "sata_mv_blk",
1026 .id = UCLASS_BLK,
1027 .ops = &sata_mv_blk_ops,
1028 .platdata_auto_alloc_size = sizeof(struct mv_priv),
1029};
1030
1031static int sata_mv_probe(struct udevice *dev)
1032{
1033 const void *blob = gd->fdt_blob;
1034 int node = dev_of_offset(dev);
1035 struct mv_priv *priv;
1036 struct udevice *blk;
1037 int nr_ports;
1038 int ret;
1039 int i;
1040
1041 /* Get number of ports of this SATA controller */
1042 nr_ports = min(fdtdec_get_int(blob, node, "nr-ports", -1),
1043 CONFIG_SYS_SATA_MAX_DEVICE);
1044
1045 for (i = 0; i < nr_ports; i++) {
1046 ret = blk_create_devicef(dev, "sata_mv_blk", "blk",
1047 IF_TYPE_SATA, -1, 512, 0, &blk);
1048 if (ret) {
1049 debug("Can't create device\n");
1050 return ret;
1051 }
1052
1053 priv = dev_get_platdata(blk);
1054 priv->dev_nr = i;
1055
1056 /* Init SATA port */
1057 ret = sata_mv_init_sata(blk, i);
1058 if (ret) {
1059 debug("%s: Failed to init bus\n", __func__);
1060 return ret;
1061 }
1062
1063 /* Scan SATA port */
1064 ret = sata_mv_scan_sata(blk, i);
1065 if (ret) {
1066 debug("%s: Failed to scan bus\n", __func__);
1067 return ret;
1068 }
1069 }
1070
1071 return 0;
1072}
1073
1074static int sata_mv_scan(struct udevice *dev)
1075{
1076 /* Nothing to do here */
1077
1078 return 0;
1079}
1080
1081static const struct udevice_id sata_mv_ids[] = {
1082 { .compatible = "marvell,armada-370-sata" },
586f7b91 1083 { .compatible = "marvell,orion-sata" },
0506620f
SR		 1084 { }
1085};
1086
1087struct ahci_ops sata_mv_ahci_ops = {
1088 .scan = sata_mv_scan,
1089};
1090
1091U_BOOT_DRIVER(sata_mv_ahci) = {
1092 .name = "sata_mv_ahci",
1093 .id = UCLASS_AHCI,
1094 .of_match = sata_mv_ids,
1095 .ops = &sata_mv_ahci_ops,
1096 .probe = sata_mv_probe,
1097};
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