[J-u-boot.git] / arch / arm / dts / tegra30.dtsi

#include <dt-bindings/clock/tegra30-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "skeleton.dtsi"

/ {
	compatible = "nvidia,tegra30";
	interrupt-parent = <&intc>;

	intc: interrupt-controller@50041000 {
		compatible = "arm,cortex-a9-gic";
		reg = <0x50041000 0x1000
		       0x50040100 0x0100>;
		interrupt-controller;
		#interrupt-cells = <3>;
	};

	tegra_car: clock {
		compatible = "nvidia,tegra30-car";
		reg = <0x60006000 0x1000>;
		#clock-cells = <1>;
	};

	apbdma: dma {
		compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
		reg = <0x6000a000 0x1400>;
		interrupts = <0 104 0x04
			      0 105 0x04
			      0 106 0x04
			      0 107 0x04
			      0 108 0x04
			      0 109 0x04
			      0 110 0x04
			      0 111 0x04
			      0 112 0x04
			      0 113 0x04
			      0 114 0x04
			      0 115 0x04
			      0 116 0x04
			      0 117 0x04
			      0 118 0x04
			      0 119 0x04
			      0 128 0x04
			      0 129 0x04
			      0 130 0x04
			      0 131 0x04
			      0 132 0x04
			      0 133 0x04
			      0 134 0x04
			      0 135 0x04
			      0 136 0x04
			      0 137 0x04
			      0 138 0x04
			      0 139 0x04
			      0 140 0x04
			      0 141 0x04
			      0 142 0x04
			      0 143 0x04>;
		clocks = <&tegra_car 34>;
	};

	gpio: gpio@6000d000 {
		compatible = "nvidia,tegra30-gpio";
		reg = <0x6000d000 0x1000>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	i2c@7000c000 {
		compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c000 0x100>;
		interrupts = <0 38 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 12>, <&tegra_car 182>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000c400 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c400 0x100>;
		interrupts = <0 84 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 54>, <&tegra_car 182>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000c500 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c500 0x100>;
		interrupts = <0 92 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 67>, <&tegra_car 182>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000c700 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c700 0x100>;
		interrupts = <0 120 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 103>, <&tegra_car 182>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000d000 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000d000 0x100>;
		interrupts = <0 53 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 47>, <&tegra_car 182>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	uarta: serial@70006000 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006000 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_UARTA>;
		resets = <&tegra_car 6>;
		reset-names = "serial";
		dmas = <&apbdma 8>, <&apbdma 8>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	uartb: serial@70006040 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006040 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_UARTB>;
		resets = <&tegra_car 7>;
		reset-names = "serial";
		dmas = <&apbdma 9>, <&apbdma 9>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	uartc: serial@70006200 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006200 0x100>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_UARTC>;
		resets = <&tegra_car 55>;
		reset-names = "serial";
		dmas = <&apbdma 10>, <&apbdma 10>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	uartd: serial@70006300 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006300 0x100>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_UARTD>;
		resets = <&tegra_car 65>;
		reset-names = "serial";
		dmas = <&apbdma 19>, <&apbdma 19>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	uarte: serial@70006400 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006400 0x100>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_UARTE>;
		resets = <&tegra_car 66>;
		reset-names = "serial";
		dmas = <&apbdma 20>, <&apbdma 20>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	spi@7000d400 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000d400 0x200>;
		interrupts = <0 59 0x04>;
		nvidia,dma-request-selector = <&apbdma 15>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 41>;
		status = "disabled";
	};

	spi@7000d600 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000d600 0x200>;
		interrupts = <0 82 0x04>;
		nvidia,dma-request-selector = <&apbdma 16>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 44>;
		status = "disabled";
	};

	spi@7000d800 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000d480 0x200>;
		interrupts = <0 83 0x04>;
		nvidia,dma-request-selector = <&apbdma 17>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 46>;
		status = "disabled";
	};

	spi@7000da00 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000da00 0x200>;
		interrupts = <0 93 0x04>;
		nvidia,dma-request-selector = <&apbdma 18>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 68>;
		status = "disabled";
	};

	spi@7000dc00 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000dc00 0x200>;
		interrupts = <0 94 0x04>;
		nvidia,dma-request-selector = <&apbdma 27>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 104>;
		status = "disabled";
	};

	spi@7000de00 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000de00 0x200>;
		interrupts = <0 79 0x04>;
		nvidia,dma-request-selector = <&apbdma 28>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 105>;
		status = "disabled";
	};

	sdhci@78000000 {
		compatible = "nvidia,tegra30-sdhci";
		reg = <0x78000000 0x200>;
		interrupts = <0 14 0x04>;
		clocks = <&tegra_car 14>;
		status = "disabled";
	};

	sdhci@78000200 {
		compatible = "nvidia,tegra30-sdhci";
		reg = <0x78000200 0x200>;
		interrupts = <0 15 0x04>;
		clocks = <&tegra_car 9>;
		status = "disabled";
	};

	sdhci@78000400 {
		compatible = "nvidia,tegra30-sdhci";
		reg = <0x78000400 0x200>;
		interrupts = <0 19 0x04>;
		clocks = <&tegra_car 69>;
		status = "disabled";
	};

	sdhci@78000600 {
		compatible = "nvidia,tegra30-sdhci";
		reg = <0x78000600 0x200>;
		interrupts = <0 31 0x04>;
		clocks = <&tegra_car 15>;
		status = "disabled";
	};

	usb@7d000000 {
		compatible = "nvidia,tegra30-ehci";
		reg = <0x7d000000 0x4000>;
		interrupts = <52>;
		phy_type = "utmi";
		clocks = <&tegra_car 22>;	/* PERIPH_ID_USBD */
		status = "disabled";
	};

	usb@7d004000 {
		compatible = "nvidia,tegra30-ehci";
		reg = <0x7d004000 0x4000>;
		interrupts = <53>;
		phy_type = "hsic";
		clocks = <&tegra_car 58>;	/* PERIPH_ID_USB2 */
		status = "disabled";
	};

	usb@7d008000 {
		compatible = "nvidia,tegra30-ehci";
		reg = <0x7d008000 0x4000>;
		interrupts = <129>;
		phy_type = "utmi";
		clocks = <&tegra_car 59>;	/* PERIPH_ID_USB3 */
		status = "disabled";
	};
};
Commit	Line	Data
c3691392	1	#include <dt-bindings/clock/tegra30-car.h>
8946034a SG	2	#include <dt-bindings/gpio/tegra-gpio.h>
	3	#include <dt-bindings/interrupt-controller/arm-gic.h>
	4
6c5be646	5	#include "skeleton.dtsi"
79ce91ba TW	6
	7	/ {
	8	compatible = "nvidia,tegra30";
cd998761 TR	9	interrupt-parent = <&intc>;
	10
	11	intc: interrupt-controller@50041000 {
	12	compatible = "arm,cortex-a9-gic";
	13	reg = <0x50041000 0x1000
	14	0x50040100 0x0100>;
	15	interrupt-controller;
	16	#interrupt-cells = <3>;
	17	};
083bbbbe	18
527519ae TW	19	tegra_car: clock {
527519ae TW	20	compatible = "nvidia,tegra30-car";
083bbbbe TW	21	reg = <0x60006000 0x1000>;
	22	#clock-cells = <1>;
	23	};
	24
64e6ec1d AM	25	apbdma: dma {
	26	compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
	27	reg = <0x6000a000 0x1400>;
	28	interrupts = <0 104 0x04
	29	0 105 0x04
	30	0 106 0x04
	31	0 107 0x04
	32	0 108 0x04
	33	0 109 0x04
	34	0 110 0x04
	35	0 111 0x04
	36	0 112 0x04
	37	0 113 0x04
	38	0 114 0x04
	39	0 115 0x04
	40	0 116 0x04
	41	0 117 0x04
	42	0 118 0x04
	43	0 119 0x04
	44	0 128 0x04
	45	0 129 0x04
	46	0 130 0x04
	47	0 131 0x04
	48	0 132 0x04
	49	0 133 0x04
	50	0 134 0x04
	51	0 135 0x04
	52	0 136 0x04
	53	0 137 0x04
	54	0 138 0x04
	55	0 139 0x04
	56	0 140 0x04
	57	0 141 0x04
	58	0 142 0x04
	59	0 143 0x04>;
527519ae TW	60	clocks = <&tegra_car 34>;
	61	};
	62
8946034a	63	gpio: gpio@6000d000 {
527519ae TW	64	compatible = "nvidia,tegra30-gpio";
527519ae TW	65	reg = <0x6000d000 0x1000>;
8946034a SG	66	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
	67	<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
	68	<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
	69	<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
	70	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	71	<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
	72	<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
	73	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
527519ae TW	74	#gpio-cells = <2>;
	75	gpio-controller;
	76	#interrupt-cells = <2>;
	77	interrupt-controller;
64e6ec1d AM	78	};
64e6ec1d AM	79
083bbbbe	80	i2c@7000c000 {
527519ae TW	81	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
	82	reg = <0x7000c000 0x100>;
	83	interrupts = <0 38 0x04>;
083bbbbe TW	84	#address-cells = <1>;
083bbbbe TW	85	#size-cells = <0>;
527519ae TW	86	clocks = <&tegra_car 12>, <&tegra_car 182>;
	87	clock-names = "div-clk", "fast-clk";
	88	status = "disabled";
083bbbbe TW	89	};
	90
	91	i2c@7000c400 {
527519ae TW	92	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
	93	reg = <0x7000c400 0x100>;
	94	interrupts = <0 84 0x04>;
083bbbbe TW	95	#address-cells = <1>;
083bbbbe TW	96	#size-cells = <0>;
527519ae TW	97	clocks = <&tegra_car 54>, <&tegra_car 182>;
	98	clock-names = "div-clk", "fast-clk";
	99	status = "disabled";
083bbbbe TW	100	};
	101
	102	i2c@7000c500 {
527519ae TW	103	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
	104	reg = <0x7000c500 0x100>;
	105	interrupts = <0 92 0x04>;
083bbbbe TW	106	#address-cells = <1>;
083bbbbe TW	107	#size-cells = <0>;
527519ae TW	108	clocks = <&tegra_car 67>, <&tegra_car 182>;
	109	clock-names = "div-clk", "fast-clk";
	110	status = "disabled";
083bbbbe TW	111	};
	112
	113	i2c@7000c700 {
527519ae TW	114	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
	115	reg = <0x7000c700 0x100>;
	116	interrupts = <0 120 0x04>;
083bbbbe TW	117	#address-cells = <1>;
083bbbbe TW	118	#size-cells = <0>;
527519ae TW	119	clocks = <&tegra_car 103>, <&tegra_car 182>;
	120	clock-names = "div-clk", "fast-clk";
	121	status = "disabled";
083bbbbe TW	122	};
	123
	124	i2c@7000d000 {
527519ae TW	125	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
	126	reg = <0x7000d000 0x100>;
	127	interrupts = <0 53 0x04>;
083bbbbe TW	128	#address-cells = <1>;
083bbbbe TW	129	#size-cells = <0>;
527519ae TW	130	clocks = <&tegra_car 47>, <&tegra_car 182>;
	131	clock-names = "div-clk", "fast-clk";
	132	status = "disabled";
083bbbbe	133	};
23e3158f	134
c3691392 SG	135	uarta: serial@70006000 {
	136	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	137	reg = <0x70006000 0x40>;
	138	reg-shift = <2>;
	139	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	140	clocks = <&tegra_car TEGRA30_CLK_UARTA>;
	141	resets = <&tegra_car 6>;
	142	reset-names = "serial";
	143	dmas = <&apbdma 8>, <&apbdma 8>;
	144	dma-names = "rx", "tx";
	145	status = "disabled";
	146	};
	147
	148	uartb: serial@70006040 {
	149	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	150	reg = <0x70006040 0x40>;
	151	reg-shift = <2>;
	152	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	153	clocks = <&tegra_car TEGRA30_CLK_UARTB>;
	154	resets = <&tegra_car 7>;
	155	reset-names = "serial";
	156	dmas = <&apbdma 9>, <&apbdma 9>;
	157	dma-names = "rx", "tx";
	158	status = "disabled";
	159	};
	160
	161	uartc: serial@70006200 {
	162	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	163	reg = <0x70006200 0x100>;
	164	reg-shift = <2>;
	165	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	166	clocks = <&tegra_car TEGRA30_CLK_UARTC>;
	167	resets = <&tegra_car 55>;
	168	reset-names = "serial";
	169	dmas = <&apbdma 10>, <&apbdma 10>;
	170	dma-names = "rx", "tx";
	171	status = "disabled";
	172	};
	173
	174	uartd: serial@70006300 {
	175	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	176	reg = <0x70006300 0x100>;
	177	reg-shift = <2>;
	178	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
	179	clocks = <&tegra_car TEGRA30_CLK_UARTD>;
	180	resets = <&tegra_car 65>;
	181	reset-names = "serial";
	182	dmas = <&apbdma 19>, <&apbdma 19>;
	183	dma-names = "rx", "tx";
	184	status = "disabled";
	185	};
	186
	187	uarte: serial@70006400 {
	188	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	189	reg = <0x70006400 0x100>;
	190	reg-shift = <2>;
	191	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	192	clocks = <&tegra_car TEGRA30_CLK_UARTE>;
	193	resets = <&tegra_car 66>;
	194	reset-names = "serial";
	195	dmas = <&apbdma 20>, <&apbdma 20>;
	196	dma-names = "rx", "tx";
	197	status = "disabled";
	198	};
199
23e3158f AM	200	spi@7000d400 {
	201	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	202	reg = <0x7000d400 0x200>;
	203	interrupts = <0 59 0x04>;
	204	nvidia,dma-request-selector = <&apbdma 15>;
	205	#address-cells = <1>;
	206	#size-cells = <0>;
23e3158f	207	clocks = <&tegra_car 41>;
527519ae	208	status = "disabled";
23e3158f AM	209	};
	210
	211	spi@7000d600 {
	212	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	213	reg = <0x7000d600 0x200>;
	214	interrupts = <0 82 0x04>;
	215	nvidia,dma-request-selector = <&apbdma 16>;
	216	#address-cells = <1>;
	217	#size-cells = <0>;
23e3158f	218	clocks = <&tegra_car 44>;
527519ae	219	status = "disabled";
23e3158f AM	220	};
	221
	222	spi@7000d800 {
	223	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	224	reg = <0x7000d480 0x200>;
	225	interrupts = <0 83 0x04>;
	226	nvidia,dma-request-selector = <&apbdma 17>;
	227	#address-cells = <1>;
	228	#size-cells = <0>;
23e3158f	229	clocks = <&tegra_car 46>;
527519ae	230	status = "disabled";
23e3158f AM	231	};
	232
	233	spi@7000da00 {
	234	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	235	reg = <0x7000da00 0x200>;
	236	interrupts = <0 93 0x04>;
	237	nvidia,dma-request-selector = <&apbdma 18>;
	238	#address-cells = <1>;
	239	#size-cells = <0>;
23e3158f	240	clocks = <&tegra_car 68>;
527519ae	241	status = "disabled";
23e3158f AM	242	};
	243
	244	spi@7000dc00 {
	245	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	246	reg = <0x7000dc00 0x200>;
	247	interrupts = <0 94 0x04>;
	248	nvidia,dma-request-selector = <&apbdma 27>;
	249	#address-cells = <1>;
	250	#size-cells = <0>;
23e3158f	251	clocks = <&tegra_car 104>;
527519ae	252	status = "disabled";
23e3158f AM	253	};
	254
	255	spi@7000de00 {
	256	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	257	reg = <0x7000de00 0x200>;
	258	interrupts = <0 79 0x04>;
	259	nvidia,dma-request-selector = <&apbdma 28>;
	260	#address-cells = <1>;
	261	#size-cells = <0>;
23e3158f	262	clocks = <&tegra_car 105>;
527519ae	263	status = "disabled";
23e3158f	264	};
1baa4e72 TW	265
	266	sdhci@78000000 {
	267	compatible = "nvidia,tegra30-sdhci";
	268	reg = <0x78000000 0x200>;
	269	interrupts = <0 14 0x04>;
	270	clocks = <&tegra_car 14>;
	271	status = "disabled";
	272	};
	273
	274	sdhci@78000200 {
	275	compatible = "nvidia,tegra30-sdhci";
	276	reg = <0x78000200 0x200>;
	277	interrupts = <0 15 0x04>;
	278	clocks = <&tegra_car 9>;
	279	status = "disabled";
	280	};
	281
	282	sdhci@78000400 {
	283	compatible = "nvidia,tegra30-sdhci";
	284	reg = <0x78000400 0x200>;
	285	interrupts = <0 19 0x04>;
	286	clocks = <&tegra_car 69>;
	287	status = "disabled";
	288	};
	289
	290	sdhci@78000600 {
	291	compatible = "nvidia,tegra30-sdhci";
	292	reg = <0x78000600 0x200>;
	293	interrupts = <0 31 0x04>;
	294	clocks = <&tegra_car 15>;
	295	status = "disabled";
	296	};
56867d88 JL	297
	298	usb@7d000000 {
	299	compatible = "nvidia,tegra30-ehci";
	300	reg = <0x7d000000 0x4000>;
	301	interrupts = <52>;
	302	phy_type = "utmi";
	303	clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
	304	status = "disabled";
	305	};
	306
	307	usb@7d004000 {
	308	compatible = "nvidia,tegra30-ehci";
	309	reg = <0x7d004000 0x4000>;
	310	interrupts = <53>;
	311	phy_type = "hsic";
	312	clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
	313	status = "disabled";
	314	};
	315
	316	usb@7d008000 {
	317	compatible = "nvidia,tegra30-ehci";
	318	reg = <0x7d008000 0x4000>;
	319	interrupts = <129>;
	320	phy_type = "utmi";
	321	clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
	322	status = "disabled";
	323	};
79ce91ba	324	};