[J-u-boot.git] / drivers / spi / sh_qspi.c

// SPDX-License-Identifier: GPL-2.0
/*
 * SH QSPI (Quad SPI) driver
 *
 * Copyright (C) 2013 Renesas Electronics Corporation
 * Copyright (C) 2013 Nobuhiro Iwamatsu <[email protected]>
 */

#include <common.h>
#include <console.h>
#include <malloc.h>
#include <spi.h>
#include <wait_bit.h>
#include <asm/arch/rmobile.h>
#include <asm/io.h>
#include <linux/bitops.h>

/* SH QSPI register bit masks <REG>_<BIT> */
#define SPCR_MSTR	0x08
#define SPCR_SPE	0x40
#define SPSR_SPRFF	0x80
#define SPSR_SPTEF	0x20
#define SPPCR_IO3FV	0x04
#define SPPCR_IO2FV	0x02
#define SPPCR_IO1FV	0x01
#define SPBDCR_RXBC0	BIT(0)
#define SPCMD_SCKDEN	BIT(15)
#define SPCMD_SLNDEN	BIT(14)
#define SPCMD_SPNDEN	BIT(13)
#define SPCMD_SSLKP	BIT(7)
#define SPCMD_BRDV0	BIT(2)
#define SPCMD_INIT1	SPCMD_SCKDEN | SPCMD_SLNDEN | \
			SPCMD_SPNDEN | SPCMD_SSLKP | \
			SPCMD_BRDV0
#define SPCMD_INIT2	SPCMD_SPNDEN | SPCMD_SSLKP | \
			SPCMD_BRDV0
#define SPBFCR_TXRST	BIT(7)
#define SPBFCR_RXRST	BIT(6)
#define SPBFCR_TXTRG	0x30
#define SPBFCR_RXTRG	0x07

/* SH QSPI register set */
struct sh_qspi_regs {
	u8	spcr;
	u8	sslp;
	u8	sppcr;
	u8	spsr;
	u32	spdr;
	u8	spscr;
	u8	spssr;
	u8	spbr;
	u8	spdcr;
	u8	spckd;
	u8	sslnd;
	u8	spnd;
	u8	dummy0;
	u16	spcmd0;
	u16	spcmd1;
	u16	spcmd2;
	u16	spcmd3;
	u8	spbfcr;
	u8	dummy1;
	u16	spbdcr;
	u32	spbmul0;
	u32	spbmul1;
	u32	spbmul2;
	u32	spbmul3;
};

struct sh_qspi_slave {
#ifndef CONFIG_DM_SPI
	struct spi_slave	slave;
#endif
	struct sh_qspi_regs	*regs;
};

static void sh_qspi_init(struct sh_qspi_slave *ss)
{
	/* QSPI initialize */
	/* Set master mode only */
	writeb(SPCR_MSTR, &ss->regs->spcr);

	/* Set SSL signal level */
	writeb(0x00, &ss->regs->sslp);

	/* Set MOSI signal value when transfer is in idle state */
	writeb(SPPCR_IO3FV|SPPCR_IO2FV, &ss->regs->sppcr);

	/* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
	writeb(0x01, &ss->regs->spbr);

	/* Disable Dummy Data Transmission */
	writeb(0x00, &ss->regs->spdcr);

	/* Set clock delay value */
	writeb(0x00, &ss->regs->spckd);

	/* Set SSL negation delay value */
	writeb(0x00, &ss->regs->sslnd);

	/* Set next-access delay value */
	writeb(0x00, &ss->regs->spnd);

	/* Set equence command */
	writew(SPCMD_INIT2, &ss->regs->spcmd0);

	/* Reset transfer and receive Buffer */
	setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);

	/* Clear transfer and receive Buffer control bit */
	clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);

	/* Set equence control method. Use equence0 only */
	writeb(0x00, &ss->regs->spscr);

	/* Enable SPI function */
	setbits_8(&ss->regs->spcr, SPCR_SPE);
}

static void sh_qspi_cs_activate(struct sh_qspi_slave *ss)
{
	/* Set master mode only */
	writeb(SPCR_MSTR, &ss->regs->spcr);

	/* Set command */
	writew(SPCMD_INIT1, &ss->regs->spcmd0);

	/* Reset transfer and receive Buffer */
	setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);

	/* Clear transfer and receive Buffer control bit */
	clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);

	/* Set equence control method. Use equence0 only */
	writeb(0x00, &ss->regs->spscr);

	/* Enable SPI function */
	setbits_8(&ss->regs->spcr, SPCR_SPE);
}

static void sh_qspi_cs_deactivate(struct sh_qspi_slave *ss)
{
	/* Disable SPI Function */
	clrbits_8(&ss->regs->spcr, SPCR_SPE);
}

static int sh_qspi_xfer_common(struct sh_qspi_slave *ss, unsigned int bitlen,
			       const void *dout, void *din, unsigned long flags)
{
	u32 nbyte, chunk;
	int i, ret = 0;
	u8 dtdata = 0, drdata;
	u8 *tdata = &dtdata, *rdata = &drdata;
	u32 *spbmul0 = &ss->regs->spbmul0;

	if (dout == NULL && din == NULL) {
		if (flags & SPI_XFER_END)
			sh_qspi_cs_deactivate(ss);
		return 0;
	}

	if (bitlen % 8) {
		printf("%s: bitlen is not 8bit alined %d", __func__, bitlen);
		return 1;
	}

	nbyte = bitlen / 8;

	if (flags & SPI_XFER_BEGIN) {
		sh_qspi_cs_activate(ss);

		/* Set 1048576 byte */
		writel(0x100000, spbmul0);
	}

	if (flags & SPI_XFER_END)
		writel(nbyte, spbmul0);

	if (dout != NULL)
		tdata = (u8 *)dout;

	if (din != NULL)
		rdata = din;

	while (nbyte > 0) {
		/*
		 * Check if there is 32 Byte chunk and if there is, transfer
		 * it in one burst, otherwise transfer on byte-by-byte basis.
		 */
		chunk = (nbyte >= 32) ? 32 : 1;

		clrsetbits_8(&ss->regs->spbfcr, SPBFCR_TXTRG | SPBFCR_RXTRG,
			     chunk == 32 ? SPBFCR_TXTRG | SPBFCR_RXTRG : 0);

		ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPTEF,
				     true, 1000, true);
		if (ret)
			return ret;

		for (i = 0; i < chunk; i++) {
			writeb(*tdata, &ss->regs->spdr);
			if (dout != NULL)
				tdata++;
		}

		ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPRFF,
				     true, 1000, true);
		if (ret)
			return ret;

		for (i = 0; i < chunk; i++) {
			*rdata = readb(&ss->regs->spdr);
			if (din != NULL)
				rdata++;
		}

		nbyte -= chunk;
	}

	if (flags & SPI_XFER_END)
		sh_qspi_cs_deactivate(ss);

	return ret;
}

#ifndef CONFIG_DM_SPI
static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave)
{
	return container_of(slave, struct sh_qspi_slave, slave);
}

int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
	return 1;
}

void spi_cs_activate(struct spi_slave *slave)
{
	struct sh_qspi_slave *ss = to_sh_qspi(slave);

	sh_qspi_cs_activate(ss);
}

void spi_cs_deactivate(struct spi_slave *slave)
{
	struct sh_qspi_slave *ss = to_sh_qspi(slave);

	sh_qspi_cs_deactivate(ss);
}

struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
		unsigned int max_hz, unsigned int mode)
{
	struct sh_qspi_slave *ss;

	if (!spi_cs_is_valid(bus, cs))
		return NULL;

	ss = spi_alloc_slave(struct sh_qspi_slave, bus, cs);
	if (!ss) {
		printf("SPI_error: Fail to allocate sh_qspi_slave\n");
		return NULL;
	}

	ss->regs = (struct sh_qspi_regs *)SH_QSPI_BASE;

	/* Init SH QSPI */
	sh_qspi_init(ss);

	return &ss->slave;
}

void spi_free_slave(struct spi_slave *slave)
{
	struct sh_qspi_slave *spi = to_sh_qspi(slave);

	free(spi);
}

int spi_claim_bus(struct spi_slave *slave)
{
	return 0;
}

void spi_release_bus(struct spi_slave *slave)
{
}

int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
	     const void *dout, void *din, unsigned long flags)
{
	struct sh_qspi_slave *ss = to_sh_qspi(slave);

	return sh_qspi_xfer_common(ss, bitlen, dout, din, flags);
}

#else

#include <dm.h>

static int sh_qspi_xfer(struct udevice *dev, unsigned int bitlen,
			const void *dout, void *din, unsigned long flags)
{
	struct udevice *bus = dev->parent;
	struct sh_qspi_slave *ss = dev_get_platdata(bus);

	return sh_qspi_xfer_common(ss, bitlen, dout, din, flags);
}

static int sh_qspi_set_speed(struct udevice *dev, uint speed)
{
	/* This is a SPI NOR controller, do nothing. */
	return 0;
}

static int sh_qspi_set_mode(struct udevice *dev, uint mode)
{
	/* This is a SPI NOR controller, do nothing. */
	return 0;
}

static int sh_qspi_probe(struct udevice *dev)
{
	struct sh_qspi_slave *ss = dev_get_platdata(dev);

	sh_qspi_init(ss);

	return 0;
}

static int sh_qspi_ofdata_to_platdata(struct udevice *dev)
{
	struct sh_qspi_slave *plat = dev_get_platdata(dev);

	plat->regs = (struct sh_qspi_regs *)dev_read_addr(dev);

	return 0;
}

static const struct dm_spi_ops sh_qspi_ops = {
	.xfer		= sh_qspi_xfer,
	.set_speed	= sh_qspi_set_speed,
	.set_mode	= sh_qspi_set_mode,
};

static const struct udevice_id sh_qspi_ids[] = {
	{ .compatible = "renesas,qspi" },
	{ }
};

U_BOOT_DRIVER(sh_qspi) = {
	.name		= "sh_qspi",
	.id		= UCLASS_SPI,
	.of_match	= sh_qspi_ids,
	.ops		= &sh_qspi_ops,
	.ofdata_to_platdata = sh_qspi_ofdata_to_platdata,
	.platdata_auto_alloc_size = sizeof(struct sh_qspi_slave),
	.probe		= sh_qspi_probe,
};
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0
16f47c9c NI	2	/*
	3	* SH QSPI (Quad SPI) driver
	4	*
	5	* Copyright (C) 2013 Renesas Electronics Corporation
	6	* Copyright (C) 2013 Nobuhiro Iwamatsu <[email protected]>
16f47c9c NI	7	*/
	8
	9	#include <common.h>
24b852a7	10	#include <console.h>
16f47c9c NI	11	#include <malloc.h>
16f47c9c NI	12	#include <spi.h>
9573db65	13	#include <wait_bit.h>
22e75d6d	14	#include <asm/arch/rmobile.h>
16f47c9c	15	#include <asm/io.h>
cd93d625	16	#include <linux/bitops.h>
16f47c9c NI	17
	18	/* SH QSPI register bit masks <REG>_<BIT> */
	19	#define SPCR_MSTR 0x08
	20	#define SPCR_SPE 0x40
	21	#define SPSR_SPRFF 0x80
	22	#define SPSR_SPTEF 0x20
	23	#define SPPCR_IO3FV 0x04
	24	#define SPPCR_IO2FV 0x02
	25	#define SPPCR_IO1FV 0x01
ccaa9485 JT	26	#define SPBDCR_RXBC0 BIT(0)
	27	#define SPCMD_SCKDEN BIT(15)
	28	#define SPCMD_SLNDEN BIT(14)
	29	#define SPCMD_SPNDEN BIT(13)
	30	#define SPCMD_SSLKP BIT(7)
	31	#define SPCMD_BRDV0 BIT(2)
16f47c9c NI	32	#define SPCMD_INIT1 SPCMD_SCKDEN \| SPCMD_SLNDEN \| \
	33	SPCMD_SPNDEN \| SPCMD_SSLKP \| \
	34	SPCMD_BRDV0
	35	#define SPCMD_INIT2 SPCMD_SPNDEN \| SPCMD_SSLKP \| \
	36	SPCMD_BRDV0
ccaa9485 JT	37	#define SPBFCR_TXRST BIT(7)
ccaa9485 JT	38	#define SPBFCR_RXRST BIT(6)
ea5512eb MV	39	#define SPBFCR_TXTRG 0x30
ea5512eb MV	40	#define SPBFCR_RXTRG 0x07
16f47c9c NI	41
	42	/* SH QSPI register set */
	43	struct sh_qspi_regs {
0e6fa20b MV	44	u8 spcr;
	45	u8 sslp;
	46	u8 sppcr;
	47	u8 spsr;
	48	u32 spdr;
	49	u8 spscr;
	50	u8 spssr;
	51	u8 spbr;
	52	u8 spdcr;
	53	u8 spckd;
	54	u8 sslnd;
	55	u8 spnd;
	56	u8 dummy0;
	57	u16 spcmd0;
	58	u16 spcmd1;
	59	u16 spcmd2;
	60	u16 spcmd3;
	61	u8 spbfcr;
	62	u8 dummy1;
	63	u16 spbdcr;
	64	u32 spbmul0;
	65	u32 spbmul1;
	66	u32 spbmul2;
	67	u32 spbmul3;
16f47c9c NI	68	};
	69
	70	struct sh_qspi_slave {
b3bec252	71	#ifndef CONFIG_DM_SPI
16f47c9c	72	struct spi_slave slave;
b3bec252	73	#endif
16f47c9c NI	74	struct sh_qspi_regs *regs;
	75	};
	76
16f47c9c NI	77	static void sh_qspi_init(struct sh_qspi_slave *ss)
	78	{
	79	/* QSPI initialize */
	80	/* Set master mode only */
	81	writeb(SPCR_MSTR, &ss->regs->spcr);
	82
	83	/* Set SSL signal level */
	84	writeb(0x00, &ss->regs->sslp);
	85
	86	/* Set MOSI signal value when transfer is in idle state */
	87	writeb(SPPCR_IO3FV\|SPPCR_IO2FV, &ss->regs->sppcr);
	88
	89	/* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
	90	writeb(0x01, &ss->regs->spbr);
	91
	92	/* Disable Dummy Data Transmission */
	93	writeb(0x00, &ss->regs->spdcr);
	94
	95	/* Set clock delay value */
	96	writeb(0x00, &ss->regs->spckd);
	97
	98	/* Set SSL negation delay value */
	99	writeb(0x00, &ss->regs->sslnd);
	100
	101	/* Set next-access delay value */
	102	writeb(0x00, &ss->regs->spnd);
	103
	104	/* Set equence command */
	105	writew(SPCMD_INIT2, &ss->regs->spcmd0);
	106
	107	/* Reset transfer and receive Buffer */
	108	setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST\|SPBFCR_RXRST);
	109
	110	/* Clear transfer and receive Buffer control bit */
	111	clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST\|SPBFCR_RXRST);
	112
	113	/* Set equence control method. Use equence0 only */
	114	writeb(0x00, &ss->regs->spscr);
	115
	116	/* Enable SPI function */
	117	setbits_8(&ss->regs->spcr, SPCR_SPE);
	118	}
	119
b3bec252	120	static void sh_qspi_cs_activate(struct sh_qspi_slave *ss)
16f47c9c	121	{
16f47c9c NI	122	/* Set master mode only */
	123	writeb(SPCR_MSTR, &ss->regs->spcr);
	124
	125	/* Set command */
	126	writew(SPCMD_INIT1, &ss->regs->spcmd0);
	127
	128	/* Reset transfer and receive Buffer */
	129	setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST\|SPBFCR_RXRST);
	130
	131	/* Clear transfer and receive Buffer control bit */
	132	clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST\|SPBFCR_RXRST);
	133
	134	/* Set equence control method. Use equence0 only */
	135	writeb(0x00, &ss->regs->spscr);
	136
	137	/* Enable SPI function */
	138	setbits_8(&ss->regs->spcr, SPCR_SPE);
	139	}
	140
b3bec252	141	static void sh_qspi_cs_deactivate(struct sh_qspi_slave *ss)
16f47c9c	142	{
16f47c9c NI	143	/* Disable SPI Function */
	144	clrbits_8(&ss->regs->spcr, SPCR_SPE);
	145	}
	146
b3bec252 MV	147	static int sh_qspi_xfer_common(struct sh_qspi_slave *ss, unsigned int bitlen,
b3bec252 MV	148	const void dout, void din, unsigned long flags)
16f47c9c	149	{
ea5512eb MV	150	u32 nbyte, chunk;
ea5512eb MV	151	int i, ret = 0;
0e6fa20b MV	152	u8 dtdata = 0, drdata;
	153	u8 tdata = &dtdata, rdata = &drdata;
	154	u32 *spbmul0 = &ss->regs->spbmul0;
16f47c9c NI	155
	156	if (dout == NULL && din == NULL) {
	157	if (flags & SPI_XFER_END)
b3bec252	158	sh_qspi_cs_deactivate(ss);
16f47c9c NI	159	return 0;
	160	}
	161
	162	if (bitlen % 8) {
	163	printf("%s: bitlen is not 8bit alined %d", __func__, bitlen);
	164	return 1;
	165	}
	166
	167	nbyte = bitlen / 8;
	168
	169	if (flags & SPI_XFER_BEGIN) {
b3bec252	170	sh_qspi_cs_activate(ss);
16f47c9c NI	171
	172	/* Set 1048576 byte */
	173	writel(0x100000, spbmul0);
	174	}
	175
	176	if (flags & SPI_XFER_END)
	177	writel(nbyte, spbmul0);
	178
	179	if (dout != NULL)
0e6fa20b	180	tdata = (u8 *)dout;
16f47c9c NI	181
	182	if (din != NULL)
	183	rdata = din;
	184
	185	while (nbyte > 0) {
ea5512eb MV	186	/*
	187	* Check if there is 32 Byte chunk and if there is, transfer
	188	* it in one burst, otherwise transfer on byte-by-byte basis.
	189	*/
	190	chunk = (nbyte >= 32) ? 32 : 1;
	191
	192	clrsetbits_8(&ss->regs->spbfcr, SPBFCR_TXTRG \| SPBFCR_RXTRG,
	193	chunk == 32 ? SPBFCR_TXTRG \| SPBFCR_RXTRG : 0);
	194
9573db65 MV	195	ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPTEF,
	196	true, 1000, true);
	197	if (ret)
	198	return ret;
16f47c9c	199
ea5512eb MV	200	for (i = 0; i < chunk; i++) {
	201	writeb(*tdata, &ss->regs->spdr);
	202	if (dout != NULL)
	203	tdata++;
	204	}
16f47c9c	205
9573db65 MV	206	ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPRFF,
	207	true, 1000, true);
	208	if (ret)
	209	return ret;
16f47c9c	210
ea5512eb MV	211	for (i = 0; i < chunk; i++) {
	212	*rdata = readb(&ss->regs->spdr);
	213	if (din != NULL)
	214	rdata++;
	215	}
16f47c9c	216
ea5512eb	217	nbyte -= chunk;
16f47c9c NI	218	}
	219
	220	if (flags & SPI_XFER_END)
b3bec252	221	sh_qspi_cs_deactivate(ss);
16f47c9c NI	222
	223	return ret;
	224	}
b3bec252 MV	225
	226	#ifndef CONFIG_DM_SPI
	227	static inline struct sh_qspi_slave to_sh_qspi(struct spi_slave slave)
	228	{
	229	return container_of(slave, struct sh_qspi_slave, slave);
	230	}
	231
	232	int spi_cs_is_valid(unsigned int bus, unsigned int cs)
	233	{
	234	return 1;
	235	}
	236
	237	void spi_cs_activate(struct spi_slave *slave)
	238	{
	239	struct sh_qspi_slave *ss = to_sh_qspi(slave);
	240
	241	sh_qspi_cs_activate(ss);
	242	}
	243
	244	void spi_cs_deactivate(struct spi_slave *slave)
	245	{
	246	struct sh_qspi_slave *ss = to_sh_qspi(slave);
	247
	248	sh_qspi_cs_deactivate(ss);
	249	}
	250
b3bec252 MV	251	struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
	252	unsigned int max_hz, unsigned int mode)
	253	{
	254	struct sh_qspi_slave *ss;
	255
	256	if (!spi_cs_is_valid(bus, cs))
	257	return NULL;
	258
	259	ss = spi_alloc_slave(struct sh_qspi_slave, bus, cs);
	260	if (!ss) {
	261	printf("SPI_error: Fail to allocate sh_qspi_slave\n");
	262	return NULL;
	263	}
	264
	265	ss->regs = (struct sh_qspi_regs *)SH_QSPI_BASE;
	266
	267	/* Init SH QSPI */
	268	sh_qspi_init(ss);
	269
	270	return &ss->slave;
	271	}
	272
	273	void spi_free_slave(struct spi_slave *slave)
	274	{
	275	struct sh_qspi_slave *spi = to_sh_qspi(slave);
	276
	277	free(spi);
	278	}
	279
	280	int spi_claim_bus(struct spi_slave *slave)
	281	{
	282	return 0;
	283	}
	284
	285	void spi_release_bus(struct spi_slave *slave)
	286	{
	287	}
	288
	289	int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
	290	const void dout, void din, unsigned long flags)
	291	{
	292	struct sh_qspi_slave *ss = to_sh_qspi(slave);
	293
	294	return sh_qspi_xfer_common(ss, bitlen, dout, din, flags);
	295	}
	296
	297	#else
	298
	299	#include <dm.h>
	300
	301	static int sh_qspi_xfer(struct udevice *dev, unsigned int bitlen,
	302	const void dout, void din, unsigned long flags)
	303	{
	304	struct udevice *bus = dev->parent;
	305	struct sh_qspi_slave *ss = dev_get_platdata(bus);
	306
	307	return sh_qspi_xfer_common(ss, bitlen, dout, din, flags);
	308	}
	309
	310	static int sh_qspi_set_speed(struct udevice *dev, uint speed)
	311	{
	312	/* This is a SPI NOR controller, do nothing. */
	313	return 0;
	314	}
315
316	static int sh_qspi_set_mode(struct udevice *dev, uint mode)
317	{
318	/* This is a SPI NOR controller, do nothing. */
319	return 0;
320	}
321
322	static int sh_qspi_probe(struct udevice *dev)
323	{
324	struct sh_qspi_slave *ss = dev_get_platdata(dev);
325
326	sh_qspi_init(ss);
327
328	return 0;
329	}
330
331	static int sh_qspi_ofdata_to_platdata(struct udevice *dev)
332	{
333	struct sh_qspi_slave *plat = dev_get_platdata(dev);
334
335	plat->regs = (struct sh_qspi_regs *)dev_read_addr(dev);
336
337	return 0;
338	}
339
340	static const struct dm_spi_ops sh_qspi_ops = {
341	.xfer = sh_qspi_xfer,
342	.set_speed = sh_qspi_set_speed,
343	.set_mode = sh_qspi_set_mode,
344	};
345
346	static const struct udevice_id sh_qspi_ids[] = {
347	{ .compatible = "renesas,qspi" },
348	{ }
349	};
350
351	U_BOOT_DRIVER(sh_qspi) = {
352	.name = "sh_qspi",
353	.id = UCLASS_SPI,
354	.of_match = sh_qspi_ids,
355	.ops = &sh_qspi_ops,
356	.ofdata_to_platdata = sh_qspi_ofdata_to_platdata,
357	.platdata_auto_alloc_size = sizeof(struct sh_qspi_slave),
358	.probe = sh_qspi_probe,
359	};
360	#endif