projects / J-u-boot.git / blame
| Commit | Line | Data |
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| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
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2 | /* |
| 3 | * Bluewater Systems Snapper 9260 and 9G20 modules | |
| 4 | * | |
| 5 | * (C) Copyright 2011 Bluewater Systems | |
| 6 | * Author: Andre Renaud <[email protected]> | |
| 7 | * Author: Ryan Mallon <[email protected]> | |
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8 | */ |
| 9 | ||
| 10 | #ifndef __CONFIG_H | |
| 11 | #define __CONFIG_H | |
| 12 | ||
| 13 | /* SoC type is defined in boards.cfg */ | |
| 14 | #include <asm/hardware.h> | |
| 1ace4022 | 15 | #include <linux/sizes.h> |
| b8d41dda | 16 | |
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17 | /* ARM asynchronous clock */ |
| 18 | #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */ | |
| 19 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 | |
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20 | |
| 21 | /* CPU */ | |
| b8d41dda | 22 | |
| b8d41dda | 23 | /* SDRAM */ |
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24 | #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 |
| 25 | #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */ | |
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26 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 |
| 27 | #define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 | |
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28 | |
| 29 | /* Mem test settings */ | |
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30 | |
| 31 | /* NAND Flash */ | |
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32 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 33 | #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 | |
| 34 | #define CONFIG_SYS_NAND_DBW_8 | |
| 35 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */ | |
| 36 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */ | |
| 37 | #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 | |
| 38 | #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 | |
| 39 | ||
| b8d41dda | 40 | /* USB */ |
| b8d41dda | 41 | #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE |
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42 | |
| 43 | /* GPIOs and IO expander */ | |
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44 | #define CONFIG_PCA953X |
| 45 | #define CONFIG_SYS_I2C_PCA953X_ADDR 0x28 | |
| 46 | #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x28, 16} } | |
| 47 | ||
| 48 | /* UARTs/Serial console */ | |
| 1a1927f3 | 49 | #ifndef CONFIG_DM_SERIAL |
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50 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU |
| 51 | #define CONFIG_USART_ID ATMEL_ID_SYS | |
| 1a1927f3 | 52 | #endif |
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53 | |
| 54 | /* I2C - Bit-bashed */ | |
| b8d41dda | 55 | #define CONFIG_SOFT_I2C_READ_REPEATED_START |
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56 | #define I2C_INIT do { \ |
| 57 | at91_set_gpio_output(AT91_PIN_PA23, 1); \ | |
| 58 | at91_set_gpio_output(AT91_PIN_PA24, 1); \ | |
| 59 | at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \ | |
| 60 | at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \ | |
| 61 | } while (0) | |
| 62 | #define I2C_SOFT_DECLARATIONS | |
| 63 | #define I2C_ACTIVE | |
| 64 | #define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PA23, 1); | |
| 65 | #define I2C_READ at91_get_gpio_value(AT91_PIN_PA23); | |
| 66 | #define I2C_SDA(bit) do { \ | |
| 67 | if (bit) { \ | |
| 68 | at91_set_gpio_input(AT91_PIN_PA23, 1); \ | |
| 69 | } else { \ | |
| 70 | at91_set_gpio_output(AT91_PIN_PA23, 1); \ | |
| 71 | at91_set_gpio_value(AT91_PIN_PA23, bit); \ | |
| 72 | } \ | |
| 73 | } while (0) | |
| 74 | #define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) | |
| 75 | #define I2C_DELAY udelay(2) | |
| 76 | ||
| 77 | /* Boot options */ | |
| b8d41dda | 78 | |
| b8d41dda | 79 | /* Environment settings */ |
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80 | |
| 81 | /* Console settings */ | |
| b8d41dda | 82 | |
| b8d41dda | 83 | #endif /* __CONFIG_H */ |