[J-u-boot.git] / drivers / spi / zynq_spi.c

/*
 * (C) Copyright 2013 Xilinx, Inc.
 * (C) Copyright 2015 Jagan Teki <[email protected]>
 *
 * Xilinx Zynq PS SPI controller driver (master mode only)
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <malloc.h>
#include <spi.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

/* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
#define ZYNQ_SPI_CR_MSA_MASK		BIT(15)	/* Manual start enb */
#define ZYNQ_SPI_CR_MCS_MASK		BIT(14)	/* Manual chip select */
#define ZYNQ_SPI_CR_CS_MASK		GENMASK(13, 10)	/* Chip select */
#define ZYNQ_SPI_CR_BAUD_MASK		GENMASK(5, 3)	/* Baud rate div */
#define ZYNQ_SPI_CR_CPHA_MASK		BIT(2)	/* Clock phase */
#define ZYNQ_SPI_CR_CPOL_MASK		BIT(1)	/* Clock polarity */
#define ZYNQ_SPI_CR_MSTREN_MASK		BIT(0)	/* Mode select */
#define ZYNQ_SPI_IXR_RXNEMPTY_MASK	BIT(4)	/* RX_FIFO_not_empty */
#define ZYNQ_SPI_IXR_TXOW_MASK		BIT(2)	/* TX_FIFO_not_full */
#define ZYNQ_SPI_IXR_ALL_MASK		GENMASK(6, 0)	/* All IXR bits */
#define ZYNQ_SPI_ENR_SPI_EN_MASK	BIT(0)	/* SPI Enable */

#define ZYNQ_SPI_CR_BAUD_MAX		8	/* Baud rate divisor max val */
#define ZYNQ_SPI_CR_BAUD_SHIFT		3	/* Baud rate divisor shift */
#define ZYNQ_SPI_CR_SS_SHIFT		10	/* Slave select shift */

#define ZYNQ_SPI_FIFO_DEPTH		128
#ifndef CONFIG_SYS_ZYNQ_SPI_WAIT
#define CONFIG_SYS_ZYNQ_SPI_WAIT	(CONFIG_SYS_HZ/100)	/* 10 ms */
#endif

/* zynq spi register set */
struct zynq_spi_regs {
	u32 cr;		/* 0x00 */
	u32 isr;	/* 0x04 */
	u32 ier;	/* 0x08 */
	u32 idr;	/* 0x0C */
	u32 imr;	/* 0x10 */
	u32 enr;	/* 0x14 */
	u32 dr;		/* 0x18 */
	u32 txdr;	/* 0x1C */
	u32 rxdr;	/* 0x20 */
};


/* zynq spi platform data */
struct zynq_spi_platdata {
	struct zynq_spi_regs *regs;
	u32 frequency;		/* input frequency */
	u32 speed_hz;
};

/* zynq spi priv */
struct zynq_spi_priv {
	struct zynq_spi_regs *regs;
	u8 cs;
	u8 mode;
	u8 fifo_depth;
	u32 freq;		/* required frequency */
};

static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
{
	struct zynq_spi_platdata *plat = bus->platdata;
	const void *blob = gd->fdt_blob;
	int node = bus->of_offset;

	plat->regs = (struct zynq_spi_regs *)dev_get_addr(bus);

	/* FIXME: Use 250MHz as a suitable default */
	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
					250000000);
	plat->speed_hz = plat->frequency / 2;

	debug("%s: regs=%p max-frequency=%d\n", __func__,
	      plat->regs, plat->frequency);

	return 0;
}

static void zynq_spi_init_hw(struct zynq_spi_priv *priv)
{
	struct zynq_spi_regs *regs = priv->regs;
	u32 confr;

	/* Disable SPI */
	confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
	writel(~confr, &regs->enr);

	/* Disable Interrupts */
	writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->idr);

	/* Clear RX FIFO */
	while (readl(&regs->isr) &
			ZYNQ_SPI_IXR_RXNEMPTY_MASK)
		readl(&regs->rxdr);

	/* Clear Interrupts */
	writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->isr);

	/* Manual slave select and Auto start */
	confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK |
		ZYNQ_SPI_CR_MSTREN_MASK;
	confr &= ~ZYNQ_SPI_CR_MSA_MASK;
	writel(confr, &regs->cr);

	/* Enable SPI */
	writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
}

static int zynq_spi_probe(struct udevice *bus)
{
	struct zynq_spi_platdata *plat = dev_get_platdata(bus);
	struct zynq_spi_priv *priv = dev_get_priv(bus);

	priv->regs = plat->regs;
	priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;

	/* init the zynq spi hw */
	zynq_spi_init_hw(priv);

	return 0;
}

static void spi_cs_activate(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct zynq_spi_priv *priv = dev_get_priv(bus);
	struct zynq_spi_regs *regs = priv->regs;
	u32 cr;

	clrbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
	cr = readl(&regs->cr);
	/*
	 * CS cal logic: CS[13:10]
	 * xxx0	- cs0
	 * xx01	- cs1
	 * x011 - cs2
	 */
	cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
	writel(cr, &regs->cr);
}

static void spi_cs_deactivate(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct zynq_spi_priv *priv = dev_get_priv(bus);
	struct zynq_spi_regs *regs = priv->regs;

	setbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
}

static int zynq_spi_claim_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct zynq_spi_priv *priv = dev_get_priv(bus);
	struct zynq_spi_regs *regs = priv->regs;

	writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);

	return 0;
}

static int zynq_spi_release_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct zynq_spi_priv *priv = dev_get_priv(bus);
	struct zynq_spi_regs *regs = priv->regs;
	u32 confr;

	confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
	writel(~confr, &regs->enr);

	return 0;
}

static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
			    const void *dout, void *din, unsigned long flags)
{
	struct udevice *bus = dev->parent;
	struct zynq_spi_priv *priv = dev_get_priv(bus);
	struct zynq_spi_regs *regs = priv->regs;
	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
	u32 len = bitlen / 8;
	u32 tx_len = len, rx_len = len, tx_tvl;
	const u8 *tx_buf = dout;
	u8 *rx_buf = din, buf;
	u32 ts, status;

	debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
	      bus->seq, slave_plat->cs, bitlen, len, flags);

	if (bitlen % 8) {
		debug("spi_xfer: Non byte aligned SPI transfer\n");
		return -1;
	}

	priv->cs = slave_plat->cs;
	if (flags & SPI_XFER_BEGIN)
		spi_cs_activate(dev);

	while (rx_len > 0) {
		/* Write the data into TX FIFO - tx threshold is fifo_depth */
		tx_tvl = 0;
		while ((tx_tvl < priv->fifo_depth) && tx_len) {
			if (tx_buf)
				buf = *tx_buf++;
			else
				buf = 0;
			writel(buf, &regs->txdr);
			tx_len--;
			tx_tvl++;
		}

		/* Check TX FIFO completion */
		ts = get_timer(0);
		status = readl(&regs->isr);
		while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
			if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) {
				printf("spi_xfer: Timeout! TX FIFO not full\n");
				return -1;
			}
			status = readl(&regs->isr);
		}

		/* Read the data from RX FIFO */
		status = readl(&regs->isr);
		while ((status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) && rx_len) {
			buf = readl(&regs->rxdr);
			if (rx_buf)
				*rx_buf++ = buf;
			status = readl(&regs->isr);
			rx_len--;
		}
	}

	if (flags & SPI_XFER_END)
		spi_cs_deactivate(dev);

	return 0;
}

static int zynq_spi_set_speed(struct udevice *bus, uint speed)
{
	struct zynq_spi_platdata *plat = bus->platdata;
	struct zynq_spi_priv *priv = dev_get_priv(bus);
	struct zynq_spi_regs *regs = priv->regs;
	uint32_t confr;
	u8 baud_rate_val = 0;

	if (speed > plat->frequency)
		speed = plat->frequency;

	/* Set the clock frequency */
	confr = readl(&regs->cr);
	if (speed == 0) {
		/* Set baudrate x8, if the freq is 0 */
		baud_rate_val = 0x2;
	} else if (plat->speed_hz != speed) {
		while ((baud_rate_val < ZYNQ_SPI_CR_BAUD_MAX) &&
				((plat->frequency /
				(2 << baud_rate_val)) > speed))
			baud_rate_val++;
		plat->speed_hz = speed / (2 << baud_rate_val);
	}
	confr &= ~ZYNQ_SPI_CR_BAUD_MASK;
	confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT);

	writel(confr, &regs->cr);
	priv->freq = speed;

	debug("zynq_spi_set_speed: regs=%p, speed=%d\n",
	      priv->regs, priv->freq);

	return 0;
}

static int zynq_spi_set_mode(struct udevice *bus, uint mode)
{
	struct zynq_spi_priv *priv = dev_get_priv(bus);
	struct zynq_spi_regs *regs = priv->regs;
	uint32_t confr;

	/* Set the SPI Clock phase and polarities */
	confr = readl(&regs->cr);
	confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);

	if (mode & SPI_CPHA)
		confr |= ZYNQ_SPI_CR_CPHA_MASK;
	if (mode & SPI_CPOL)
		confr |= ZYNQ_SPI_CR_CPOL_MASK;

	writel(confr, &regs->cr);
	priv->mode = mode;

	debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode);

	return 0;
}

static const struct dm_spi_ops zynq_spi_ops = {
	.claim_bus	= zynq_spi_claim_bus,
	.release_bus	= zynq_spi_release_bus,
	.xfer		= zynq_spi_xfer,
	.set_speed	= zynq_spi_set_speed,
	.set_mode	= zynq_spi_set_mode,
};

static const struct udevice_id zynq_spi_ids[] = {
	{ .compatible = "xlnx,zynq-spi-r1p6" },
	{ .compatible = "cdns,spi-r1p6" },
	{ }
};

U_BOOT_DRIVER(zynq_spi) = {
	.name	= "zynq_spi",
	.id	= UCLASS_SPI,
	.of_match = zynq_spi_ids,
	.ops	= &zynq_spi_ops,
	.ofdata_to_platdata = zynq_spi_ofdata_to_platdata,
	.platdata_auto_alloc_size = sizeof(struct zynq_spi_platdata),
	.priv_auto_alloc_size = sizeof(struct zynq_spi_priv),
	.probe	= zynq_spi_probe,
};
Commit	Line	Data
1465d055	1	/*
86e99b98	2	* (C) Copyright 2013 Xilinx, Inc.
b1c82da2	3	* (C) Copyright 2015 Jagan Teki <[email protected]>
1465d055 JT	4	*
	5	* Xilinx Zynq PS SPI controller driver (master mode only)
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9
1465d055	10	#include <common.h>
b1c82da2	11	#include <dm.h>
1465d055 JT	12	#include <malloc.h>
	13	#include <spi.h>
	14	#include <asm/io.h>
1465d055	15
cdc9dd07 JT	16	DECLARE_GLOBAL_DATA_PTR;
cdc9dd07 JT	17
1465d055	18	/* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
736b4df1 JT	19	#define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */
736b4df1 JT	20	#define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */
9cf2ffb3 JT	21	#define ZYNQ_SPI_CR_CS_MASK GENMASK(13, 10) /* Chip select */
9cf2ffb3 JT	22	#define ZYNQ_SPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
736b4df1 JT	23	#define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */
	24	#define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
	25	#define ZYNQ_SPI_CR_MSTREN_MASK BIT(0) /* Mode select */
	26	#define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
	27	#define ZYNQ_SPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
9cf2ffb3	28	#define ZYNQ_SPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
736b4df1	29	#define ZYNQ_SPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
1465d055	30
46ab8a6a JT	31	#define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
	32	#define ZYNQ_SPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
	33	#define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */
	34
1465d055 JT	35	#define ZYNQ_SPI_FIFO_DEPTH 128
	36	#ifndef CONFIG_SYS_ZYNQ_SPI_WAIT
	37	#define CONFIG_SYS_ZYNQ_SPI_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
	38	#endif
	39
	40	/* zynq spi register set */
	41	struct zynq_spi_regs {
	42	u32 cr; /* 0x00 */
	43	u32 isr; /* 0x04 */
	44	u32 ier; /* 0x08 */
	45	u32 idr; /* 0x0C */
	46	u32 imr; /* 0x10 */
	47	u32 enr; /* 0x14 */
	48	u32 dr; /* 0x18 */
	49	u32 txdr; /* 0x1C */
	50	u32 rxdr; /* 0x20 */
	51	};
	52
b1c82da2 JT	53
	54	/* zynq spi platform data */
	55	struct zynq_spi_platdata {
	56	struct zynq_spi_regs *regs;
	57	u32 frequency; /* input frequency */
1465d055	58	u32 speed_hz;
1465d055 JT	59	};
1465d055 JT	60
b1c82da2 JT	61	/* zynq spi priv */
	62	struct zynq_spi_priv {
	63	struct zynq_spi_regs *regs;
19126998	64	u8 cs;
b1c82da2 JT	65	u8 mode;
	66	u8 fifo_depth;
	67	u32 freq; /* required frequency */
	68	};
1465d055	69
b1c82da2	70	static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
1465d055	71	{
b1c82da2	72	struct zynq_spi_platdata *plat = bus->platdata;
cdc9dd07 JT	73	const void *blob = gd->fdt_blob;
	74	int node = bus->of_offset;
	75
4e9838c1	76	plat->regs = (struct zynq_spi_regs *)dev_get_addr(bus);
b1c82da2	77
cdc9dd07 JT	78	/* FIXME: Use 250MHz as a suitable default */
	79	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
	80	250000000);
b1c82da2 JT	81	plat->speed_hz = plat->frequency / 2;
b1c82da2 JT	82
80fd9792	83	debug("%s: regs=%p max-frequency=%d\n", __func__,
cdc9dd07 JT	84	plat->regs, plat->frequency);
cdc9dd07 JT	85
b1c82da2 JT	86	return 0;
	87	}
	88
	89	static void zynq_spi_init_hw(struct zynq_spi_priv *priv)
	90	{
	91	struct zynq_spi_regs *regs = priv->regs;
1465d055 JT	92	u32 confr;
	93
	94	/* Disable SPI */
5f647c22 MS	95	confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
5f647c22 MS	96	writel(~confr, &regs->enr);
1465d055 JT	97
1465d055 JT	98	/* Disable Interrupts */
b1c82da2	99	writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->idr);
1465d055 JT	100
1465d055 JT	101	/* Clear RX FIFO */
b1c82da2	102	while (readl(&regs->isr) &
1465d055	103	ZYNQ_SPI_IXR_RXNEMPTY_MASK)
b1c82da2	104	readl(&regs->rxdr);
1465d055 JT	105
1465d055 JT	106	/* Clear Interrupts */
b1c82da2	107	writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->isr);
1465d055 JT	108
	109	/* Manual slave select and Auto start */
	110	confr = ZYNQ_SPI_CR_MCS_MASK \| ZYNQ_SPI_CR_CS_MASK \|
	111	ZYNQ_SPI_CR_MSTREN_MASK;
	112	confr &= ~ZYNQ_SPI_CR_MSA_MASK;
b1c82da2	113	writel(confr, &regs->cr);
1465d055 JT	114
1465d055 JT	115	/* Enable SPI */
b1c82da2	116	writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
1465d055 JT	117	}
1465d055 JT	118
b1c82da2	119	static int zynq_spi_probe(struct udevice *bus)
1465d055	120	{
b1c82da2 JT	121	struct zynq_spi_platdata *plat = dev_get_platdata(bus);
	122	struct zynq_spi_priv *priv = dev_get_priv(bus);
	123
	124	priv->regs = plat->regs;
	125	priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;
	126
	127	/* init the zynq spi hw */
	128	zynq_spi_init_hw(priv);
	129
	130	return 0;
1465d055 JT	131	}
1465d055 JT	132
19126998	133	static void spi_cs_activate(struct udevice *dev)
1465d055	134	{
b1c82da2 JT	135	struct udevice *bus = dev->parent;
	136	struct zynq_spi_priv *priv = dev_get_priv(bus);
	137	struct zynq_spi_regs *regs = priv->regs;
1465d055 JT	138	u32 cr;
1465d055 JT	139
b1c82da2 JT	140	clrbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
b1c82da2 JT	141	cr = readl(&regs->cr);
1465d055 JT	142	/*
	143	* CS cal logic: CS[13:10]
	144	* xxx0 - cs0
	145	* xx01 - cs1
	146	* x011 - cs2
	147	*/
19126998	148	cr \|= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
b1c82da2	149	writel(cr, &regs->cr);
1465d055 JT	150	}
1465d055 JT	151
b1c82da2	152	static void spi_cs_deactivate(struct udevice *dev)
1465d055	153	{
b1c82da2 JT	154	struct udevice *bus = dev->parent;
	155	struct zynq_spi_priv *priv = dev_get_priv(bus);
	156	struct zynq_spi_regs *regs = priv->regs;
1465d055	157
b1c82da2	158	setbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
1465d055 JT	159	}
1465d055 JT	160
b1c82da2	161	static int zynq_spi_claim_bus(struct udevice *dev)
1465d055	162	{
b1c82da2 JT	163	struct udevice *bus = dev->parent;
	164	struct zynq_spi_priv *priv = dev_get_priv(bus);
	165	struct zynq_spi_regs *regs = priv->regs;
1465d055	166
b1c82da2	167	writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
1465d055	168
b1c82da2	169	return 0;
1465d055 JT	170	}
1465d055 JT	171
b1c82da2	172	static int zynq_spi_release_bus(struct udevice *dev)
1465d055	173	{
b1c82da2 JT	174	struct udevice *bus = dev->parent;
	175	struct zynq_spi_priv *priv = dev_get_priv(bus);
	176	struct zynq_spi_regs *regs = priv->regs;
5f647c22	177	u32 confr;
1465d055	178
5f647c22 MS	179	confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
5f647c22 MS	180	writel(~confr, &regs->enr);
1465d055 JT	181
	182	return 0;
	183	}
	184
b1c82da2 JT	185	static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
b1c82da2 JT	186	const void dout, void din, unsigned long flags)
1465d055	187	{
b1c82da2 JT	188	struct udevice *bus = dev->parent;
	189	struct zynq_spi_priv *priv = dev_get_priv(bus);
	190	struct zynq_spi_regs *regs = priv->regs;
	191	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
1465d055 JT	192	u32 len = bitlen / 8;
	193	u32 tx_len = len, rx_len = len, tx_tvl;
	194	const u8 *tx_buf = dout;
	195	u8 *rx_buf = din, buf;
	196	u32 ts, status;
	197
	198	debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
b1c82da2	199	bus->seq, slave_plat->cs, bitlen, len, flags);
1465d055	200
1465d055 JT	201	if (bitlen % 8) {
	202	debug("spi_xfer: Non byte aligned SPI transfer\n");
	203	return -1;
	204	}
	205
19126998	206	priv->cs = slave_plat->cs;
1465d055	207	if (flags & SPI_XFER_BEGIN)
19126998	208	spi_cs_activate(dev);
1465d055 JT	209
	210	while (rx_len > 0) {
	211	/* Write the data into TX FIFO - tx threshold is fifo_depth */
	212	tx_tvl = 0;
b1c82da2	213	while ((tx_tvl < priv->fifo_depth) && tx_len) {
1465d055 JT	214	if (tx_buf)
	215	buf = *tx_buf++;
	216	else
	217	buf = 0;
b1c82da2	218	writel(buf, &regs->txdr);
1465d055 JT	219	tx_len--;
	220	tx_tvl++;
	221	}
	222
	223	/* Check TX FIFO completion */
	224	ts = get_timer(0);
b1c82da2	225	status = readl(&regs->isr);
1465d055 JT	226	while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
	227	if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) {
	228	printf("spi_xfer: Timeout! TX FIFO not full\n");
	229	return -1;
	230	}
b1c82da2	231	status = readl(&regs->isr);
1465d055 JT	232	}
	233
	234	/* Read the data from RX FIFO */
b1c82da2	235	status = readl(&regs->isr);
d2998286	236	while ((status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) && rx_len) {
b1c82da2	237	buf = readl(&regs->rxdr);
1465d055 JT	238	if (rx_buf)
1465d055 JT	239	*rx_buf++ = buf;
b1c82da2	240	status = readl(&regs->isr);
1465d055 JT	241	rx_len--;
	242	}
	243	}
	244
	245	if (flags & SPI_XFER_END)
b1c82da2 JT	246	spi_cs_deactivate(dev);
	247
	248	return 0;
	249	}
	250
	251	static int zynq_spi_set_speed(struct udevice *bus, uint speed)
	252	{
	253	struct zynq_spi_platdata *plat = bus->platdata;
	254	struct zynq_spi_priv *priv = dev_get_priv(bus);
	255	struct zynq_spi_regs *regs = priv->regs;
	256	uint32_t confr;
	257	u8 baud_rate_val = 0;
	258
	259	if (speed > plat->frequency)
	260	speed = plat->frequency;
	261
	262	/* Set the clock frequency */
	263	confr = readl(&regs->cr);
	264	if (speed == 0) {
	265	/* Set baudrate x8, if the freq is 0 */
	266	baud_rate_val = 0x2;
	267	} else if (plat->speed_hz != speed) {
46ab8a6a	268	while ((baud_rate_val < ZYNQ_SPI_CR_BAUD_MAX) &&
b1c82da2 JT	269	((plat->frequency /
	270	(2 << baud_rate_val)) > speed))
	271	baud_rate_val++;
	272	plat->speed_hz = speed / (2 << baud_rate_val);
	273	}
dda6241a	274	confr &= ~ZYNQ_SPI_CR_BAUD_MASK;
46ab8a6a	275	confr \|= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT);
b1c82da2 JT	276
	277	writel(confr, &regs->cr);
	278	priv->freq = speed;
	279
a22bba81 JT	280	debug("zynq_spi_set_speed: regs=%p, speed=%d\n",
a22bba81 JT	281	priv->regs, priv->freq);
b1c82da2 JT	282
	283	return 0;
	284	}
	285
	286	static int zynq_spi_set_mode(struct udevice *bus, uint mode)
	287	{
	288	struct zynq_spi_priv *priv = dev_get_priv(bus);
	289	struct zynq_spi_regs *regs = priv->regs;
	290	uint32_t confr;
	291
	292	/* Set the SPI Clock phase and polarities */
	293	confr = readl(&regs->cr);
	294	confr &= ~(ZYNQ_SPI_CR_CPHA_MASK \| ZYNQ_SPI_CR_CPOL_MASK);
	295
a22bba81	296	if (mode & SPI_CPHA)
b1c82da2	297	confr \|= ZYNQ_SPI_CR_CPHA_MASK;
a22bba81	298	if (mode & SPI_CPOL)
b1c82da2 JT	299	confr \|= ZYNQ_SPI_CR_CPOL_MASK;
	300
	301	writel(confr, &regs->cr);
	302	priv->mode = mode;
	303
	304	debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode);
1465d055 JT	305
	306	return 0;
	307	}
b1c82da2 JT	308
	309	static const struct dm_spi_ops zynq_spi_ops = {
	310	.claim_bus = zynq_spi_claim_bus,
	311	.release_bus = zynq_spi_release_bus,
	312	.xfer = zynq_spi_xfer,
	313	.set_speed = zynq_spi_set_speed,
	314	.set_mode = zynq_spi_set_mode,
	315	};
	316
	317	static const struct udevice_id zynq_spi_ids[] = {
40b383fa	318	{ .compatible = "xlnx,zynq-spi-r1p6" },
23ef5aea	319	{ .compatible = "cdns,spi-r1p6" },
b1c82da2 JT	320	{ }
	321	};
	322
	323	U_BOOT_DRIVER(zynq_spi) = {
	324	.name = "zynq_spi",
	325	.id = UCLASS_SPI,
	326	.of_match = zynq_spi_ids,
	327	.ops = &zynq_spi_ops,
	328	.ofdata_to_platdata = zynq_spi_ofdata_to_platdata,
	329	.platdata_auto_alloc_size = sizeof(struct zynq_spi_platdata),
	330	.priv_auto_alloc_size = sizeof(struct zynq_spi_priv),
	331	.probe = zynq_spi_probe,
	332	};