[J-u-boot.git] / drivers / spi / ich.h

/*
 * Copyright (c) 2011 The Chromium OS Authors.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * This file is derived from the flashrom project.
 */

#ifndef _ICH_H_
#define _ICH_H_

struct ich7_spi_regs {
	uint16_t spis;
	uint16_t spic;
	uint32_t spia;
	uint64_t spid[8];
	uint64_t _pad;
	uint32_t bbar;
	uint16_t preop;
	uint16_t optype;
	uint8_t opmenu[8];
} __packed;

struct ich9_spi_regs {
	uint32_t bfpr;		/* 0x00 */
	uint16_t hsfs;
	uint16_t hsfc;
	uint32_t faddr;
	uint32_t _reserved0;
	uint32_t fdata[16];	/* 0x10 */
	uint32_t frap;		/* 0x50 */
	uint32_t freg[5];
	uint32_t _reserved1[3];
	uint32_t pr[5];		/* 0x74 */
	uint32_t _reserved2[2];
	uint8_t ssfs;		/* 0x90 */
	uint8_t ssfc[3];
	uint16_t preop;		/* 0x94 */
	uint16_t optype;
	uint8_t opmenu[8];	/* 0x98 */
	uint32_t bbar;
	uint8_t _reserved3[12];
	uint32_t fdoc;		/* 0xb0 */
	uint32_t fdod;
	uint8_t _reserved4[8];
	uint32_t afc;		/* 0xc0 */
	uint32_t lvscc;
	uint32_t uvscc;
	uint8_t _reserved5[4];
	uint32_t fpb;		/* 0xd0 */
	uint8_t _reserved6[28];
	uint32_t srdl;		/* 0xf0 */
	uint32_t srdc;
	uint32_t scs;
	uint32_t bcr;
} __packed;

enum {
	SPIS_SCIP =		0x0001,
	SPIS_GRANT =		0x0002,
	SPIS_CDS =		0x0004,
	SPIS_FCERR =		0x0008,
	SSFS_AEL =		0x0010,
	SPIS_LOCK =		0x8000,
	SPIS_RESERVED_MASK =	0x7ff0,
	SSFS_RESERVED_MASK =	0x7fe2
};

enum {
	SPIC_SCGO =		0x000002,
	SPIC_ACS =		0x000004,
	SPIC_SPOP =		0x000008,
	SPIC_DBC =		0x003f00,
	SPIC_DS =		0x004000,
	SPIC_SME =		0x008000,
	SSFC_SCF_MASK =		0x070000,
	SSFC_RESERVED =		0xf80000,

	/* Mask for speed byte, biuts 23:16 of SSFC */
	SSFC_SCF_33MHZ	=	0x01,
};

enum {
	HSFS_FDONE =		0x0001,
	HSFS_FCERR =		0x0002,
	HSFS_AEL =		0x0004,
	HSFS_BERASE_MASK =	0x0018,
	HSFS_BERASE_SHIFT =	3,
	HSFS_SCIP =		0x0020,
	HSFS_FDOPSS =		0x2000,
	HSFS_FDV =		0x4000,
	HSFS_FLOCKDN =		0x8000
};

enum {
	HSFC_FGO =		0x0001,
	HSFC_FCYCLE_MASK =	0x0006,
	HSFC_FCYCLE_SHIFT =	1,
	HSFC_FDBC_MASK =	0x3f00,
	HSFC_FDBC_SHIFT =	8,
	HSFC_FSMIE =		0x8000
};

enum {
	SPI_OPCODE_TYPE_READ_NO_ADDRESS =	0,
	SPI_OPCODE_TYPE_WRITE_NO_ADDRESS =	1,
	SPI_OPCODE_TYPE_READ_WITH_ADDRESS =	2,
	SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS =	3
};

enum {
	ICH_MAX_CMD_LEN		= 5,
};

struct spi_trans {
	uint8_t cmd[ICH_MAX_CMD_LEN];
	int cmd_len;
	const uint8_t *out;
	uint32_t bytesout;
	uint8_t *in;
	uint32_t bytesin;
	uint8_t type;
	uint8_t opcode;
	uint32_t offset;
};

#define SPI_OPCODE_WREN		0x06
#define SPI_OPCODE_FAST_READ	0x0b

enum ich_version {
	ICHV_7,
	ICHV_9,
};

struct ich_spi_platdata {
	enum ich_version ich_version;	/* Controller version, 7 or 9 */
};

struct ich_spi_priv {
	int ichspi_lock;
	int locked;
	int opmenu;
	int menubytes;
	void *base;		/* Base of register set */
	int preop;
	int optype;
	int addr;
	int data;
	unsigned databytes;
	int status;
	int control;
	int bbar;
	int bcr;
	uint32_t *pr;		/* only for ich9 */
	int speed;		/* pointer to speed control */
	ulong max_speed;	/* Maximum bus speed in MHz */
	ulong cur_speed;	/* Current bus speed */
	struct spi_trans trans;	/* current transaction in progress */
};

#endif /* _ICH_H_ */
Commit	Line	Data
1853030e SG	1	/*
	2	* Copyright (c) 2011 The Chromium OS Authors.
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
1853030e SG	5	*
	6	* This file is derived from the flashrom project.
	7	*/
	8
9eb4339b BM	9	#ifndef _ICH_H_
	10	#define _ICH_H_
	11
1853030e SG	12	struct ich7_spi_regs {
	13	uint16_t spis;
	14	uint16_t spic;
	15	uint32_t spia;
	16	uint64_t spid[8];
	17	uint64_t _pad;
	18	uint32_t bbar;
	19	uint16_t preop;
	20	uint16_t optype;
	21	uint8_t opmenu[8];
	22	} __packed;
	23
	24	struct ich9_spi_regs {
9eb4339b	25	uint32_t bfpr; /* 0x00 */
1853030e SG	26	uint16_t hsfs;
	27	uint16_t hsfc;
	28	uint32_t faddr;
	29	uint32_t _reserved0;
9eb4339b BM	30	uint32_t fdata[16]; /* 0x10 */
9eb4339b BM	31	uint32_t frap; /* 0x50 */
1853030e SG	32	uint32_t freg[5];
1853030e SG	33	uint32_t _reserved1[3];
9eb4339b	34	uint32_t pr[5]; /* 0x74 */
1853030e	35	uint32_t _reserved2[2];
9eb4339b	36	uint8_t ssfs; /* 0x90 */
1853030e	37	uint8_t ssfc[3];
9eb4339b	38	uint16_t preop; /* 0x94 */
1853030e	39	uint16_t optype;
9eb4339b	40	uint8_t opmenu[8]; /* 0x98 */
1853030e SG	41	uint32_t bbar;
1853030e SG	42	uint8_t _reserved3[12];
9eb4339b	43	uint32_t fdoc; /* 0xb0 */
1853030e SG	44	uint32_t fdod;
1853030e SG	45	uint8_t _reserved4[8];
9eb4339b	46	uint32_t afc; /* 0xc0 */
1853030e SG	47	uint32_t lvscc;
	48	uint32_t uvscc;
	49	uint8_t _reserved5[4];
9eb4339b	50	uint32_t fpb; /* 0xd0 */
1853030e	51	uint8_t _reserved6[28];
9eb4339b	52	uint32_t srdl; /* 0xf0 */
1853030e	53	uint32_t srdc;
5093badb SG	54	uint32_t scs;
5093badb SG	55	uint32_t bcr;
1853030e SG	56	} __packed;
	57
	58	enum {
	59	SPIS_SCIP = 0x0001,
	60	SPIS_GRANT = 0x0002,
	61	SPIS_CDS = 0x0004,
	62	SPIS_FCERR = 0x0008,
	63	SSFS_AEL = 0x0010,
	64	SPIS_LOCK = 0x8000,
	65	SPIS_RESERVED_MASK = 0x7ff0,
	66	SSFS_RESERVED_MASK = 0x7fe2
	67	};
	68
	69	enum {
	70	SPIC_SCGO = 0x000002,
	71	SPIC_ACS = 0x000004,
	72	SPIC_SPOP = 0x000008,
	73	SPIC_DBC = 0x003f00,
	74	SPIC_DS = 0x004000,
	75	SPIC_SME = 0x008000,
	76	SSFC_SCF_MASK = 0x070000,
	77	SSFC_RESERVED = 0xf80000,
	78
	79	/* Mask for speed byte, biuts 23:16 of SSFC */
	80	SSFC_SCF_33MHZ = 0x01,
	81	};
	82
	83	enum {
	84	HSFS_FDONE = 0x0001,
	85	HSFS_FCERR = 0x0002,
	86	HSFS_AEL = 0x0004,
	87	HSFS_BERASE_MASK = 0x0018,
	88	HSFS_BERASE_SHIFT = 3,
	89	HSFS_SCIP = 0x0020,
	90	HSFS_FDOPSS = 0x2000,
	91	HSFS_FDV = 0x4000,
	92	HSFS_FLOCKDN = 0x8000
	93	};
	94
	95	enum {
	96	HSFC_FGO = 0x0001,
	97	HSFC_FCYCLE_MASK = 0x0006,
	98	HSFC_FCYCLE_SHIFT = 1,
	99	HSFC_FDBC_MASK = 0x3f00,
	100	HSFC_FDBC_SHIFT = 8,
	101	HSFC_FSMIE = 0x8000
	102	};
	103
	104	enum {
	105	SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0,
	106	SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1,
	107	SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2,
	108	SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3
	109	};
	110
	111	enum {
	112	ICH_MAX_CMD_LEN = 5,
	113	};
	114
	115	struct spi_trans {
	116	uint8_t cmd[ICH_MAX_CMD_LEN];
	117	int cmd_len;
	118	const uint8_t *out;
	119	uint32_t bytesout;
120	uint8_t *in;
121	uint32_t bytesin;
122	uint8_t type;
123	uint8_t opcode;
124	uint32_t offset;
125	};
126
9eb4339b BM	127	#define SPI_OPCODE_WREN 0x06
	128	#define SPI_OPCODE_FAST_READ 0x0b
	129
6e670b5c BM	130	enum ich_version {
	131	ICHV_7,
	132	ICHV_9,
	133	};
	134
9eb4339b	135	struct ich_spi_platdata {
6e670b5c	136	enum ich_version ich_version; /* Controller version, 7 or 9 */
9eb4339b BM	137	};
	138
	139	struct ich_spi_priv {
	140	int ichspi_lock;
	141	int locked;
	142	int opmenu;
	143	int menubytes;
	144	void base; / Base of register set */
	145	int preop;
	146	int optype;
	147	int addr;
	148	int data;
	149	unsigned databytes;
	150	int status;
	151	int control;
	152	int bbar;
	153	int bcr;
	154	uint32_t pr; / only for ich9 */
	155	int speed; /* pointer to speed control */
	156	ulong max_speed; /* Maximum bus speed in MHz */
	157	ulong cur_speed; /* Current bus speed */
1853030e	158	struct spi_trans trans; /* current transaction in progress */
1853030e	159	};
9eb4339b BM	160
9eb4339b BM	161	#endif /* _ICH_H_ */