[J-u-boot.git] / drivers / mmc / exynos_dw_mmc.c

/*
 * (C) Copyright 2012 SAMSUNG Electronics
 * Jaehoon Chung <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dwmmc.h>
#include <fdtdec.h>
#include <libfdt.h>
#include <malloc.h>
#include <asm/arch/dwmmc.h>
#include <asm/arch/clk.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/power.h>
#include <asm/gpio.h>
#include <asm-generic/errno.h>

#define	DWMMC_MAX_CH_NUM		4
#define	DWMMC_MAX_FREQ			52000000
#define	DWMMC_MIN_FREQ			400000
#define	DWMMC_MMC0_SDR_TIMING_VAL	0x03030001
#define	DWMMC_MMC2_SDR_TIMING_VAL	0x03020001

/* Exynos implmentation specific drver private data */
struct dwmci_exynos_priv_data {
	u32 sdr_timing;
};

/*
 * Function used as callback function to initialise the
 * CLKSEL register for every mmc channel.
 */
static void exynos_dwmci_clksel(struct dwmci_host *host)
{
	struct dwmci_exynos_priv_data *priv = host->priv;

	dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing);
}

unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq)
{
	unsigned long sclk;
	int8_t clk_div;

	/*
	 * Since SDCLKIN is divided inside controller by the DIVRATIO
	 * value set in the CLKSEL register, we need to use the same output
	 * clock value to calculate the CLKDIV value.
	 * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
	 */
	clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
			& DWMCI_DIVRATIO_MASK) + 1;
	sclk = get_mmc_clk(host->dev_index);

	/*
	 * Assume to know divider value.
	 * When clock unit is broken, need to set "host->div"
	 */
	return sclk / clk_div / (host->div + 1);
}

static void exynos_dwmci_board_init(struct dwmci_host *host)
{
	struct dwmci_exynos_priv_data *priv = host->priv;

	if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
		dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
		dwmci_writel(host, EMMCP_SEND0, 0);
		dwmci_writel(host, EMMCP_CTRL0,
			     MPSCTRL_SECURE_READ_BIT |
			     MPSCTRL_SECURE_WRITE_BIT |
			     MPSCTRL_NON_SECURE_READ_BIT |
			     MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
	}

	/* Set to timing value at initial time */
	if (priv->sdr_timing)
		exynos_dwmci_clksel(host);
}

static int exynos_dwmci_core_init(struct dwmci_host *host, int index)
{
	unsigned int div;
	unsigned long freq, sclk;
	struct dwmci_exynos_priv_data *priv = host->priv;

	if (host->bus_hz)
		freq = host->bus_hz;
	else
		freq = DWMMC_MAX_FREQ;

	/* request mmc clock vlaue of 52MHz.  */
	sclk = get_mmc_clk(index);
	div = DIV_ROUND_UP(sclk, freq);
	/* set the clock divisor for mmc */
	set_mmc_clk(index, div);

	host->name = "EXYNOS DWMMC";
#ifdef CONFIG_EXYNOS5420
	host->quirks = DWMCI_QUIRK_DISABLE_SMU;
#endif
	host->board_init = exynos_dwmci_board_init;

	if (!priv->sdr_timing) {
		if (index == 0)
			priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL;
		else if (index == 2)
			priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL;
	}

	host->caps = MMC_MODE_DDR_52MHz;
	host->clksel = exynos_dwmci_clksel;
	host->dev_index = index;
	host->get_mmc_clk = exynos_dwmci_get_clk;
	/* Add the mmc channel to be registered with mmc core */
	if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
		printf("DWMMC%d registration failed\n", index);
		return -1;
	}
	return 0;
}

/*
 * This function adds the mmc channel to be registered with mmc core.
 * index -	mmc channel number.
 * regbase -	register base address of mmc channel specified in 'index'.
 * bus_width -	operating bus width of mmc channel specified in 'index'.
 * clksel -	value to be written into CLKSEL register in case of FDT.
 *		NULL in case od non-FDT.
 */
int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
{
	struct dwmci_host *host = NULL;
	struct dwmci_exynos_priv_data *priv;

	host = malloc(sizeof(struct dwmci_host));
	if (!host) {
		error("dwmci_host malloc fail!\n");
		return -ENOMEM;
	}

	priv = malloc(sizeof(struct dwmci_exynos_priv_data));
	if (!priv) {
		error("dwmci_exynos_priv_data malloc fail!\n");
		return -ENOMEM;
	}

	host->ioaddr = (void *)regbase;
	host->buswidth = bus_width;

	if (clksel)
		priv->sdr_timing = clksel;

	host->priv = priv;

	return exynos_dwmci_core_init(host, index);
}

#if CONFIG_IS_ENABLED(OF_CONTROL)
static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM];

static int do_dwmci_init(struct dwmci_host *host)
{
	int index, flag, err;

	index = host->dev_index;

	flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
	err = exynos_pinmux_config(host->dev_id, flag);
	if (err) {
		printf("DWMMC%d not configure\n", index);
		return err;
	}

	return exynos_dwmci_core_init(host, index);
}

static int exynos_dwmci_get_config(const void *blob, int node,
					struct dwmci_host *host)
{
	int err = 0;
	u32 base, timing[3];
	struct dwmci_exynos_priv_data *priv;

	priv = malloc(sizeof(struct dwmci_exynos_priv_data));
	if (!priv) {
		error("dwmci_exynos_priv_data malloc fail!\n");
		return -ENOMEM;
	}

	/* Extract device id for each mmc channel */
	host->dev_id = pinmux_decode_periph_id(blob, node);

	host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
	if (host->dev_index == host->dev_id)
		host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;

	/* Get the bus width from the device node */
	host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
	if (host->buswidth <= 0) {
		printf("DWMMC%d: Can't get bus-width\n", host->dev_index);
		return -EINVAL;
	}

	/* Set the base address from the device node */
	base = fdtdec_get_addr(blob, node, "reg");
	if (!base) {
		printf("DWMMC%d: Can't get base address\n", host->dev_index);
		return -EINVAL;
	}
	host->ioaddr = (void *)base;

	/* Extract the timing info from the node */
	err =  fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3);
	if (err) {
		printf("DWMMC%d: Can't get sdr-timings for devider\n",
				host->dev_index);
		return -EINVAL;
	}

	priv->sdr_timing = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
			DWMCI_SET_DRV_CLK(timing[1]) |
			DWMCI_SET_DIV_RATIO(timing[2]));

	/* sdr_timing didn't assigned anything, use the default value */
	if (!priv->sdr_timing) {
		if (host->dev_index == 0)
			priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL;
		else if (host->dev_index == 2)
			priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL;
	}

	host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0);
	host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0);
	host->div = fdtdec_get_int(blob, node, "div", 0);

	host->priv = priv;

	return 0;
}

static int exynos_dwmci_process_node(const void *blob,
					int node_list[], int count)
{
	struct dwmci_host *host;
	int i, node, err;

	for (i = 0; i < count; i++) {
		node = node_list[i];
		if (node <= 0)
			continue;
		host = &dwmci_host[i];
		err = exynos_dwmci_get_config(blob, node, host);
		if (err) {
			printf("%s: failed to decode dev %d\n", __func__, i);
			return err;
		}

		do_dwmci_init(host);
	}
	return 0;
}

int exynos_dwmmc_init(const void *blob)
{
	int compat_id;
	int node_list[DWMMC_MAX_CH_NUM];
	int boot_dev_node;
	int err = 0, count;

	compat_id = COMPAT_SAMSUNG_EXYNOS_DWMMC;

	count = fdtdec_find_aliases_for_id(blob, "mmc",
				compat_id, node_list, DWMMC_MAX_CH_NUM);

	/* For DWMMC always set boot device as mmc 0 */
	if (count >= 3 && get_boot_mode() == BOOT_MODE_SD) {
		boot_dev_node = node_list[2];
		node_list[2] = node_list[0];
		node_list[0] = boot_dev_node;
	}

	err = exynos_dwmci_process_node(blob, node_list, count);

	return err;
}
#endif
Commit	Line	Data
d0ebbb8d JC	1	/*
	2	* (C) Copyright 2012 SAMSUNG Electronics
	3	* Jaehoon Chung <[email protected]>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
d0ebbb8d JC	6	*/
	7
	8	#include <common.h>
d0ebbb8d	9	#include <dwmmc.h>
a082a2dd A	10	#include <fdtdec.h>
	11	#include <libfdt.h>
	12	#include <malloc.h>
d0ebbb8d JC	13	#include <asm/arch/dwmmc.h>
d0ebbb8d JC	14	#include <asm/arch/clk.h>
a082a2dd	15	#include <asm/arch/pinmux.h>
64029f7a	16	#include <asm/arch/power.h>
959198f7 JC	17	#include <asm/gpio.h>
959198f7 JC	18	#include <asm-generic/errno.h>
d0ebbb8d	19
a082a2dd A	20	#define DWMMC_MAX_CH_NUM 4
	21	#define DWMMC_MAX_FREQ 52000000
	22	#define DWMMC_MIN_FREQ 400000
5dab81ce JC	23	#define DWMMC_MMC0_SDR_TIMING_VAL 0x03030001
	24	#define DWMMC_MMC2_SDR_TIMING_VAL 0x03020001
	25
	26	/* Exynos implmentation specific drver private data */
	27	struct dwmci_exynos_priv_data {
	28	u32 sdr_timing;
	29	};
d0ebbb8d	30
a082a2dd A	31	/*
	32	* Function used as callback function to initialise the
	33	* CLKSEL register for every mmc channel.
	34	*/
d0ebbb8d JC	35	static void exynos_dwmci_clksel(struct dwmci_host *host)
d0ebbb8d JC	36	{
5dab81ce JC	37	struct dwmci_exynos_priv_data *priv = host->priv;
	38
	39	dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing);
a082a2dd	40	}
d0ebbb8d	41
e3563f2e	42	unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq)
a082a2dd	43	{
d3e016cc RS	44	unsigned long sclk;
	45	int8_t clk_div;
	46
	47	/*
	48	* Since SDCLKIN is divided inside controller by the DIVRATIO
	49	* value set in the CLKSEL register, we need to use the same output
	50	* clock value to calculate the CLKDIV value.
	51	* as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
	52	*/
	53	clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
	54	& DWMCI_DIVRATIO_MASK) + 1;
	55	sclk = get_mmc_clk(host->dev_index);
	56
959198f7 JC	57	/*
	58	* Assume to know divider value.
	59	* When clock unit is broken, need to set "host->div"
	60	*/
	61	return sclk / clk_div / (host->div + 1);
d0ebbb8d JC	62	}
d0ebbb8d JC	63
18ab6755 JC	64	static void exynos_dwmci_board_init(struct dwmci_host *host)
18ab6755 JC	65	{
5dab81ce JC	66	struct dwmci_exynos_priv_data *priv = host->priv;
5dab81ce JC	67
18ab6755 JC	68	if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
	69	dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
	70	dwmci_writel(host, EMMCP_SEND0, 0);
	71	dwmci_writel(host, EMMCP_CTRL0,
	72	MPSCTRL_SECURE_READ_BIT \|
	73	MPSCTRL_SECURE_WRITE_BIT \|
	74	MPSCTRL_NON_SECURE_READ_BIT \|
	75	MPSCTRL_NON_SECURE_WRITE_BIT \| MPSCTRL_VALID);
	76	}
3a33bb18	77
5dab81ce JC	78	/* Set to timing value at initial time */
5dab81ce JC	79	if (priv->sdr_timing)
3a33bb18	80	exynos_dwmci_clksel(host);
18ab6755 JC	81	}
18ab6755 JC	82
959198f7	83	static int exynos_dwmci_core_init(struct dwmci_host *host, int index)
d0ebbb8d	84	{
a082a2dd A	85	unsigned int div;
a082a2dd A	86	unsigned long freq, sclk;
5dab81ce	87	struct dwmci_exynos_priv_data *priv = host->priv;
959198f7 JC	88
	89	if (host->bus_hz)
	90	freq = host->bus_hz;
	91	else
	92	freq = DWMMC_MAX_FREQ;
	93
a082a2dd	94	/* request mmc clock vlaue of 52MHz. */
a082a2dd A	95	sclk = get_mmc_clk(index);
	96	div = DIV_ROUND_UP(sclk, freq);
	97	/* set the clock divisor for mmc */
	98	set_mmc_clk(index, div);
d0ebbb8d	99
a082a2dd	100	host->name = "EXYNOS DWMMC";
6f0b7caa RS	101	#ifdef CONFIG_EXYNOS5420
	102	host->quirks = DWMCI_QUIRK_DISABLE_SMU;
	103	#endif
18ab6755	104	host->board_init = exynos_dwmci_board_init;
a082a2dd	105
5dab81ce	106	if (!priv->sdr_timing) {
959198f7	107	if (index == 0)
5dab81ce	108	priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL;
959198f7	109	else if (index == 2)
5dab81ce	110	priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL;
a082a2dd A	111	}
a082a2dd A	112
e09bd853	113	host->caps = MMC_MODE_DDR_52MHz;
d0ebbb8d JC	114	host->clksel = exynos_dwmci_clksel;
d0ebbb8d JC	115	host->dev_index = index;
b44fe83a	116	host->get_mmc_clk = exynos_dwmci_get_clk;
a082a2dd A	117	/* Add the mmc channel to be registered with mmc core */
a082a2dd A	118	if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
dfcb683a	119	printf("DWMMC%d registration failed\n", index);
a082a2dd A	120	return -1;
	121	}
	122	return 0;
	123	}
	124
959198f7 JC	125	/*
	126	* This function adds the mmc channel to be registered with mmc core.
	127	* index - mmc channel number.
	128	* regbase - register base address of mmc channel specified in 'index'.
	129	* bus_width - operating bus width of mmc channel specified in 'index'.
	130	* clksel - value to be written into CLKSEL register in case of FDT.
	131	* NULL in case od non-FDT.
	132	*/
	133	int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
	134	{
	135	struct dwmci_host *host = NULL;
5dab81ce	136	struct dwmci_exynos_priv_data *priv;
959198f7 JC	137
	138	host = malloc(sizeof(struct dwmci_host));
	139	if (!host) {
	140	error("dwmci_host malloc fail!\n");
	141	return -ENOMEM;
	142	}
	143
5dab81ce JC	144	priv = malloc(sizeof(struct dwmci_exynos_priv_data));
	145	if (!priv) {
	146	error("dwmci_exynos_priv_data malloc fail!\n");
	147	return -ENOMEM;
	148	}
	149
959198f7 JC	150	host->ioaddr = (void *)regbase;
	151	host->buswidth = bus_width;
	152
	153	if (clksel)
5dab81ce JC	154	priv->sdr_timing = clksel;
	155
	156	host->priv = priv;
959198f7 JC	157
	158	return exynos_dwmci_core_init(host, index);
	159	}
	160
0f925822	161	#if CONFIG_IS_ENABLED(OF_CONTROL)
959198f7 JC	162	static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM];
	163
	164	static int do_dwmci_init(struct dwmci_host *host)
a082a2dd	165	{
959198f7	166	int index, flag, err;
a082a2dd	167
959198f7	168	index = host->dev_index;
a082a2dd	169
959198f7 JC	170	flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
	171	err = exynos_pinmux_config(host->dev_id, flag);
	172	if (err) {
dfcb683a	173	printf("DWMMC%d not configure\n", index);
959198f7 JC	174	return err;
959198f7 JC	175	}
a082a2dd	176
959198f7 JC	177	return exynos_dwmci_core_init(host, index);
959198f7 JC	178	}
d0ebbb8d	179
959198f7 JC	180	static int exynos_dwmci_get_config(const void *blob, int node,
	181	struct dwmci_host *host)
	182	{
	183	int err = 0;
5dab81ce JC	184	u32 base, timing[3];
	185	struct dwmci_exynos_priv_data *priv;
	186
	187	priv = malloc(sizeof(struct dwmci_exynos_priv_data));
	188	if (!priv) {
	189	error("dwmci_exynos_priv_data malloc fail!\n");
	190	return -ENOMEM;
	191	}
d0ebbb8d	192
959198f7 JC	193	/* Extract device id for each mmc channel */
959198f7 JC	194	host->dev_id = pinmux_decode_periph_id(blob, node);
a082a2dd	195
dfcb683a JC	196	host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
	197	if (host->dev_index == host->dev_id)
	198	host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
	199
959198f7 JC	200	/* Get the bus width from the device node */
	201	host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
	202	if (host->buswidth <= 0) {
dfcb683a	203	printf("DWMMC%d: Can't get bus-width\n", host->dev_index);
959198f7 JC	204	return -EINVAL;
959198f7 JC	205	}
a082a2dd	206
959198f7 JC	207	/* Set the base address from the device node */
	208	base = fdtdec_get_addr(blob, node, "reg");
	209	if (!base) {
dfcb683a	210	printf("DWMMC%d: Can't get base address\n", host->dev_index);
959198f7 JC	211	return -EINVAL;
	212	}
	213	host->ioaddr = (void *)base;
	214
	215	/* Extract the timing info from the node */
	216	err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3);
	217	if (err) {
dfcb683a JC	218	printf("DWMMC%d: Can't get sdr-timings for devider\n",
dfcb683a JC	219	host->dev_index);
959198f7 JC	220	return -EINVAL;
	221	}
	222
5dab81ce	223	priv->sdr_timing = (DWMCI_SET_SAMPLE_CLK(timing[0]) \|
959198f7 JC	224	DWMCI_SET_DRV_CLK(timing[1]) \|
959198f7 JC	225	DWMCI_SET_DIV_RATIO(timing[2]));
5dab81ce JC	226
	227	/* sdr_timing didn't assigned anything, use the default value */
	228	if (!priv->sdr_timing) {
	229	if (host->dev_index == 0)
	230	priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL;
	231	else if (host->dev_index == 2)
	232	priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL;
	233	}
959198f7 JC	234
	235	host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0);
	236	host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0);
	237	host->div = fdtdec_get_int(blob, node, "div", 0);
	238
5dab81ce JC	239	host->priv = priv;
5dab81ce JC	240
959198f7 JC	241	return 0;
	242	}
	243
	244	static int exynos_dwmci_process_node(const void *blob,
	245	int node_list[], int count)
	246	{
	247	struct dwmci_host *host;
	248	int i, node, err;
	249
	250	for (i = 0; i < count; i++) {
	251	node = node_list[i];
	252	if (node <= 0)
	253	continue;
	254	host = &dwmci_host[i];
	255	err = exynos_dwmci_get_config(blob, node, host);
a082a2dd	256	if (err) {
dfcb683a	257	printf("%s: failed to decode dev %d\n", __func__, i);
959198f7	258	return err;
a082a2dd A	259	}
a082a2dd A	260
959198f7	261	do_dwmci_init(host);
a082a2dd	262	}
d0ebbb8d JC	263	return 0;
d0ebbb8d JC	264	}
959198f7 JC	265
	266	int exynos_dwmmc_init(const void *blob)
	267	{
	268	int compat_id;
	269	int node_list[DWMMC_MAX_CH_NUM];
64029f7a	270	int boot_dev_node;
959198f7 JC	271	int err = 0, count;
	272
	273	compat_id = COMPAT_SAMSUNG_EXYNOS_DWMMC;
	274
	275	count = fdtdec_find_aliases_for_id(blob, "mmc",
	276	compat_id, node_list, DWMMC_MAX_CH_NUM);
64029f7a PM	277
	278	/* For DWMMC always set boot device as mmc 0 */
	279	if (count >= 3 && get_boot_mode() == BOOT_MODE_SD) {
	280	boot_dev_node = node_list[2];
	281	node_list[2] = node_list[0];
	282	node_list[0] = boot_dev_node;
	283	}
	284
959198f7 JC	285	err = exynos_dwmci_process_node(blob, node_list, count);
	286
	287	return err;
	288	}
a082a2dd	289	#endif