[J-u-boot.git] / drivers / video / mali_dp.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2016-2018 ARM Ltd.
 * Author: Liviu Dudau <[email protected]>
 *
 */
#define DEBUG
#include <common.h>
#include <malloc.h>
#include <video.h>
#include <dm.h>
#ifdef CONFIG_DISPLAY
#include <display.h>
#endif
#include <fdtdec.h>
#include <asm/io.h>
#include <os.h>
#include <fdt_support.h>
#include <clk.h>
#include <dm/device_compat.h>
#include <linux/delay.h>
#include <linux/sizes.h>

#define MALIDP_CORE_ID		0x0018
#define MALIDP_REG_BG_COLOR	0x0044
#define MALIDP_LAYER_LV1	0x0100
#define MALIDP_DC_STATUS	0xc000
#define MALIDP_DC_CONTROL	0xc010
#define MALIDP_DC_CFG_VALID	0xc014

/* offsets inside the modesetting register block */
#define MALIDP_H_INTERVALS	0x0000
#define MALIDP_V_INTERVALS	0x0004
#define MALIDP_SYNC_CONTROL	0x0008
#define MALIDP_HV_ACTIVESIZE	0x000c
#define MALIDP_OUTPUT_DEPTH	0x001c

/* offsets inside the layer register block */
#define MALIDP_LAYER_FORMAT	0x0000
#define MALIDP_LAYER_CONTROL	0x0004
#define MALIDP_LAYER_IN_SIZE	0x000c
#define MALIDP_LAYER_CMP_SIZE	0x0010
#define MALIDP_LAYER_STRIDE	0x0018
#define MALIDP_LAYER_PTR_LOW	0x0024
#define MALIDP_LAYER_PTR_HIGH	0x0028

/* offsets inside the IRQ control blocks */
#define MALIDP_REG_MASKIRQ	0x0008
#define MALIDP_REG_CLEARIRQ	0x000c

#define M1BITS	0x0001
#define M2BITS	0x0003
#define M4BITS	0x000f
#define M8BITS	0x00ff
#define M10BITS	0x03ff
#define M12BITS	0x0fff
#define M13BITS	0x1fff
#define M16BITS	0xffff
#define M17BITS	0x1ffff

#define MALIDP_H_FRONTPORCH(x)	(((x) & M12BITS) << 0)
#define MALIDP_H_BACKPORCH(x)	(((x) & M10BITS) << 16)
#define MALIDP_V_FRONTPORCH(x)	(((x) & M12BITS) << 0)
#define MALIDP_V_BACKPORCH(x)	(((x) & M8BITS) << 16)
#define MALIDP_H_SYNCWIDTH(x)	(((x) & M10BITS) << 0)
#define MALIDP_V_SYNCWIDTH(x)	(((x) & M8BITS) << 16)
#define MALIDP_H_ACTIVE(x)	(((x) & M13BITS) << 0)
#define MALIDP_V_ACTIVE(x)	(((x) & M13BITS) << 16)

#define MALIDP_CMP_V_SIZE(x)	(((x) & M13BITS) << 16)
#define MALIDP_CMP_H_SIZE(x)	(((x) & M13BITS) << 0)

#define MALIDP_IN_V_SIZE(x)	(((x) & M13BITS) << 16)
#define MALIDP_IN_H_SIZE(x)	(((x) & M13BITS) << 0)

#define MALIDP_DC_CM_CONTROL(x)	((x) & M1BITS) << 16, 1 << 16
#define MALIDP_DC_STATUS_GET_CM(reg) (((reg) >> 16) & M1BITS)

#define MALIDP_FORMAT_ARGB8888	0x08
#define MALIDP_DEFAULT_BG_R 0x0
#define MALIDP_DEFAULT_BG_G 0x0
#define MALIDP_DEFAULT_BG_B 0x0

#define MALIDP_PRODUCT_ID(core_id)	((u32)(core_id) >> 16)

#define MALIDP500	0x500

DECLARE_GLOBAL_DATA_PTR;

struct malidp_priv {
	phys_addr_t base_addr;
	phys_addr_t dc_status_addr;
	phys_addr_t dc_control_addr;
	phys_addr_t cval_addr;
	struct udevice *display;	/* display device attached */
	struct clk aclk;
	struct clk pxlclk;
	u16 modeset_regs_offset;
	u8 config_bit_shift;
	u8 clear_irq;			/* offset for IRQ clear register */
};

static const struct video_ops malidp_ops = {
};

static int malidp_get_hwid(phys_addr_t base_addr)
{
	int hwid;

	/*
	 * reading from the old CORE_ID offset will always
	 * return 0x5000000 on DP500
	 */
	hwid = readl(base_addr + MALIDP_CORE_ID);
	if (MALIDP_PRODUCT_ID(hwid) == MALIDP500)
		return hwid;
	/* otherwise try the other gen CORE_ID offset */
	hwid = readl(base_addr + MALIDP_DC_STATUS + MALIDP_CORE_ID);

	return hwid;
}

/*
 * wait for config mode bit setup to be acted upon by the hardware
 */
static int malidp_wait_configdone(struct malidp_priv *malidp)
{
	u32 status, tries = 300;

	while (tries--) {
		status = readl(malidp->dc_status_addr);
		if ((status >> malidp->config_bit_shift) & 1)
			break;
		udelay(500);
	}

	if (!tries)
		return -ETIMEDOUT;

	return 0;
}

/*
 * signal the hardware to enter configuration mode
 */
static int malidp_enter_config(struct malidp_priv *malidp)
{
	setbits_le32(malidp->dc_control_addr, 1 << malidp->config_bit_shift);
	return malidp_wait_configdone(malidp);
}

/*
 * signal the hardware to exit configuration mode
 */
static int malidp_leave_config(struct malidp_priv *malidp)
{
	clrbits_le32(malidp->dc_control_addr, 1 << malidp->config_bit_shift);
	return malidp_wait_configdone(malidp);
}

static void malidp_setup_timings(struct malidp_priv *malidp,
				 struct display_timing *timings)
{
	u32 val = MALIDP_H_SYNCWIDTH(timings->hsync_len.typ) |
		  MALIDP_V_SYNCWIDTH(timings->vsync_len.typ);
	writel(val, malidp->base_addr + malidp->modeset_regs_offset +
	       MALIDP_SYNC_CONTROL);
	val = MALIDP_H_BACKPORCH(timings->hback_porch.typ) |
		MALIDP_H_FRONTPORCH(timings->hfront_porch.typ);
	writel(val, malidp->base_addr + malidp->modeset_regs_offset +
	       MALIDP_H_INTERVALS);
	val = MALIDP_V_BACKPORCH(timings->vback_porch.typ) |
		MALIDP_V_FRONTPORCH(timings->vfront_porch.typ);
	writel(val, malidp->base_addr + malidp->modeset_regs_offset +
	       MALIDP_V_INTERVALS);
	val = MALIDP_H_ACTIVE(timings->hactive.typ) |
		MALIDP_V_ACTIVE(timings->vactive.typ);
	writel(val, malidp->base_addr + malidp->modeset_regs_offset +
	       MALIDP_HV_ACTIVESIZE);
	/* default output bit-depth per colour is 8 bits */
	writel(0x080808, malidp->base_addr + malidp->modeset_regs_offset +
	       MALIDP_OUTPUT_DEPTH);
}

static int malidp_setup_mode(struct malidp_priv *malidp,
			     struct display_timing *timings)
{
	int err;

	if (clk_set_rate(&malidp->pxlclk, timings->pixelclock.typ) == 0)
		return -EIO;

	malidp_setup_timings(malidp, timings);

	err = display_enable(malidp->display, 8, timings);
	if (err)
		printf("display_enable failed with %d\n", err);

	return err;
}

static void malidp_setup_layer(struct malidp_priv *malidp,
			       struct display_timing *timings,
			       u32 layer_offset, phys_addr_t fb_addr)
{
	u32 val;

	/* setup the base layer's pixel format to A8R8G8B8 */
	writel(MALIDP_FORMAT_ARGB8888, malidp->base_addr + layer_offset +
	       MALIDP_LAYER_FORMAT);
	/* setup layer composition size */
	val = MALIDP_CMP_V_SIZE(timings->vactive.typ) |
		MALIDP_CMP_H_SIZE(timings->hactive.typ);
	writel(val, malidp->base_addr + layer_offset +
	       MALIDP_LAYER_CMP_SIZE);
	/* setup layer input size */
	val = MALIDP_IN_V_SIZE(timings->vactive.typ) |
		MALIDP_IN_H_SIZE(timings->hactive.typ);
	writel(val, malidp->base_addr + layer_offset + MALIDP_LAYER_IN_SIZE);
	/* setup layer stride in bytes */
	writel(timings->hactive.typ << 2, malidp->base_addr + layer_offset +
	       MALIDP_LAYER_STRIDE);
	/* set framebuffer address */
	writel(lower_32_bits(fb_addr), malidp->base_addr + layer_offset +
	       MALIDP_LAYER_PTR_LOW);
	writel(upper_32_bits(fb_addr), malidp->base_addr + layer_offset +
	       MALIDP_LAYER_PTR_HIGH);
	/* enable layer */
	setbits_le32(malidp->base_addr + layer_offset +
		     MALIDP_LAYER_CONTROL, 1);
}

static void malidp_set_configvalid(struct malidp_priv *malidp)
{
	setbits_le32(malidp->cval_addr, 1);
}

static int malidp_update_timings_from_edid(struct udevice *dev,
					   struct display_timing *timings)
{
#ifdef CONFIG_DISPLAY
	struct malidp_priv *priv = dev_get_priv(dev);
	struct udevice *disp_dev;
	int err;

	err = uclass_first_device(UCLASS_DISPLAY, &disp_dev);
	if (err)
		return err;

	priv->display = disp_dev;

	err = display_read_timing(disp_dev, timings);
	if (err)
		return err;

#endif
	return 0;
}

static int malidp_probe(struct udevice *dev)
{
	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
	struct video_uc_platdata *uc_plat = dev_get_uclass_plat(dev);
	ofnode framebuffer = ofnode_find_subnode(dev_ofnode(dev), "framebuffer");
	struct malidp_priv *priv = dev_get_priv(dev);
	struct display_timing timings;
	phys_addr_t fb_base, fb_size;
	const char *format;
	u32 value;
	int err;

	if (!ofnode_valid(framebuffer))
		return -EINVAL;

	err = clk_get_by_name(dev, "pxlclk", &priv->pxlclk);
	if (err) {
		dev_err(dev, "failed to get pixel clock\n");
		return err;
	}
	err = clk_get_by_name(dev, "aclk", &priv->aclk);
	if (err) {
		dev_err(dev, "failed to get AXI clock\n");
		goto fail_aclk;
	}

	err = ofnode_decode_display_timing(dev_ofnode(dev), 1, &timings);
	if (err) {
		dev_err(dev, "failed to get any display timings\n");
		goto fail_timings;
	}

	err = malidp_update_timings_from_edid(dev, &timings);
	if (err) {
		printf("malidp_update_timings_from_edid failed: %d\n", err);
		goto fail_timings;
	}

	fb_base = ofnode_get_addr_size(framebuffer, "reg", &fb_size);
	if (fb_base != FDT_ADDR_T_NONE) {
		uc_plat->base = fb_base;
		uc_plat->size = fb_size;
	} else {
		printf("cannot get address size for framebuffer\n");
	}

	err = ofnode_read_u32(framebuffer, "width", &value);
	if (err)
		goto fail_timings;
	uc_priv->xsize = (ushort)value;

	err = ofnode_read_u32(framebuffer, "height", &value);
	if (err)
		goto fail_timings;
	uc_priv->ysize = (ushort)value;

	format = ofnode_read_string(framebuffer, "format");
	if (!format) {
		err = -EINVAL;
		goto fail_timings;
	} else if (!strncmp(format, "a8r8g8b8", 8)) {
		uc_priv->bpix = VIDEO_BPP32;
	}

	uc_priv->rot = 0;
	priv->base_addr = (phys_addr_t)dev_read_addr(dev);

	clk_enable(&priv->pxlclk);
	clk_enable(&priv->aclk);

	value = malidp_get_hwid(priv->base_addr);
	printf("Display: Arm Mali DP%3x r%dp%d\n", MALIDP_PRODUCT_ID(value),
	       (value >> 12) & 0xf, (value >> 8) & 0xf);

	if (MALIDP_PRODUCT_ID(value) == MALIDP500) {
		/* DP500 is special */
		priv->modeset_regs_offset = 0x28;
		priv->dc_status_addr = priv->base_addr;
		priv->dc_control_addr = priv->base_addr + 0xc;
		priv->cval_addr = priv->base_addr + 0xf00;
		priv->config_bit_shift = 17;
		priv->clear_irq = 0;
	} else {
		priv->modeset_regs_offset = 0x30;
		priv->dc_status_addr = priv->base_addr + MALIDP_DC_STATUS;
		priv->dc_control_addr = priv->base_addr + MALIDP_DC_CONTROL;
		priv->cval_addr = priv->base_addr + MALIDP_DC_CFG_VALID;
		priv->config_bit_shift = 16;
		priv->clear_irq = MALIDP_REG_CLEARIRQ;
	}

	/* enter config mode */
	err  = malidp_enter_config(priv);
	if (err)
		return err;

	/* disable interrupts */
	writel(0, priv->dc_status_addr + MALIDP_REG_MASKIRQ);
	writel(0xffffffff, priv->dc_status_addr + priv->clear_irq);

	err = malidp_setup_mode(priv, &timings);
	if (err)
		goto fail_timings;

	malidp_setup_layer(priv, &timings, MALIDP_LAYER_LV1,
			   (phys_addr_t)uc_plat->base);

	err = malidp_leave_config(priv);
	if (err)
		goto fail_timings;

	malidp_set_configvalid(priv);

	return 0;

fail_timings:
	clk_free(&priv->aclk);
fail_aclk:
	clk_free(&priv->pxlclk);

	return err;
}

static int malidp_bind(struct udevice *dev)
{
	struct video_uc_platdata *uc_plat = dev_get_uclass_plat(dev);

	/* choose max possible size: 2K x 2K, XRGB888 framebuffer */
	uc_plat->size = 4 * 2048 * 2048;

	return 0;
}

static const struct udevice_id malidp_ids[] = {
	{ .compatible = "arm,mali-dp500" },
	{ .compatible = "arm,mali-dp550" },
	{ .compatible = "arm,mali-dp650" },
	{ }
};

U_BOOT_DRIVER(mali_dp) = {
	.name		= "mali_dp",
	.id		= UCLASS_VIDEO,
	.of_match	= malidp_ids,
	.bind		= malidp_bind,
	.probe		= malidp_probe,
	.priv_auto	= sizeof(struct malidp_priv),
	.ops		= &malidp_ops,
};
Commit	Line	Data
c1a65a8c LD	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* (C) Copyright 2016-2018 ARM Ltd.
	4	* Author: Liviu Dudau <[email protected]>
	5	*
	6	*/
	7	#define DEBUG
	8	#include <common.h>
336d4615	9	#include <malloc.h>
c1a65a8c LD	10	#include <video.h>
	11	#include <dm.h>
	12	#ifdef CONFIG_DISPLAY
	13	#include <display.h>
	14	#endif
	15	#include <fdtdec.h>
	16	#include <asm/io.h>
	17	#include <os.h>
	18	#include <fdt_support.h>
	19	#include <clk.h>
336d4615	20	#include <dm/device_compat.h>
c05ed00a	21	#include <linux/delay.h>
c1a65a8c LD	22	#include <linux/sizes.h>
	23
	24	#define MALIDP_CORE_ID 0x0018
	25	#define MALIDP_REG_BG_COLOR 0x0044
	26	#define MALIDP_LAYER_LV1 0x0100
	27	#define MALIDP_DC_STATUS 0xc000
	28	#define MALIDP_DC_CONTROL 0xc010
	29	#define MALIDP_DC_CFG_VALID 0xc014
	30
	31	/* offsets inside the modesetting register block */
	32	#define MALIDP_H_INTERVALS 0x0000
	33	#define MALIDP_V_INTERVALS 0x0004
	34	#define MALIDP_SYNC_CONTROL 0x0008
	35	#define MALIDP_HV_ACTIVESIZE 0x000c
	36	#define MALIDP_OUTPUT_DEPTH 0x001c
	37
	38	/* offsets inside the layer register block */
	39	#define MALIDP_LAYER_FORMAT 0x0000
	40	#define MALIDP_LAYER_CONTROL 0x0004
	41	#define MALIDP_LAYER_IN_SIZE 0x000c
	42	#define MALIDP_LAYER_CMP_SIZE 0x0010
	43	#define MALIDP_LAYER_STRIDE 0x0018
	44	#define MALIDP_LAYER_PTR_LOW 0x0024
	45	#define MALIDP_LAYER_PTR_HIGH 0x0028
	46
	47	/* offsets inside the IRQ control blocks */
	48	#define MALIDP_REG_MASKIRQ 0x0008
	49	#define MALIDP_REG_CLEARIRQ 0x000c
	50
	51	#define M1BITS 0x0001
	52	#define M2BITS 0x0003
	53	#define M4BITS 0x000f
	54	#define M8BITS 0x00ff
	55	#define M10BITS 0x03ff
	56	#define M12BITS 0x0fff
	57	#define M13BITS 0x1fff
	58	#define M16BITS 0xffff
	59	#define M17BITS 0x1ffff
	60
	61	#define MALIDP_H_FRONTPORCH(x) (((x) & M12BITS) << 0)
	62	#define MALIDP_H_BACKPORCH(x) (((x) & M10BITS) << 16)
	63	#define MALIDP_V_FRONTPORCH(x) (((x) & M12BITS) << 0)
	64	#define MALIDP_V_BACKPORCH(x) (((x) & M8BITS) << 16)
	65	#define MALIDP_H_SYNCWIDTH(x) (((x) & M10BITS) << 0)
	66	#define MALIDP_V_SYNCWIDTH(x) (((x) & M8BITS) << 16)
	67	#define MALIDP_H_ACTIVE(x) (((x) & M13BITS) << 0)
	68	#define MALIDP_V_ACTIVE(x) (((x) & M13BITS) << 16)
	69
	70	#define MALIDP_CMP_V_SIZE(x) (((x) & M13BITS) << 16)
	71	#define MALIDP_CMP_H_SIZE(x) (((x) & M13BITS) << 0)
	72
	73	#define MALIDP_IN_V_SIZE(x) (((x) & M13BITS) << 16)
	74	#define MALIDP_IN_H_SIZE(x) (((x) & M13BITS) << 0)
	75
	76	#define MALIDP_DC_CM_CONTROL(x) ((x) & M1BITS) << 16, 1 << 16
	77	#define MALIDP_DC_STATUS_GET_CM(reg) (((reg) >> 16) & M1BITS)
	78
	79	#define MALIDP_FORMAT_ARGB8888 0x08
	80	#define MALIDP_DEFAULT_BG_R 0x0
	81	#define MALIDP_DEFAULT_BG_G 0x0
	82	#define MALIDP_DEFAULT_BG_B 0x0
	83
	84	#define MALIDP_PRODUCT_ID(core_id) ((u32)(core_id) >> 16)
	85
86	#define MALIDP500 0x500
87
88	DECLARE_GLOBAL_DATA_PTR;
89
90	struct malidp_priv {
91	phys_addr_t base_addr;
92	phys_addr_t dc_status_addr;
93	phys_addr_t dc_control_addr;
94	phys_addr_t cval_addr;
95	struct udevice display; / display device attached */
96	struct clk aclk;
97	struct clk pxlclk;
98	u16 modeset_regs_offset;
99	u8 config_bit_shift;
100	u8 clear_irq; /* offset for IRQ clear register */
101	};
102
103	static const struct video_ops malidp_ops = {
104	};
105
106	static int malidp_get_hwid(phys_addr_t base_addr)
107	{
108	int hwid;
109
110	/*
111	* reading from the old CORE_ID offset will always
112	* return 0x5000000 on DP500
113	*/
114	hwid = readl(base_addr + MALIDP_CORE_ID);
115	if (MALIDP_PRODUCT_ID(hwid) == MALIDP500)
116	return hwid;
117	/* otherwise try the other gen CORE_ID offset */
118	hwid = readl(base_addr + MALIDP_DC_STATUS + MALIDP_CORE_ID);
119
120	return hwid;
121	}
122
123	/*
124	* wait for config mode bit setup to be acted upon by the hardware
125	*/
126	static int malidp_wait_configdone(struct malidp_priv *malidp)
127	{
128	u32 status, tries = 300;
129
130	while (tries--) {
131	status = readl(malidp->dc_status_addr);
132	if ((status >> malidp->config_bit_shift) & 1)
133	break;
134	udelay(500);
135	}
136
137	if (!tries)
138	return -ETIMEDOUT;
139
140	return 0;
141	}
142
143	/*
144	* signal the hardware to enter configuration mode
145	*/
146	static int malidp_enter_config(struct malidp_priv *malidp)
147	{
148	setbits_le32(malidp->dc_control_addr, 1 << malidp->config_bit_shift);
149	return malidp_wait_configdone(malidp);
150	}
151
152	/*
153	* signal the hardware to exit configuration mode
154	*/
155	static int malidp_leave_config(struct malidp_priv *malidp)
156	{
157	clrbits_le32(malidp->dc_control_addr, 1 << malidp->config_bit_shift);
158	return malidp_wait_configdone(malidp);
159	}
160
161	static void malidp_setup_timings(struct malidp_priv *malidp,
162	struct display_timing *timings)
163	{
164	u32 val = MALIDP_H_SYNCWIDTH(timings->hsync_len.typ) \|
165	MALIDP_V_SYNCWIDTH(timings->vsync_len.typ);
166	writel(val, malidp->base_addr + malidp->modeset_regs_offset +
167	MALIDP_SYNC_CONTROL);
168	val = MALIDP_H_BACKPORCH(timings->hback_porch.typ) \|
169	MALIDP_H_FRONTPORCH(timings->hfront_porch.typ);
170	writel(val, malidp->base_addr + malidp->modeset_regs_offset +
171	MALIDP_H_INTERVALS);
172	val = MALIDP_V_BACKPORCH(timings->vback_porch.typ) \|
173	MALIDP_V_FRONTPORCH(timings->vfront_porch.typ);
174	writel(val, malidp->base_addr + malidp->modeset_regs_offset +
175	MALIDP_V_INTERVALS);
176	val = MALIDP_H_ACTIVE(timings->hactive.typ) \|
177	MALIDP_V_ACTIVE(timings->vactive.typ);
178	writel(val, malidp->base_addr + malidp->modeset_regs_offset +
179	MALIDP_HV_ACTIVESIZE);
180	/* default output bit-depth per colour is 8 bits */
181	writel(0x080808, malidp->base_addr + malidp->modeset_regs_offset +
182	MALIDP_OUTPUT_DEPTH);
183	}
184
185	static int malidp_setup_mode(struct malidp_priv *malidp,
186	struct display_timing *timings)
187	{
188	int err;
189
190	if (clk_set_rate(&malidp->pxlclk, timings->pixelclock.typ) == 0)
191	return -EIO;
192
193	malidp_setup_timings(malidp, timings);
194
195	err = display_enable(malidp->display, 8, timings);
196	if (err)
197	printf("display_enable failed with %d\n", err);
198
199	return err;
200	}
201
202	static void malidp_setup_layer(struct malidp_priv *malidp,
203	struct display_timing *timings,
204	u32 layer_offset, phys_addr_t fb_addr)
205	{
206	u32 val;
207
208	/* setup the base layer's pixel format to A8R8G8B8 */
209	writel(MALIDP_FORMAT_ARGB8888, malidp->base_addr + layer_offset +
210	MALIDP_LAYER_FORMAT);
211	/* setup layer composition size */
212	val = MALIDP_CMP_V_SIZE(timings->vactive.typ) \|
213	MALIDP_CMP_H_SIZE(timings->hactive.typ);
214	writel(val, malidp->base_addr + layer_offset +
215	MALIDP_LAYER_CMP_SIZE);
216	/* setup layer input size */
217	val = MALIDP_IN_V_SIZE(timings->vactive.typ) \|
218	MALIDP_IN_H_SIZE(timings->hactive.typ);
219	writel(val, malidp->base_addr + layer_offset + MALIDP_LAYER_IN_SIZE);
220	/* setup layer stride in bytes */
221	writel(timings->hactive.typ << 2, malidp->base_addr + layer_offset +
222	MALIDP_LAYER_STRIDE);
223	/* set framebuffer address */
224	writel(lower_32_bits(fb_addr), malidp->base_addr + layer_offset +
225	MALIDP_LAYER_PTR_LOW);
226	writel(upper_32_bits(fb_addr), malidp->base_addr + layer_offset +
227	MALIDP_LAYER_PTR_HIGH);
228	/* enable layer */
229	setbits_le32(malidp->base_addr + layer_offset +
230	MALIDP_LAYER_CONTROL, 1);
231	}
232
233	static void malidp_set_configvalid(struct malidp_priv *malidp)
234	{
235	setbits_le32(malidp->cval_addr, 1);
236	}
237
238	static int malidp_update_timings_from_edid(struct udevice *dev,
239	struct display_timing *timings)
240	{
241	#ifdef CONFIG_DISPLAY
242	struct malidp_priv *priv = dev_get_priv(dev);
243	struct udevice *disp_dev;
244	int err;
245
246	err = uclass_first_device(UCLASS_DISPLAY, &disp_dev);
247	if (err)
248	return err;
249
250	priv->display = disp_dev;
251
252	err = display_read_timing(disp_dev, timings);
253	if (err)
254	return err;
255
256	#endif
257	return 0;
258	}
259
260	static int malidp_probe(struct udevice *dev)
261	{
262	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
caa4daa2	263	struct video_uc_platdata *uc_plat = dev_get_uclass_plat(dev);
c1a65a8c LD	264	ofnode framebuffer = ofnode_find_subnode(dev_ofnode(dev), "framebuffer");
	265	struct malidp_priv *priv = dev_get_priv(dev);
	266	struct display_timing timings;
	267	phys_addr_t fb_base, fb_size;
	268	const char *format;
	269	u32 value;
	270	int err;
	271
	272	if (!ofnode_valid(framebuffer))
	273	return -EINVAL;
	274
	275	err = clk_get_by_name(dev, "pxlclk", &priv->pxlclk);
	276	if (err) {
	277	dev_err(dev, "failed to get pixel clock\n");
	278	return err;
	279	}
	280	err = clk_get_by_name(dev, "aclk", &priv->aclk);
	281	if (err) {
	282	dev_err(dev, "failed to get AXI clock\n");
	283	goto fail_aclk;
	284	}
	285
	286	err = ofnode_decode_display_timing(dev_ofnode(dev), 1, &timings);
	287	if (err) {
	288	dev_err(dev, "failed to get any display timings\n");
	289	goto fail_timings;
	290	}
	291
	292	err = malidp_update_timings_from_edid(dev, &timings);
	293	if (err) {
	294	printf("malidp_update_timings_from_edid failed: %d\n", err);
	295	goto fail_timings;
	296	}
	297
	298	fb_base = ofnode_get_addr_size(framebuffer, "reg", &fb_size);
	299	if (fb_base != FDT_ADDR_T_NONE) {
	300	uc_plat->base = fb_base;
	301	uc_plat->size = fb_size;
	302	} else {
	303	printf("cannot get address size for framebuffer\n");
	304	}
	305
	306	err = ofnode_read_u32(framebuffer, "width", &value);
	307	if (err)
	308	goto fail_timings;
	309	uc_priv->xsize = (ushort)value;
	310
	311	err = ofnode_read_u32(framebuffer, "height", &value);
	312	if (err)
	313	goto fail_timings;
	314	uc_priv->ysize = (ushort)value;
	315
	316	format = ofnode_read_string(framebuffer, "format");
	317	if (!format) {
	318	err = -EINVAL;
	319	goto fail_timings;
	320	} else if (!strncmp(format, "a8r8g8b8", 8)) {
	321	uc_priv->bpix = VIDEO_BPP32;
	322	}
	323
	324	uc_priv->rot = 0;
	325	priv->base_addr = (phys_addr_t)dev_read_addr(dev);
	326
	327	clk_enable(&priv->pxlclk);
328	clk_enable(&priv->aclk);
329
330	value = malidp_get_hwid(priv->base_addr);
331	printf("Display: Arm Mali DP%3x r%dp%d\n", MALIDP_PRODUCT_ID(value),
332	(value >> 12) & 0xf, (value >> 8) & 0xf);
333
334	if (MALIDP_PRODUCT_ID(value) == MALIDP500) {
335	/* DP500 is special */
336	priv->modeset_regs_offset = 0x28;
337	priv->dc_status_addr = priv->base_addr;
338	priv->dc_control_addr = priv->base_addr + 0xc;
339	priv->cval_addr = priv->base_addr + 0xf00;
340	priv->config_bit_shift = 17;
341	priv->clear_irq = 0;
342	} else {
343	priv->modeset_regs_offset = 0x30;
344	priv->dc_status_addr = priv->base_addr + MALIDP_DC_STATUS;
345	priv->dc_control_addr = priv->base_addr + MALIDP_DC_CONTROL;
346	priv->cval_addr = priv->base_addr + MALIDP_DC_CFG_VALID;
347	priv->config_bit_shift = 16;
348	priv->clear_irq = MALIDP_REG_CLEARIRQ;
349	}
350
351	/* enter config mode */
352	err = malidp_enter_config(priv);
353	if (err)
354	return err;
355
356	/* disable interrupts */
357	writel(0, priv->dc_status_addr + MALIDP_REG_MASKIRQ);
358	writel(0xffffffff, priv->dc_status_addr + priv->clear_irq);
359
360	err = malidp_setup_mode(priv, &timings);
361	if (err)
362	goto fail_timings;
363
364	malidp_setup_layer(priv, &timings, MALIDP_LAYER_LV1,
365	(phys_addr_t)uc_plat->base);
366
367	err = malidp_leave_config(priv);
368	if (err)
369	goto fail_timings;
370
371	malidp_set_configvalid(priv);
372
373	return 0;
374
375	fail_timings:
376	clk_free(&priv->aclk);
377	fail_aclk:
378	clk_free(&priv->pxlclk);
379
380	return err;
381	}
382
383	static int malidp_bind(struct udevice *dev)
384	{
caa4daa2	385	struct video_uc_platdata *uc_plat = dev_get_uclass_plat(dev);
c1a65a8c LD	386
	387	/* choose max possible size: 2K x 2K, XRGB888 framebuffer */
	388	uc_plat->size = 4 * 2048 * 2048;
	389
	390	return 0;
	391	}
	392
	393	static const struct udevice_id malidp_ids[] = {
	394	{ .compatible = "arm,mali-dp500" },
	395	{ .compatible = "arm,mali-dp550" },
	396	{ .compatible = "arm,mali-dp650" },
	397	{ }
	398	};
	399
	400	U_BOOT_DRIVER(mali_dp) = {
	401	.name = "mali_dp",
	402	.id = UCLASS_VIDEO,
	403	.of_match = malidp_ids,
	404	.bind = malidp_bind,
	405	.probe = malidp_probe,
41575d8e	406	.priv_auto = sizeof(struct malidp_priv),
c1a65a8c LD	407	.ops = &malidp_ops,
c1a65a8c LD	408	};