[J-u-boot.git] / drivers / gpio / zynq_gpio.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Xilinx Zynq GPIO device driver
 *
 * Copyright (C) 2015 DAVE Embedded Systems <[email protected]>
 *
 * Most of code taken from linux kernel driver (linux/drivers/gpio/gpio-zynq.c)
 * Copyright (C) 2009 - 2014 Xilinx, Inc.
 */

#include <common.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/errno.h>
#include <dm.h>
#include <fdtdec.h>

/* Maximum banks */
#define ZYNQ_GPIO_MAX_BANK	4

#define ZYNQ_GPIO_BANK0_NGPIO	32
#define ZYNQ_GPIO_BANK1_NGPIO	22
#define ZYNQ_GPIO_BANK2_NGPIO	32
#define ZYNQ_GPIO_BANK3_NGPIO	32

#define ZYNQ_GPIO_NR_GPIOS	(ZYNQ_GPIO_BANK0_NGPIO + \
				 ZYNQ_GPIO_BANK1_NGPIO + \
				 ZYNQ_GPIO_BANK2_NGPIO + \
				 ZYNQ_GPIO_BANK3_NGPIO)

#define ZYNQMP_GPIO_MAX_BANK	6

#define ZYNQMP_GPIO_BANK0_NGPIO	26
#define ZYNQMP_GPIO_BANK1_NGPIO	26
#define ZYNQMP_GPIO_BANK2_NGPIO	26
#define ZYNQMP_GPIO_BANK3_NGPIO	32
#define ZYNQMP_GPIO_BANK4_NGPIO	32
#define ZYNQMP_GPIO_BANK5_NGPIO	32

#define ZYNQMP_GPIO_NR_GPIOS	174

#define ZYNQ_GPIO_BANK0_PIN_MIN(str)	0
#define ZYNQ_GPIO_BANK0_PIN_MAX(str)	(ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
					ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
#define ZYNQ_GPIO_BANK1_PIN_MIN(str)	(ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
#define ZYNQ_GPIO_BANK1_PIN_MAX(str)	(ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
					ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
#define ZYNQ_GPIO_BANK2_PIN_MIN(str)	(ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
#define ZYNQ_GPIO_BANK2_PIN_MAX(str)	(ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
					ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
#define ZYNQ_GPIO_BANK3_PIN_MIN(str)	(ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
#define ZYNQ_GPIO_BANK3_PIN_MAX(str)	(ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
					ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
#define ZYNQ_GPIO_BANK4_PIN_MIN(str)	(ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
#define ZYNQ_GPIO_BANK4_PIN_MAX(str)	(ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
					ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
#define ZYNQ_GPIO_BANK5_PIN_MIN(str)	(ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
#define ZYNQ_GPIO_BANK5_PIN_MAX(str)	(ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
					ZYNQ##str##_GPIO_BANK5_NGPIO - 1)

/* Register offsets for the GPIO device */
/* LSW Mask & Data -WO */
#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK)	(0x000 + (8 * BANK))
/* MSW Mask & Data -WO */
#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK)	(0x004 + (8 * BANK))
/* Data Register-RW */
#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK)	(0x060 + (4 * BANK))
/* Direction mode reg-RW */
#define ZYNQ_GPIO_DIRM_OFFSET(BANK)	(0x204 + (0x40 * BANK))
/* Output enable reg-RW */
#define ZYNQ_GPIO_OUTEN_OFFSET(BANK)	(0x208 + (0x40 * BANK))
/* Interrupt mask reg-RO */
#define ZYNQ_GPIO_INTMASK_OFFSET(BANK)	(0x20C + (0x40 * BANK))
/* Interrupt enable reg-WO */
#define ZYNQ_GPIO_INTEN_OFFSET(BANK)	(0x210 + (0x40 * BANK))
/* Interrupt disable reg-WO */
#define ZYNQ_GPIO_INTDIS_OFFSET(BANK)	(0x214 + (0x40 * BANK))
/* Interrupt status reg-RO */
#define ZYNQ_GPIO_INTSTS_OFFSET(BANK)	(0x218 + (0x40 * BANK))
/* Interrupt type reg-RW */
#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK)	(0x21C + (0x40 * BANK))
/* Interrupt polarity reg-RW */
#define ZYNQ_GPIO_INTPOL_OFFSET(BANK)	(0x220 + (0x40 * BANK))
/* Interrupt on any, reg-RW */
#define ZYNQ_GPIO_INTANY_OFFSET(BANK)	(0x224 + (0x40 * BANK))

/* Disable all interrupts mask */
#define ZYNQ_GPIO_IXR_DISABLE_ALL	0xFFFFFFFF

/* Mid pin number of a bank */
#define ZYNQ_GPIO_MID_PIN_NUM 16

/* GPIO upper 16 bit mask */
#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000

#define PMC_GPIO_NR_GPIOS	116
#define PMC_GPIO_MAX_BANK	5

struct zynq_gpio_platdata {
	phys_addr_t base;
	const struct zynq_platform_data *p_data;
};

/**
 * struct zynq_platform_data -  zynq gpio platform data structure
 * @label:	string to store in gpio->label
 * @ngpio:	max number of gpio pins
 * @max_bank:	maximum number of gpio banks
 * @bank_min:	this array represents bank's min pin
 * @bank_max:	this array represents bank's max pin
 */
struct zynq_platform_data {
	const char *label;
	u16 ngpio;
	u32 max_bank;
	u32 bank_min[ZYNQMP_GPIO_MAX_BANK];
	u32 bank_max[ZYNQMP_GPIO_MAX_BANK];
};

#define VERSAL_GPIO_NR_GPIOS	58
#define VERSAL_GPIO_MAX_BANK	4

static const struct zynq_platform_data versal_gpio_def = {
	.label = "versal_gpio",
	.ngpio = VERSAL_GPIO_NR_GPIOS,
	.max_bank = VERSAL_GPIO_MAX_BANK,
	.bank_min[0] = 0,
	.bank_max[0] = 25,
	.bank_min[3] = 26,
	.bank_max[3] = 57,
};

static const struct zynq_platform_data pmc_gpio_def = {
	.label = "pmc_gpio",
	.ngpio = PMC_GPIO_NR_GPIOS,
	.max_bank = PMC_GPIO_MAX_BANK,
	.bank_min[0] = 0,
	.bank_max[0] = 25,
	.bank_min[1] = 26,
	.bank_max[1] = 51,
	.bank_min[3] = 52,
	.bank_max[3] = 83,
	.bank_min[4] = 84,
	.bank_max[4] = 115,
};

static const struct zynq_platform_data zynqmp_gpio_def = {
	.label = "zynqmp_gpio",
	.ngpio = ZYNQMP_GPIO_NR_GPIOS,
	.max_bank = ZYNQMP_GPIO_MAX_BANK,
	.bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
	.bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
	.bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
	.bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
	.bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
	.bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
	.bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
	.bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
	.bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
	.bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
	.bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
	.bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
};

static const struct zynq_platform_data zynq_gpio_def = {
	.label = "zynq_gpio",
	.ngpio = ZYNQ_GPIO_NR_GPIOS,
	.max_bank = ZYNQ_GPIO_MAX_BANK,
	.bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
	.bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
	.bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
	.bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
	.bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
	.bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
	.bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
	.bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
};

/**
 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
 * for a given pin in the GPIO device
 * @pin_num:	gpio pin number within the device
 * @bank_num:	an output parameter used to return the bank number of the gpio
 *		pin
 * @bank_pin_num: an output parameter used to return pin number within a bank
 *		  for the given gpio pin
 *
 * Returns the bank number and pin offset within the bank.
 */
static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
					  unsigned int *bank_num,
					  unsigned int *bank_pin_num,
					  struct udevice *dev)
{
	struct zynq_gpio_platdata *plat = dev_get_platdata(dev);
	u32 bank;

	for (bank = 0; bank < plat->p_data->max_bank; bank++) {
		if (pin_num >= plat->p_data->bank_min[bank] &&
		    pin_num <= plat->p_data->bank_max[bank]) {
			*bank_num = bank;
			*bank_pin_num = pin_num -
					plat->p_data->bank_min[bank];
			return;
		}
	}

	if (bank >= plat->p_data->max_bank) {
		printf("Invalid bank and pin num\n");
		*bank_num = 0;
		*bank_pin_num = 0;
	}
}

static int gpio_is_valid(unsigned gpio, struct udevice *dev)
{
	struct zynq_gpio_platdata *plat = dev_get_platdata(dev);

	return gpio < plat->p_data->ngpio;
}

static int check_gpio(unsigned gpio, struct udevice *dev)
{
	if (!gpio_is_valid(gpio, dev)) {
		printf("ERROR : check_gpio: invalid GPIO %d\n", gpio);
		return -1;
	}
	return 0;
}

static int zynq_gpio_get_value(struct udevice *dev, unsigned gpio)
{
	u32 data;
	unsigned int bank_num, bank_pin_num;
	struct zynq_gpio_platdata *plat = dev_get_platdata(dev);

	if (check_gpio(gpio, dev) < 0)
		return -1;

	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);

	data = readl(plat->base +
			     ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));

	return (data >> bank_pin_num) & 1;
}

static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
{
	unsigned int reg_offset, bank_num, bank_pin_num;
	struct zynq_gpio_platdata *plat = dev_get_platdata(dev);

	if (check_gpio(gpio, dev) < 0)
		return -1;

	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);

	if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
		/* only 16 data bits in bit maskable reg */
		bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
		reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
	} else {
		reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
	}

	/*
	 * get the 32 bit value to be written to the mask/data register where
	 * the upper 16 bits is the mask and lower 16 bits is the data
	 */
	value = !!value;
	value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
		((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);

	writel(value, plat->base + reg_offset);

	return 0;
}

static int zynq_gpio_direction_input(struct udevice *dev, unsigned gpio)
{
	u32 reg;
	unsigned int bank_num, bank_pin_num;
	struct zynq_gpio_platdata *plat = dev_get_platdata(dev);

	if (check_gpio(gpio, dev) < 0)
		return -1;

	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);

	/* bank 0 pins 7 and 8 are special and cannot be used as inputs */
	if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8))
		return -1;

	/* clear the bit in direction mode reg to set the pin as input */
	reg = readl(plat->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
	reg &= ~BIT(bank_pin_num);
	writel(reg, plat->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));

	return 0;
}

static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio,
				      int value)
{
	u32 reg;
	unsigned int bank_num, bank_pin_num;
	struct zynq_gpio_platdata *plat = dev_get_platdata(dev);

	if (check_gpio(gpio, dev) < 0)
		return -1;

	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);

	/* set the GPIO pin as output */
	reg = readl(plat->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
	reg |= BIT(bank_pin_num);
	writel(reg, plat->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));

	/* configure the output enable reg for the pin */
	reg = readl(plat->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
	reg |= BIT(bank_pin_num);
	writel(reg, plat->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));

	/* set the state of the pin */
	zynq_gpio_set_value(dev, gpio, value);
	return 0;
}

static int zynq_gpio_get_function(struct udevice *dev, unsigned offset)
{
	u32 reg;
	unsigned int bank_num, bank_pin_num;
	struct zynq_gpio_platdata *plat = dev_get_platdata(dev);

	if (check_gpio(offset, dev) < 0)
		return -1;

	zynq_gpio_get_bank_pin(offset, &bank_num, &bank_pin_num, dev);

	/* set the GPIO pin as output */
	reg = readl(plat->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
	reg &= BIT(bank_pin_num);
	if (reg)
		return GPIOF_OUTPUT;
	else
		return GPIOF_INPUT;
}

static const struct dm_gpio_ops gpio_zynq_ops = {
	.direction_input	= zynq_gpio_direction_input,
	.direction_output	= zynq_gpio_direction_output,
	.get_value		= zynq_gpio_get_value,
	.set_value		= zynq_gpio_set_value,
	.get_function		= zynq_gpio_get_function,
};

static const struct udevice_id zynq_gpio_ids[] = {
	{ .compatible = "xlnx,zynq-gpio-1.0",
	  .data = (ulong)&zynq_gpio_def},
	{ .compatible = "xlnx,zynqmp-gpio-1.0",
	  .data = (ulong)&zynqmp_gpio_def},
	{ .compatible = "xlnx,versal-gpio-1.0",
	  .data = (ulong)&versal_gpio_def},
	{ .compatible = "xlnx,pmc-gpio-1.0",
	  .data = (ulong)&pmc_gpio_def },
	{ }
};

static int zynq_gpio_probe(struct udevice *dev)
{
	struct zynq_gpio_platdata *plat = dev_get_platdata(dev);
	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	const void *label_ptr;

	label_ptr = dev_read_prop(dev, "label", NULL);
	if (label_ptr) {
		uc_priv->bank_name = strdup(label_ptr);
		if (!uc_priv->bank_name)
			return -ENOMEM;
	} else {
		uc_priv->bank_name = dev->name;
	}

	if (plat->p_data)
		uc_priv->gpio_count = plat->p_data->ngpio;

	return 0;
}

static int zynq_gpio_ofdata_to_platdata(struct udevice *dev)
{
	struct zynq_gpio_platdata *plat = dev_get_platdata(dev);

	plat->base = (phys_addr_t)dev_read_addr(dev);

	plat->p_data =
		(struct zynq_platform_data *)dev_get_driver_data(dev);

	return 0;
}

U_BOOT_DRIVER(gpio_zynq) = {
	.name	= "gpio_zynq",
	.id	= UCLASS_GPIO,
	.ops	= &gpio_zynq_ops,
	.of_match = zynq_gpio_ids,
	.ofdata_to_platdata = zynq_gpio_ofdata_to_platdata,
	.probe	= zynq_gpio_probe,
	.plat_auto	= sizeof(struct zynq_gpio_platdata),
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
d37c6288 AS	2	/*
	3	* Xilinx Zynq GPIO device driver
	4	*
	5	* Copyright (C) 2015 DAVE Embedded Systems <[email protected]>
	6	*
	7	* Most of code taken from linux kernel driver (linux/drivers/gpio/gpio-zynq.c)
	8	* Copyright (C) 2009 - 2014 Xilinx, Inc.
d37c6288 AS	9	*/
	10
	11	#include <common.h>
	12	#include <asm/gpio.h>
	13	#include <asm/io.h>
cd93d625	14	#include <linux/bitops.h>
1221ce45	15	#include <linux/errno.h>
68c7026e SDPP	16	#include <dm.h>
	17	#include <fdtdec.h>
	18
f17abcae SDPP	19	/* Maximum banks */
	20	#define ZYNQ_GPIO_MAX_BANK 4
	21
	22	#define ZYNQ_GPIO_BANK0_NGPIO 32
	23	#define ZYNQ_GPIO_BANK1_NGPIO 22
	24	#define ZYNQ_GPIO_BANK2_NGPIO 32
	25	#define ZYNQ_GPIO_BANK3_NGPIO 32
	26
	27	#define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \
	28	ZYNQ_GPIO_BANK1_NGPIO + \
	29	ZYNQ_GPIO_BANK2_NGPIO + \
	30	ZYNQ_GPIO_BANK3_NGPIO)
	31
404a00c7 SDPP	32	#define ZYNQMP_GPIO_MAX_BANK 6
	33
	34	#define ZYNQMP_GPIO_BANK0_NGPIO 26
	35	#define ZYNQMP_GPIO_BANK1_NGPIO 26
	36	#define ZYNQMP_GPIO_BANK2_NGPIO 26
	37	#define ZYNQMP_GPIO_BANK3_NGPIO 32
	38	#define ZYNQMP_GPIO_BANK4_NGPIO 32
	39	#define ZYNQMP_GPIO_BANK5_NGPIO 32
	40
	41	#define ZYNQMP_GPIO_NR_GPIOS 174
	42
	43	#define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
	44	#define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
	45	ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
	46	#define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
	47	#define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
	48	ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
	49	#define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
	50	#define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
	51	ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
	52	#define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
	53	#define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
	54	ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
	55	#define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
	56	#define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
	57	ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
	58	#define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
	59	#define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
	60	ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
f17abcae SDPP	61
	62	/* Register offsets for the GPIO device */
	63	/* LSW Mask & Data -WO */
	64	#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
	65	/* MSW Mask & Data -WO */
	66	#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
	67	/* Data Register-RW */
	68	#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
	69	/* Direction mode reg-RW */
	70	#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
	71	/* Output enable reg-RW */
	72	#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
	73	/* Interrupt mask reg-RO */
	74	#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
	75	/* Interrupt enable reg-WO */
	76	#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
	77	/* Interrupt disable reg-WO */
	78	#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
	79	/* Interrupt status reg-RO */
	80	#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
	81	/* Interrupt type reg-RW */
	82	#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
	83	/* Interrupt polarity reg-RW */
	84	#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
	85	/* Interrupt on any, reg-RW */
	86	#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
	87
	88	/* Disable all interrupts mask */
	89	#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
	90
	91	/* Mid pin number of a bank */
	92	#define ZYNQ_GPIO_MID_PIN_NUM 16
	93
	94	/* GPIO upper 16 bit mask */
	95	#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
	96
98927daa SD	97	#define PMC_GPIO_NR_GPIOS 116
	98	#define PMC_GPIO_MAX_BANK 5
	99
0f072573	100	struct zynq_gpio_platdata {
68c7026e	101	phys_addr_t base;
404a00c7 SDPP	102	const struct zynq_platform_data *p_data;
	103	};
	104
	105	/**
	106	* struct zynq_platform_data - zynq gpio platform data structure
	107	* @label: string to store in gpio->label
	108	* @ngpio: max number of gpio pins
	109	* @max_bank: maximum number of gpio banks
	110	* @bank_min: this array represents bank's min pin
	111	* @bank_max: this array represents bank's max pin
	112	*/
	113	struct zynq_platform_data {
	114	const char *label;
	115	u16 ngpio;
01fcf01e MS	116	u32 max_bank;
	117	u32 bank_min[ZYNQMP_GPIO_MAX_BANK];
	118	u32 bank_max[ZYNQMP_GPIO_MAX_BANK];
404a00c7 SDPP	119	};
404a00c7 SDPP	120
98248521 ARS	121	#define VERSAL_GPIO_NR_GPIOS 58
	122	#define VERSAL_GPIO_MAX_BANK 4
	123
	124	static const struct zynq_platform_data versal_gpio_def = {
	125	.label = "versal_gpio",
	126	.ngpio = VERSAL_GPIO_NR_GPIOS,
	127	.max_bank = VERSAL_GPIO_MAX_BANK,
	128	.bank_min[0] = 0,
	129	.bank_max[0] = 25,
	130	.bank_min[3] = 26,
	131	.bank_max[3] = 57,
	132	};
	133
98927daa SD	134	static const struct zynq_platform_data pmc_gpio_def = {
	135	.label = "pmc_gpio",
	136	.ngpio = PMC_GPIO_NR_GPIOS,
	137	.max_bank = PMC_GPIO_MAX_BANK,
	138	.bank_min[0] = 0,
	139	.bank_max[0] = 25,
	140	.bank_min[1] = 26,
	141	.bank_max[1] = 51,
	142	.bank_min[3] = 52,
	143	.bank_max[3] = 83,
	144	.bank_min[4] = 84,
	145	.bank_max[4] = 115,
	146	};
	147
404a00c7 SDPP	148	static const struct zynq_platform_data zynqmp_gpio_def = {
	149	.label = "zynqmp_gpio",
	150	.ngpio = ZYNQMP_GPIO_NR_GPIOS,
	151	.max_bank = ZYNQMP_GPIO_MAX_BANK,
	152	.bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
	153	.bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
	154	.bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
	155	.bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
	156	.bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
	157	.bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
	158	.bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
	159	.bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
	160	.bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
	161	.bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
	162	.bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
	163	.bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
	164	};
	165
	166	static const struct zynq_platform_data zynq_gpio_def = {
	167	.label = "zynq_gpio",
	168	.ngpio = ZYNQ_GPIO_NR_GPIOS,
	169	.max_bank = ZYNQ_GPIO_MAX_BANK,
	170	.bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
	171	.bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
	172	.bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
	173	.bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
	174	.bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
	175	.bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
	176	.bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
	177	.bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
68c7026e	178	};
68c7026e	179
d37c6288 AS	180	/**
	181	* zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
	182	* for a given pin in the GPIO device
	183	* @pin_num: gpio pin number within the device
	184	* @bank_num: an output parameter used to return the bank number of the gpio
	185	* pin
	186	* @bank_pin_num: an output parameter used to return pin number within a bank
	187	* for the given gpio pin
	188	*
	189	* Returns the bank number and pin offset within the bank.
	190	*/
	191	static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
	192	unsigned int *bank_num,
404a00c7 SDPP	193	unsigned int *bank_pin_num,
404a00c7 SDPP	194	struct udevice *dev)
d37c6288	195	{
caa4daa2	196	struct zynq_gpio_platdata *plat = dev_get_platdata(dev);
01fcf01e	197	u32 bank;
404a00c7	198
caa4daa2 SG	199	for (bank = 0; bank < plat->p_data->max_bank; bank++) {
	200	if (pin_num >= plat->p_data->bank_min[bank] &&
	201	pin_num <= plat->p_data->bank_max[bank]) {
0f072573 VK	202	*bank_num = bank;
0f072573 VK	203	*bank_pin_num = pin_num -
caa4daa2	204	plat->p_data->bank_min[bank];
0f072573	205	return;
404a00c7 SDPP	206	}
	207	}
	208
caa4daa2	209	if (bank >= plat->p_data->max_bank) {
946205a8	210	printf("Invalid bank and pin num\n");
d37c6288 AS	211	*bank_num = 0;
d37c6288 AS	212	*bank_pin_num = 0;
d37c6288 AS	213	}
	214	}
	215
404a00c7	216	static int gpio_is_valid(unsigned gpio, struct udevice *dev)
d37c6288	217	{
caa4daa2	218	struct zynq_gpio_platdata *plat = dev_get_platdata(dev);
404a00c7	219
caa4daa2	220	return gpio < plat->p_data->ngpio;
d37c6288 AS	221	}
d37c6288 AS	222
404a00c7	223	static int check_gpio(unsigned gpio, struct udevice *dev)
d37c6288	224	{
404a00c7	225	if (!gpio_is_valid(gpio, dev)) {
d37c6288 AS	226	printf("ERROR : check_gpio: invalid GPIO %d\n", gpio);
	227	return -1;
	228	}
	229	return 0;
	230	}
	231
68c7026e SDPP	232	static int zynq_gpio_get_value(struct udevice *dev, unsigned gpio)
	233	{
	234	u32 data;
	235	unsigned int bank_num, bank_pin_num;
caa4daa2	236	struct zynq_gpio_platdata *plat = dev_get_platdata(dev);
68c7026e	237
404a00c7	238	if (check_gpio(gpio, dev) < 0)
68c7026e SDPP	239	return -1;
68c7026e SDPP	240
404a00c7	241	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
68c7026e	242
caa4daa2	243	data = readl(plat->base +
68c7026e SDPP	244	ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
	245
	246	return (data >> bank_pin_num) & 1;
	247	}
	248
	249	static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
	250	{
	251	unsigned int reg_offset, bank_num, bank_pin_num;
caa4daa2	252	struct zynq_gpio_platdata *plat = dev_get_platdata(dev);
68c7026e	253
404a00c7	254	if (check_gpio(gpio, dev) < 0)
68c7026e SDPP	255	return -1;
68c7026e SDPP	256
404a00c7	257	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
68c7026e SDPP	258
	259	if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
	260	/* only 16 data bits in bit maskable reg */
	261	bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
	262	reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
	263	} else {
	264	reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
	265	}
	266
	267	/*
	268	* get the 32 bit value to be written to the mask/data register where
	269	* the upper 16 bits is the mask and lower 16 bits is the data
	270	*/
	271	value = !!value;
	272	value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
	273	((value << bank_pin_num) \| ZYNQ_GPIO_UPPER_MASK);
	274
caa4daa2	275	writel(value, plat->base + reg_offset);
68c7026e SDPP	276
	277	return 0;
	278	}
	279
	280	static int zynq_gpio_direction_input(struct udevice *dev, unsigned gpio)
	281	{
	282	u32 reg;
	283	unsigned int bank_num, bank_pin_num;
caa4daa2	284	struct zynq_gpio_platdata *plat = dev_get_platdata(dev);
68c7026e	285
404a00c7	286	if (check_gpio(gpio, dev) < 0)
68c7026e SDPP	287	return -1;
68c7026e SDPP	288
404a00c7	289	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
68c7026e SDPP	290
	291	/* bank 0 pins 7 and 8 are special and cannot be used as inputs */
	292	if (bank_num == 0 && (bank_pin_num == 7 \|\| bank_pin_num == 8))
	293	return -1;
	294
	295	/* clear the bit in direction mode reg to set the pin as input */
caa4daa2	296	reg = readl(plat->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
68c7026e	297	reg &= ~BIT(bank_pin_num);
caa4daa2	298	writel(reg, plat->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
68c7026e SDPP	299
	300	return 0;
	301	}
	302
	303	static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio,
	304	int value)
	305	{
	306	u32 reg;
	307	unsigned int bank_num, bank_pin_num;
caa4daa2	308	struct zynq_gpio_platdata *plat = dev_get_platdata(dev);
68c7026e	309
404a00c7	310	if (check_gpio(gpio, dev) < 0)
68c7026e SDPP	311	return -1;
68c7026e SDPP	312
404a00c7	313	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
68c7026e SDPP	314
68c7026e SDPP	315	/* set the GPIO pin as output */
caa4daa2	316	reg = readl(plat->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
68c7026e	317	reg \|= BIT(bank_pin_num);
caa4daa2	318	writel(reg, plat->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
68c7026e SDPP	319
68c7026e SDPP	320	/* configure the output enable reg for the pin */
caa4daa2	321	reg = readl(plat->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
68c7026e	322	reg \|= BIT(bank_pin_num);
caa4daa2	323	writel(reg, plat->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
68c7026e SDPP	324
68c7026e SDPP	325	/* set the state of the pin */
0384ac05	326	zynq_gpio_set_value(dev, gpio, value);
68c7026e SDPP	327	return 0;
	328	}
	329
a6b9587b MS	330	static int zynq_gpio_get_function(struct udevice *dev, unsigned offset)
	331	{
	332	u32 reg;
	333	unsigned int bank_num, bank_pin_num;
caa4daa2	334	struct zynq_gpio_platdata *plat = dev_get_platdata(dev);
a6b9587b MS	335
	336	if (check_gpio(offset, dev) < 0)
	337	return -1;
	338
	339	zynq_gpio_get_bank_pin(offset, &bank_num, &bank_pin_num, dev);
	340
	341	/* set the GPIO pin as output */
caa4daa2	342	reg = readl(plat->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
a6b9587b MS	343	reg &= BIT(bank_pin_num);
	344	if (reg)
	345	return GPIOF_OUTPUT;
	346	else
	347	return GPIOF_INPUT;
	348	}
	349
68c7026e SDPP	350	static const struct dm_gpio_ops gpio_zynq_ops = {
	351	.direction_input = zynq_gpio_direction_input,
	352	.direction_output = zynq_gpio_direction_output,
	353	.get_value = zynq_gpio_get_value,
	354	.set_value = zynq_gpio_set_value,
a6b9587b	355	.get_function = zynq_gpio_get_function,
68c7026e SDPP	356	};
68c7026e SDPP	357
404a00c7 SDPP	358	static const struct udevice_id zynq_gpio_ids[] = {
	359	{ .compatible = "xlnx,zynq-gpio-1.0",
	360	.data = (ulong)&zynq_gpio_def},
	361	{ .compatible = "xlnx,zynqmp-gpio-1.0",
	362	.data = (ulong)&zynqmp_gpio_def},
98248521 ARS	363	{ .compatible = "xlnx,versal-gpio-1.0",
98248521 ARS	364	.data = (ulong)&versal_gpio_def},
98927daa SD	365	{ .compatible = "xlnx,pmc-gpio-1.0",
98927daa SD	366	.data = (ulong)&pmc_gpio_def },
404a00c7 SDPP	367	{ }
	368	};
	369
68c7026e SDPP	370	static int zynq_gpio_probe(struct udevice *dev)
68c7026e SDPP	371	{
caa4daa2	372	struct zynq_gpio_platdata *plat = dev_get_platdata(dev);
404a00c7	373	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
312dd1c5	374	const void *label_ptr;
68c7026e	375
312dd1c5 MS	376	label_ptr = dev_read_prop(dev, "label", NULL);
	377	if (label_ptr) {
	378	uc_priv->bank_name = strdup(label_ptr);
	379	if (!uc_priv->bank_name)
	380	return -ENOMEM;
	381	} else {
	382	uc_priv->bank_name = dev->name;
	383	}
0d6fabb8	384
caa4daa2 SG	385	if (plat->p_data)
caa4daa2 SG	386	uc_priv->gpio_count = plat->p_data->ngpio;
68c7026e SDPP	387
	388	return 0;
	389	}
	390
	391	static int zynq_gpio_ofdata_to_platdata(struct udevice *dev)
	392	{
caa4daa2	393	struct zynq_gpio_platdata *plat = dev_get_platdata(dev);
68c7026e	394
caa4daa2	395	plat->base = (phys_addr_t)dev_read_addr(dev);
68c7026e	396
caa4daa2	397	plat->p_data =
0f072573	398	(struct zynq_platform_data *)dev_get_driver_data(dev);
0df9bea4	399
68c7026e SDPP	400	return 0;
	401	}
	402
68c7026e SDPP	403	U_BOOT_DRIVER(gpio_zynq) = {
	404	.name = "gpio_zynq",
	405	.id = UCLASS_GPIO,
	406	.ops = &gpio_zynq_ops,
	407	.of_match = zynq_gpio_ids,
	408	.ofdata_to_platdata = zynq_gpio_ofdata_to_platdata,
	409	.probe = zynq_gpio_probe,
caa4daa2	410	.plat_auto = sizeof(struct zynq_gpio_platdata),
68c7026e	411	};