[J-u-boot.git] / drivers / mmc / snps_dw_mmc.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Synopsys DesignWare Multimedia Card Interface driver
 * extensions used in various Synopsys ARC devboards.
 *
 * Copyright (C) 2019 Synopsys
 * Author: Eugeniy Paltsev <[email protected]>
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <dwmmc.h>
#include <errno.h>
#include <fdtdec.h>
#include <dm/device_compat.h>
#include <linux/libfdt.h>
#include <linux/err.h>
#include <malloc.h>

#define CLOCK_MIN		400000	/*  400 kHz */
#define FIFO_MIN		8
#define FIFO_MAX		4096

struct snps_dwmci_plat {
	struct mmc_config	cfg;
	struct mmc		mmc;
};

struct snps_dwmci_priv_data {
	struct dwmci_host	host;
	u32			f_max;
};

static int snps_dwmmc_clk_setup(struct udevice *dev)
{
	struct snps_dwmci_priv_data *priv = dev_get_priv(dev);
	struct dwmci_host *host = &priv->host;

	struct clk clk_ciu, clk_biu;
	int ret;

	ret = clk_get_by_name(dev, "ciu", &clk_ciu);
	if (ret)
		goto clk_err;

	ret = clk_enable(&clk_ciu);
	if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
		goto clk_err;

	host->bus_hz = clk_get_rate(&clk_ciu);
	if (host->bus_hz < CLOCK_MIN) {
		ret = -EINVAL;
		goto clk_err_ciu_dis;
	}

	ret = clk_get_by_name(dev, "biu", &clk_biu);
	if (ret)
		goto clk_err_ciu_dis;

	ret = clk_enable(&clk_biu);
	if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
		goto clk_err_ciu_dis;

	return 0;

clk_err_ciu_dis:
	clk_disable(&clk_ciu);
clk_err:
	dev_err(dev, "failed to setup clocks, ret %d\n", ret);

	return ret;
}

static int snps_dwmmc_of_to_plat(struct udevice *dev)
{
	struct snps_dwmci_priv_data *priv = dev_get_priv(dev);
	struct dwmci_host *host = &priv->host;
	u32 fifo_depth;
	int ret;

	host->ioaddr = dev_read_addr_ptr(dev);

	/*
	 * If fifo-depth is unset don't set fifoth_val - we will try to
	 * auto detect it.
	 */
	ret = dev_read_u32(dev, "fifo-depth", &fifo_depth);
	if (!ret) {
		if (fifo_depth < FIFO_MIN || fifo_depth > FIFO_MAX)
			return -EINVAL;

		host->fifoth_val = MSIZE(0x2) |
				   RX_WMARK(fifo_depth / 2 - 1) |
				   TX_WMARK(fifo_depth / 2);
	}

	host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
	if (host->buswidth != 1 && host->buswidth != 4 && host->buswidth != 8)
		return -EINVAL;

	/*
	 * If max-frequency is unset don't set priv->f_max - we will use
	 * host->bus_hz in probe() instead.
	 */
	ret = dev_read_u32(dev, "max-frequency", &priv->f_max);
	if (!ret && priv->f_max < CLOCK_MIN)
		return -EINVAL;

	host->fifo_mode = dev_read_bool(dev, "fifo-mode");
	host->name = dev->name;
	host->dev_index = 0;
	host->priv = priv;

	return 0;
}

int snps_dwmmc_getcd(struct udevice *dev)
{
	struct snps_dwmci_priv_data *priv = dev_get_priv(dev);
	struct dwmci_host *host = &priv->host;

	return !(dwmci_readl(host, DWMCI_CDETECT) & 1);
}

struct dm_mmc_ops snps_dwmci_dm_ops;

static int snps_dwmmc_probe(struct udevice *dev)
{
#ifdef CONFIG_BLK
	struct snps_dwmci_plat *plat = dev_get_plat(dev);
#endif
	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	struct snps_dwmci_priv_data *priv = dev_get_priv(dev);
	struct dwmci_host *host = &priv->host;
	unsigned int clock_max;
	int ret;

	/* Extend generic 'dm_dwmci_ops' with our 'getcd' implementation */
	memcpy(&snps_dwmci_dm_ops, &dm_dwmci_ops, sizeof(struct dm_mmc_ops));
	snps_dwmci_dm_ops.get_cd = snps_dwmmc_getcd;

	ret = snps_dwmmc_clk_setup(dev);
	if (ret)
		return ret;

	if (!priv->f_max)
		clock_max = host->bus_hz;
	else
		clock_max = min_t(unsigned int, host->bus_hz, priv->f_max);

#ifdef CONFIG_BLK
	dwmci_setup_cfg(&plat->cfg, host, clock_max, CLOCK_MIN);
	host->mmc = &plat->mmc;
#else
	ret = add_dwmci(host, clock_max, CLOCK_MIN);
	if (ret)
		return ret;
#endif
	host->mmc->priv = &priv->host;
	upriv->mmc = host->mmc;
	host->mmc->dev = dev;

	return dwmci_probe(dev);
}

static int snps_dwmmc_bind(struct udevice *dev)
{
#ifdef CONFIG_BLK
	struct snps_dwmci_plat *plat = dev_get_plat(dev);
	int ret;

	ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
	if (ret)
		return ret;
#endif

	return 0;
}

static const struct udevice_id snps_dwmmc_ids[] = {
	{ .compatible = "snps,dw-mshc" },
	{ }
};

U_BOOT_DRIVER(snps_dwmmc_drv) = {
	.name				= "snps_dw_mmc",
	.id				= UCLASS_MMC,
	.of_match			= snps_dwmmc_ids,
	.of_to_plat		= snps_dwmmc_of_to_plat,
	.ops				= &snps_dwmci_dm_ops,
	.bind				= snps_dwmmc_bind,
	.probe				= snps_dwmmc_probe,
	.priv_auto		= sizeof(struct snps_dwmci_priv_data),
	.plat_auto	= sizeof(struct snps_dwmci_plat),
};
Commit	Line	Data
15736e28 EP	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Synopsys DesignWare Multimedia Card Interface driver
	4	* extensions used in various Synopsys ARC devboards.
	5	*
	6	* Copyright (C) 2019 Synopsys
	7	* Author: Eugeniy Paltsev <[email protected]>
	8	*/
	9
	10	#include <common.h>
	11	#include <clk.h>
	12	#include <dm.h>
	13	#include <dwmmc.h>
	14	#include <errno.h>
	15	#include <fdtdec.h>
336d4615	16	#include <dm/device_compat.h>
15736e28 EP	17	#include <linux/libfdt.h>
	18	#include <linux/err.h>
	19	#include <malloc.h>
	20
	21	#define CLOCK_MIN 400000 /* 400 kHz */
	22	#define FIFO_MIN 8
	23	#define FIFO_MAX 4096
	24
	25	struct snps_dwmci_plat {
	26	struct mmc_config cfg;
	27	struct mmc mmc;
	28	};
	29
	30	struct snps_dwmci_priv_data {
	31	struct dwmci_host host;
	32	u32 f_max;
	33	};
	34
	35	static int snps_dwmmc_clk_setup(struct udevice *dev)
	36	{
	37	struct snps_dwmci_priv_data *priv = dev_get_priv(dev);
	38	struct dwmci_host *host = &priv->host;
	39
	40	struct clk clk_ciu, clk_biu;
	41	int ret;
	42
	43	ret = clk_get_by_name(dev, "ciu", &clk_ciu);
	44	if (ret)
	45	goto clk_err;
	46
	47	ret = clk_enable(&clk_ciu);
	48	if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
c9309f40	49	goto clk_err;
15736e28 EP	50
	51	host->bus_hz = clk_get_rate(&clk_ciu);
	52	if (host->bus_hz < CLOCK_MIN) {
	53	ret = -EINVAL;
	54	goto clk_err_ciu_dis;
	55	}
	56
	57	ret = clk_get_by_name(dev, "biu", &clk_biu);
	58	if (ret)
	59	goto clk_err_ciu_dis;
	60
	61	ret = clk_enable(&clk_biu);
	62	if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
c9309f40	63	goto clk_err_ciu_dis;
15736e28 EP	64
	65	return 0;
	66
15736e28 EP	67	clk_err_ciu_dis:
15736e28 EP	68	clk_disable(&clk_ciu);
15736e28 EP	69	clk_err:
	70	dev_err(dev, "failed to setup clocks, ret %d\n", ret);
	71
	72	return ret;
	73	}
	74
d1998a9f	75	static int snps_dwmmc_of_to_plat(struct udevice *dev)
15736e28 EP	76	{
	77	struct snps_dwmci_priv_data *priv = dev_get_priv(dev);
	78	struct dwmci_host *host = &priv->host;
	79	u32 fifo_depth;
	80	int ret;
	81
702e57e1	82	host->ioaddr = dev_read_addr_ptr(dev);
15736e28 EP	83
	84	/*
	85	* If fifo-depth is unset don't set fifoth_val - we will try to
	86	* auto detect it.
	87	*/
	88	ret = dev_read_u32(dev, "fifo-depth", &fifo_depth);
	89	if (!ret) {
	90	if (fifo_depth < FIFO_MIN \|\| fifo_depth > FIFO_MAX)
	91	return -EINVAL;
	92
	93	host->fifoth_val = MSIZE(0x2) \|
	94	RX_WMARK(fifo_depth / 2 - 1) \|
	95	TX_WMARK(fifo_depth / 2);
	96	}
	97
	98	host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
	99	if (host->buswidth != 1 && host->buswidth != 4 && host->buswidth != 8)
	100	return -EINVAL;
	101
	102	/*
	103	* If max-frequency is unset don't set priv->f_max - we will use
	104	* host->bus_hz in probe() instead.
	105	*/
	106	ret = dev_read_u32(dev, "max-frequency", &priv->f_max);
	107	if (!ret && priv->f_max < CLOCK_MIN)
	108	return -EINVAL;
	109
	110	host->fifo_mode = dev_read_bool(dev, "fifo-mode");
	111	host->name = dev->name;
	112	host->dev_index = 0;
	113	host->priv = priv;
	114
	115	return 0;
	116	}
	117
	118	int snps_dwmmc_getcd(struct udevice *dev)
	119	{
	120	struct snps_dwmci_priv_data *priv = dev_get_priv(dev);
	121	struct dwmci_host *host = &priv->host;
	122
	123	return !(dwmci_readl(host, DWMCI_CDETECT) & 1);
	124	}
	125
	126	struct dm_mmc_ops snps_dwmci_dm_ops;
	127
	128	static int snps_dwmmc_probe(struct udevice *dev)
	129	{
	130	#ifdef CONFIG_BLK
c69cda25	131	struct snps_dwmci_plat *plat = dev_get_plat(dev);
15736e28 EP	132	#endif
	133	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	134	struct snps_dwmci_priv_data *priv = dev_get_priv(dev);
	135	struct dwmci_host *host = &priv->host;
	136	unsigned int clock_max;
	137	int ret;
	138
	139	/* Extend generic 'dm_dwmci_ops' with our 'getcd' implementation */
	140	memcpy(&snps_dwmci_dm_ops, &dm_dwmci_ops, sizeof(struct dm_mmc_ops));
	141	snps_dwmci_dm_ops.get_cd = snps_dwmmc_getcd;
	142
	143	ret = snps_dwmmc_clk_setup(dev);
	144	if (ret)
	145	return ret;
	146
	147	if (!priv->f_max)
	148	clock_max = host->bus_hz;
	149	else
	150	clock_max = min_t(unsigned int, host->bus_hz, priv->f_max);
	151
	152	#ifdef CONFIG_BLK
	153	dwmci_setup_cfg(&plat->cfg, host, clock_max, CLOCK_MIN);
	154	host->mmc = &plat->mmc;
	155	#else
	156	ret = add_dwmci(host, clock_max, CLOCK_MIN);
	157	if (ret)
	158	return ret;
	159	#endif
	160	host->mmc->priv = &priv->host;
	161	upriv->mmc = host->mmc;
	162	host->mmc->dev = dev;
	163
	164	return dwmci_probe(dev);
	165	}
	166
	167	static int snps_dwmmc_bind(struct udevice *dev)
	168	{
	169	#ifdef CONFIG_BLK
c69cda25	170	struct snps_dwmci_plat *plat = dev_get_plat(dev);
15736e28 EP	171	int ret;
	172
	173	ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
	174	if (ret)
	175	return ret;
	176	#endif
	177
	178	return 0;
	179	}
	180
	181	static const struct udevice_id snps_dwmmc_ids[] = {
	182	{ .compatible = "snps,dw-mshc" },
	183	{ }
	184	};
	185
	186	U_BOOT_DRIVER(snps_dwmmc_drv) = {
	187	.name = "snps_dw_mmc",
	188	.id = UCLASS_MMC,
	189	.of_match = snps_dwmmc_ids,
d1998a9f	190	.of_to_plat = snps_dwmmc_of_to_plat,
15736e28 EP	191	.ops = &snps_dwmci_dm_ops,
	192	.bind = snps_dwmmc_bind,
	193	.probe = snps_dwmmc_probe,
41575d8e	194	.priv_auto = sizeof(struct snps_dwmci_priv_data),
caa4daa2	195	.plat_auto = sizeof(struct snps_dwmci_plat),
15736e28	196	};