projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| f981e66e | 1 | AX25 is Andes CPU IP to adopt RISC-V architecture. |
| 3fafced7 RC |
2 | |
| 3 | Features | |
| 4 | ======== | |
| 5 | ||
| 6 | CPU Core | |
| 7 | - 5-stage in-order execution pipeline | |
| 8 | - Hardware Multiplier | |
| 9 | - radix-2/radix-4/radix-16/radix-256/fast | |
| 10 | - Hardware Divider | |
| 11 | - Optional branch prediction | |
| 12 | - Machine mode and optional user mode | |
| 13 | - Optional performance monitoring | |
| 14 | ||
| 15 | ISA | |
| 16 | - RV64I base integer instructions | |
| 17 | - RVC for 16-bit compressed instructions | |
| 18 | - RVM for multiplication and division instructions | |
| 19 | ||
| 20 | Memory subsystem | |
| 21 | - I & D local memory | |
| 22 | - Size: 4KB to 16MB | |
| 23 | - Memory subsyetem soft-error protection | |
| 24 | - Protection scheme: parity-checking or error-checking-and-correction (ECC) | |
| 25 | - Automatic hardware error correction | |
| 26 | ||
| 27 | Bus | |
| 28 | - Interface Protocol | |
| 29 | - Synchronous AHB (32-bit/64-bit data-width), or | |
| 30 | - Synchronous AXI4 (64-bit data-width) | |
| 31 | ||
| 32 | Power management | |
| 33 | - Wait for interrupt (WFI) mode | |
| 34 | ||
| 35 | Debug | |
| 36 | - Configurable number of breakpoints: 2/4/8 | |
| 37 | - External Debug Module | |
| 38 | - AHB slave port | |
| 39 | - External JTAG debug transport module | |
| 40 | ||
| 41 | Platform Level Interrupt Controller (PLIC) | |
| 42 | - AHB slave port | |
| 43 | - Configurable number of interrupts: 1-1023 | |
| 44 | - Configurable number of interrupt priorities: 3/7/15/63/127/255 | |
| 45 | - Configurable number of targets: 1-16 | |
| 46 | - Preempted interrupt priority stack |