[J-u-boot.git] / include / configs / da850evm.h

/*
 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
 *
 * Based on davinci_dvevm.h. Original Copyrights follow:
 *
 * Copyright (C) 2007 Sergey Kubushyn <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * Board
 */
#define CONFIG_DRIVER_TI_EMAC
/* check if direct NOR boot config is used */
#ifndef CONFIG_DIRECT_NOR_BOOT
#define CONFIG_USE_SPIFLASH
#endif

/*
 * SoC Configuration
 */
#define CONFIG_MACH_DAVINCI_DA850_EVM
#define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
#define CONFIG_SOC_DA850		/* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ		24000000
#define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)

#ifdef CONFIG_DIRECT_NOR_BOOT
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DA8XX_GPIO
#define CONFIG_SYS_TEXT_BASE		0x60000000
#define CONFIG_SYS_DV_NOR_BOOT_CFG	(0x11)
#define CONFIG_DA850_LOWLEVEL
#else
#define CONFIG_SYS_TEXT_BASE		0xc1080000
#endif

/*
 * Memory Info
 */
#define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
#define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
#define PHYS_SDRAM_1_SIZE	(64 << 20) /* SDRAM size 64MB */
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/

/* memtest start addr */
#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)

/* memtest will be run on 16MB */
#define CONFIG_SYS_MEMTEST_END 	(PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)

#define CONFIG_NR_DRAM_BANKS	1 /* we have 1 bank of DRAM */

#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
	DAVINCI_SYSCFG_SUSPSRC_SPI1 |		\
	DAVINCI_SYSCFG_SUSPSRC_UART2 |		\
	DAVINCI_SYSCFG_SUSPSRC_EMAC |		\
	DAVINCI_SYSCFG_SUSPSRC_I2C)

/*
 * PLL configuration
 */
#define CONFIG_SYS_DV_CLKMODE          0
#define CONFIG_SYS_DA850_PLL0_POSTDIV  1
#define CONFIG_SYS_DA850_PLL0_PLLDIV1  0x8000
#define CONFIG_SYS_DA850_PLL0_PLLDIV2  0x8001
#define CONFIG_SYS_DA850_PLL0_PLLDIV3  0x8002
#define CONFIG_SYS_DA850_PLL0_PLLDIV4  0x8003
#define CONFIG_SYS_DA850_PLL0_PLLDIV5  0x8002
#define CONFIG_SYS_DA850_PLL0_PLLDIV6  CONFIG_SYS_DA850_PLL0_PLLDIV1
#define CONFIG_SYS_DA850_PLL0_PLLDIV7  0x8005

#define CONFIG_SYS_DA850_PLL1_POSTDIV  1
#define CONFIG_SYS_DA850_PLL1_PLLDIV1  0x8000
#define CONFIG_SYS_DA850_PLL1_PLLDIV2  0x8001
#define CONFIG_SYS_DA850_PLL1_PLLDIV3  0x8002

#define CONFIG_SYS_DA850_PLL0_PLLM     24
#define CONFIG_SYS_DA850_PLL1_PLLM     21

/*
 * DDR2 memory configuration
 */
#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
					DV_DDR_PHY_EXT_STRBEN | \
					(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))

#define CONFIG_SYS_DA850_DDR2_SDBCR (		\
	(1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |	\
	(1 << DV_DDR_SDCR_DDREN_SHIFT) |	\
	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |	\
	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |	\
	(0x3 << DV_DDR_SDCR_CL_SHIFT) |		\
	(0x2 << DV_DDR_SDCR_IBANK_SHIFT) |	\
	(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))

/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
#define CONFIG_SYS_DA850_DDR2_SDBCR2 0

#define CONFIG_SYS_DA850_DDR2_SDTIMR (		\
	(14 << DV_DDR_SDTMR1_RFC_SHIFT) |	\
	(2 << DV_DDR_SDTMR1_RP_SHIFT) |		\
	(2 << DV_DDR_SDTMR1_RCD_SHIFT) |	\
	(1 << DV_DDR_SDTMR1_WR_SHIFT) |		\
	(5 << DV_DDR_SDTMR1_RAS_SHIFT) |	\
	(8 << DV_DDR_SDTMR1_RC_SHIFT) |		\
	(1 << DV_DDR_SDTMR1_RRD_SHIFT) |	\
	(0 << DV_DDR_SDTMR1_WTR_SHIFT))

#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (		\
	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |	\
	(0 << DV_DDR_SDTMR2_XP_SHIFT) |		\
	(0 << DV_DDR_SDTMR2_ODT_SHIFT) |	\
	(17 << DV_DDR_SDTMR2_XSNR_SHIFT) |	\
	(199 << DV_DDR_SDTMR2_XSRD_SHIFT) |	\
	(0 << DV_DDR_SDTMR2_RTP_SHIFT) |	\
	(0 << DV_DDR_SDTMR2_CKE_SHIFT))

#define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000494
#define CONFIG_SYS_DA850_DDR2_PBBPR    0x30

/*
 * Serial Driver info
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1	DAVINCI_UART2_BASE /* Base address of UART2 */
#define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
#define CONFIG_BAUDRATE		115200		/* Default baud rate */

#define CONFIG_SPI
#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
#define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)
#define CONFIG_SF_DEFAULT_SPEED		30000000
#define CONFIG_ENV_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED

#ifdef CONFIG_USE_SPIFLASH
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8000
#define CONFIG_SYS_SPI_U_BOOT_SIZE	0x40000
#endif

/*
 * I2C Configuration
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_DAVINCI_I2C_SPEED		25000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE   10 /* Bogus, master-only in U-Boot */
#define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20

/*
 * Flash & Environment
 */
#ifdef CONFIG_USE_NAND
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
#define CONFIG_ENV_OFFSET		0x0 /* Block 0--not used by bootcode */
#define CONFIG_ENV_SIZE			(128 << 10)
#define	CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define	CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_SYS_NAND_CS		3
#define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
#define CONFIG_SYS_NAND_MASK_CLE		0x10
#define CONFIG_SYS_NAND_MASK_ALE		0x8
#undef CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE	(2 << 10)
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x28000
#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x60000
#define CONFIG_SYS_NAND_U_BOOT_DST	0xc1080000
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	(CONFIG_SYS_NAND_U_BOOT_DST - \
					CONFIG_SYS_NAND_U_BOOT_SIZE - \
					CONFIG_SYS_MALLOC_LEN -       \
					GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_NAND_ECCPOS		{				\
				24, 25, 26, 27, 28, \
				29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
				39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
				49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
				59, 60, 61, 62, 63 }
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	10
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_NAND_LOAD
#endif

/*
 * Network & Ethernet Configuration
 */
#ifdef CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT	10
#endif

#ifdef CONFIG_USE_NOR
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* max number of flash banks */
#define CONFIG_SYS_FLASH_SECT_SZ	(128 << 10) /* 128KB */
#define CONFIG_ENV_OFFSET		(CONFIG_SYS_FLASH_SECT_SZ * 3)
#define CONFIG_ENV_SIZE			(10 << 10) /* 10KB */
#define CONFIG_SYS_FLASH_BASE		DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
#define PHYS_FLASH_SIZE			(8 << 20) /* Flash size 8MB */
#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
	       + 3)
#define CONFIG_ENV_SECT_SIZE		CONFIG_SYS_FLASH_SECT_SZ
#endif

#ifdef CONFIG_USE_SPIFLASH
#undef CONFIG_ENV_IS_IN_FLASH
#undef CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE			(64 << 10)
#define CONFIG_ENV_OFFSET		(512 << 10)
#define CONFIG_ENV_SECT_SIZE		(64 << 10)
#define CONFIG_SYS_NO_FLASH
#endif

/*
 * U-Boot general configuration
 */
#define CONFIG_MISC_INIT_R
#define CONFIG_BOOTFILE		"uImage" /* Boot file name */
#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS	16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
#define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC

/*
 * Linux Information
 */
#define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
#define CONFIG_HWCONFIG		/* enable hwconfig */
#define CONFIG_CMDLINE_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTARGS		\
	"mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
#define CONFIG_EXTRA_ENV_SETTINGS	"hwconfig=dsp:wake=yes"

/*
 * U-Boot commands
 */
#define CONFIG_CMD_ENV
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_SAVES

#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
#endif

#ifndef CONFIG_DRIVER_TI_EMAC
#endif

#ifdef CONFIG_USE_NAND
#define CONFIG_CMD_NAND

#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_LZO
#define CONFIG_RBTREE
#define CONFIG_CMD_UBIFS
#endif

#ifdef CONFIG_USE_SPIFLASH
#endif

#if !defined(CONFIG_USE_NAND) && \
	!defined(CONFIG_USE_NOR) && \
	!defined(CONFIG_USE_SPIFLASH)
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_SIZE		(16 << 10)
#undef CONFIG_CMD_ENV
#endif

#ifndef CONFIG_DIRECT_NOR_BOOT
/* defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE - \
						CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE	CONFIG_SYS_MALLOC_LEN
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_LDSCRIPT	"board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
#define CONFIG_SPL_STACK	0x8001ff00
#define CONFIG_SPL_TEXT_BASE	0x80000000
#define CONFIG_SPL_MAX_FOOTPRINT	32768
#define CONFIG_SPL_PAD_TO	32768
#endif

/* Load U-Boot Image From MMC */
#ifdef CONFIG_SPL_MMC_LOAD
#undef CONFIG_SPL_SPI_LOAD
#endif

/* additions for new relocation code, must added to all boards */
#define CONFIG_SYS_SDRAM_BASE		0xc0000000

#ifdef CONFIG_DIRECT_NOR_BOOT
#define CONFIG_SYS_INIT_SP_ADDR		0x8001ff00
#else
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
					GENERATED_GBL_DATA_SIZE)
#endif /* CONFIG_DIRECT_NOR_BOOT */
#endif /* __CONFIG_H */
Commit	Line	Data
89b765c7 SR	1	/*
	2	* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
	3	*
	4	* Based on davinci_dvevm.h. Original Copyrights follow:
	5	*
	6	* Copyright (C) 2007 Sergey Kubushyn <[email protected]>
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
89b765c7 SR	9	*/
	10
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
	14	/*
	15	* Board
	16	*/
3d248d37	17	#define CONFIG_DRIVER_TI_EMAC
63777665 LP	18	/* check if direct NOR boot config is used */
63777665 LP	19	#ifndef CONFIG_DIRECT_NOR_BOOT
d73a8a1b	20	#define CONFIG_USE_SPIFLASH
63777665	21	#endif
89b765c7 SR	22
	23	/*
	24	* SoC Configuration
	25	*/
	26	#define CONFIG_MACH_DAVINCI_DA850_EVM
89b765c7	27	#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
52b0f877	28	#define CONFIG_SOC_DA850 /* TI DA850 SoC */
b67d8816	29	#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
89b765c7 SR	30	#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
	31	#define CONFIG_SYS_OSCIN_FREQ 24000000
	32	#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
	33	#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
89b765c7	34
63777665 LP	35	#ifdef CONFIG_DIRECT_NOR_BOOT
	36	#define CONFIG_ARCH_CPU_INIT
	37	#define CONFIG_DA8XX_GPIO
	38	#define CONFIG_SYS_TEXT_BASE 0x60000000
	39	#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
	40	#define CONFIG_DA850_LOWLEVEL
	41	#else
	42	#define CONFIG_SYS_TEXT_BASE 0xc1080000
	43	#endif
	44
89b765c7 SR	45	/*
	46	* Memory Info
	47	*/
	48	#define CONFIG_SYS_MALLOC_LEN (0x10000 + 110241024) /* malloc() len */
89b765c7 SR	49	#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
89b765c7 SR	50	#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
97003756	51	#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
89b765c7 SR	52
	53	/* memtest start addr */
	54	#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
	55
	56	/* memtest will be run on 16MB */
	57	#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 1610241024)
	58
	59	#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
89b765c7	60
3d2c8e6c CR	61	#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
	62	DAVINCI_SYSCFG_SUSPSRC_TIMER0 \| \
	63	DAVINCI_SYSCFG_SUSPSRC_SPI1 \| \
	64	DAVINCI_SYSCFG_SUSPSRC_UART2 \| \
	65	DAVINCI_SYSCFG_SUSPSRC_EMAC \| \
	66	DAVINCI_SYSCFG_SUSPSRC_I2C)
	67
	68	/*
	69	* PLL configuration
	70	*/
	71	#define CONFIG_SYS_DV_CLKMODE 0
	72	#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
	73	#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
	74	#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
	75	#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
	76	#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
	77	#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
	78	#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
	79	#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
	80
	81	#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
	82	#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
	83	#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
	84	#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
	85
	86	#define CONFIG_SYS_DA850_PLL0_PLLM 24
	87	#define CONFIG_SYS_DA850_PLL1_PLLM 21
	88
	89	/*
	90	* DDR2 memory configuration
	91	*/
	92	#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN \| \
	93	DV_DDR_PHY_EXT_STRBEN \| \
	94	(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
	95
	96	#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
	97	(1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) \| \
	98	(1 << DV_DDR_SDCR_DDREN_SHIFT) \| \
	99	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) \| \
	100	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) \| \
	101	(0x3 << DV_DDR_SDCR_CL_SHIFT) \| \
	102	(0x2 << DV_DDR_SDCR_IBANK_SHIFT) \| \
	103	(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
	104
	105	/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
	106	#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
	107
	108	#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
	109	(14 << DV_DDR_SDTMR1_RFC_SHIFT) \| \
	110	(2 << DV_DDR_SDTMR1_RP_SHIFT) \| \
	111	(2 << DV_DDR_SDTMR1_RCD_SHIFT) \| \
	112	(1 << DV_DDR_SDTMR1_WR_SHIFT) \| \
	113	(5 << DV_DDR_SDTMR1_RAS_SHIFT) \| \
	114	(8 << DV_DDR_SDTMR1_RC_SHIFT) \| \
	115	(1 << DV_DDR_SDTMR1_RRD_SHIFT) \| \
	116	(0 << DV_DDR_SDTMR1_WTR_SHIFT))
	117
	118	#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
	119	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) \| \
	120	(0 << DV_DDR_SDTMR2_XP_SHIFT) \| \
	121	(0 << DV_DDR_SDTMR2_ODT_SHIFT) \| \
	122	(17 << DV_DDR_SDTMR2_XSNR_SHIFT) \| \
	123	(199 << DV_DDR_SDTMR2_XSRD_SHIFT) \| \
	124	(0 << DV_DDR_SDTMR2_RTP_SHIFT) \| \
125	(0 << DV_DDR_SDTMR2_CKE_SHIFT))
126
127	#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
128	#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
129
89b765c7 SR	130	/*
	131	* Serial Driver info
	132	*/
89b765c7 SR	133	#define CONFIG_SYS_NS16550_SERIAL
	134	#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
	135	#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
	136	#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
	137	#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
	138	#define CONFIG_BAUDRATE 115200 /* Default baud rate */
89b765c7	139
d73a8a1b	140	#define CONFIG_SPI
d73a8a1b SB	141	#define CONFIG_DAVINCI_SPI
	142	#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
	143	#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
	144	#define CONFIG_SF_DEFAULT_SPEED 30000000
	145	#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
	146
42612104	147	#ifdef CONFIG_USE_SPIFLASH
42612104	148	#define CONFIG_SPL_SPI_LOAD
42612104	149	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
2a10f8b9	150	#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
42612104 LP	151	#endif
42612104 LP	152
89b765c7 SR	153	/*
	154	* I2C Configuration
	155	*/
e8459dcc VA	156	#define CONFIG_SYS_I2C
	157	#define CONFIG_SYS_I2C_DAVINCI
	158	#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000
	159	#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
d2607401	160	#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
89b765c7	161
6b2c6468 BG	162	/*
	163	* Flash & Environment
	164	*/
	165	#ifdef CONFIG_USE_NAND
	166	#undef CONFIG_ENV_IS_IN_FLASH
	167	#define CONFIG_NAND_DAVINCI
	168	#define CONFIG_SYS_NO_FLASH
	169	#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
	170	#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
	171	#define CONFIG_ENV_SIZE (128 << 10)
	172	#define CONFIG_SYS_NAND_USE_FLASH_BBT
	173	#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
	174	#define CONFIG_SYS_NAND_PAGE_2K
	175	#define CONFIG_SYS_NAND_CS 3
	176	#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
34fa0706 EB	177	#define CONFIG_SYS_NAND_MASK_CLE 0x10
34fa0706 EB	178	#define CONFIG_SYS_NAND_MASK_ALE 0x8
6b2c6468 BG	179	#undef CONFIG_SYS_NAND_HW_ECC
6b2c6468 BG	180	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
122f9c9b LP	181	#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
	182	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	183	#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
	184	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
	185	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x28000
	186	#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
	187	#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
	188	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
	189	#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
	190	CONFIG_SYS_NAND_U_BOOT_SIZE - \
	191	CONFIG_SYS_MALLOC_LEN - \
	192	GENERATED_GBL_DATA_SIZE)
	193	#define CONFIG_SYS_NAND_ECCPOS { \
	194	24, 25, 26, 27, 28, \
	195	29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
	196	39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
	197	49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
	198	59, 60, 61, 62, 63 }
	199	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	200	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	201	#define CONFIG_SYS_NAND_ECCSIZE 512
	202	#define CONFIG_SYS_NAND_ECCBYTES 10
	203	#define CONFIG_SYS_NAND_OOBSIZE 64
6f2f01b9 SW	204	#define CONFIG_SPL_NAND_BASE
	205	#define CONFIG_SPL_NAND_DRIVERS
	206	#define CONFIG_SPL_NAND_ECC
122f9c9b LP	207	#define CONFIG_SPL_NAND_SIMPLE
122f9c9b LP	208	#define CONFIG_SPL_NAND_LOAD
6b2c6468 BG	209	#endif
6b2c6468 BG	210
3d248d37 BG	211	/*
	212	* Network & Ethernet Configuration
	213	*/
	214	#ifdef CONFIG_DRIVER_TI_EMAC
3d248d37	215	#define CONFIG_MII
3d248d37 BG	216	#define CONFIG_BOOTP_DNS
	217	#define CONFIG_BOOTP_DNS2
	218	#define CONFIG_BOOTP_SEND_HOSTNAME
	219	#define CONFIG_NET_RETRY_COUNT 10
3d248d37 BG	220	#endif
3d248d37 BG	221
1506b0a8 NN	222	#ifdef CONFIG_USE_NOR
	223	#define CONFIG_ENV_IS_IN_FLASH
	224	#define CONFIG_FLASH_CFI_DRIVER
	225	#define CONFIG_SYS_FLASH_CFI
	226	#define CONFIG_SYS_FLASH_PROTECTION
	227	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
	228	#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
	229	#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
	230	#define CONFIG_ENV_SIZE (10 << 10) /* 10KB */
	231	#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
	232	#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
	233	#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
	234	+ 3)
	235	#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
	236	#endif
	237
d73a8a1b SB	238	#ifdef CONFIG_USE_SPIFLASH
	239	#undef CONFIG_ENV_IS_IN_FLASH
	240	#undef CONFIG_ENV_IS_IN_NAND
	241	#define CONFIG_ENV_IS_IN_SPI_FLASH
	242	#define CONFIG_ENV_SIZE (64 << 10)
2a10f8b9	243	#define CONFIG_ENV_OFFSET (512 << 10)
d73a8a1b SB	244	#define CONFIG_ENV_SECT_SIZE (64 << 10)
	245	#define CONFIG_SYS_NO_FLASH
	246	#endif
	247
89b765c7 SR	248	/*
	249	* U-Boot general configuration
	250	*/
cf2c24e3	251	#define CONFIG_MISC_INIT_R
89b765c7	252	#define CONFIG_BOOTFILE "uImage" /* Boot file name */
89b765c7 SR	253	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	254	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
	255	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	256	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
	257	#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
89b765c7	258	#define CONFIG_AUTO_COMPLETE
89b765c7 SR	259	#define CONFIG_CMDLINE_EDITING
	260	#define CONFIG_SYS_LONGHELP
	261	#define CONFIG_CRC32_VERIFY
	262	#define CONFIG_MX_CYCLIC
	263
	264	/*
	265	* Linux Information
	266	*/
59e0d611	267	#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
cf2c24e3	268	#define CONFIG_HWCONFIG /* enable hwconfig */
89b765c7	269	#define CONFIG_CMDLINE_TAG
4f6fc15b	270	#define CONFIG_REVISION_TAG
89b765c7 SR	271	#define CONFIG_SETUP_MEMORY_TAGS
	272	#define CONFIG_BOOTARGS \
	273	"mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
cf2c24e3	274	#define CONFIG_EXTRA_ENV_SETTINGS "hwconfig=dsp:wake=yes"
89b765c7 SR	275
	276	/*
	277	* U-Boot commands
	278	*/
89b765c7	279	#define CONFIG_CMD_ENV
89b765c7	280	#define CONFIG_CMD_DIAG
89b765c7	281	#define CONFIG_CMD_SAVES
89b765c7	282
8f5d4687 HM	283	#ifdef CONFIG_CMD_BDI
	284	#define CONFIG_CLOCKS
	285	#endif
	286
89b765c7	287	#ifndef CONFIG_DRIVER_TI_EMAC
89b765c7 SR	288	#endif
89b765c7 SR	289
6b2c6468	290	#ifdef CONFIG_USE_NAND
6b2c6468	291	#define CONFIG_CMD_NAND
771d028a BG	292
	293	#define CONFIG_CMD_MTDPARTS
	294	#define CONFIG_MTD_DEVICE
	295	#define CONFIG_MTD_PARTITIONS
	296	#define CONFIG_LZO
	297	#define CONFIG_RBTREE
771d028a	298	#define CONFIG_CMD_UBIFS
6b2c6468 BG	299	#endif
6b2c6468 BG	300
d73a8a1b	301	#ifdef CONFIG_USE_SPIFLASH
d73a8a1b SB	302	#endif
d73a8a1b SB	303
89b765c7 SR	304	#if !defined(CONFIG_USE_NAND) && \
	305	!defined(CONFIG_USE_NOR) && \
	306	!defined(CONFIG_USE_SPIFLASH)
	307	#define CONFIG_ENV_IS_NOWHERE
	308	#define CONFIG_SYS_NO_FLASH
	309	#define CONFIG_ENV_SIZE (16 << 10)
89b765c7 SR	310	#undef CONFIG_CMD_ENV
	311	#endif
	312
63777665	313	#ifndef CONFIG_DIRECT_NOR_BOOT
3d2c8e6c	314	/* defines for SPL */
3f7f2414 TR	315	#define CONFIG_SPL_FRAMEWORK
	316	#define CONFIG_SPL_BOARD_INIT
	317	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
	318	CONFIG_SYS_MALLOC_LEN)
	319	#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
3f7f2414	320	#define CONFIG_SPL_SPI_LOAD
6b873dca	321	#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
3d2c8e6c CR	322	#define CONFIG_SPL_STACK 0x8001ff00
3d2c8e6c CR	323	#define CONFIG_SPL_TEXT_BASE 0x80000000
b7b5f1a1	324	#define CONFIG_SPL_MAX_FOOTPRINT 32768
532d5318	325	#define CONFIG_SPL_PAD_TO 32768
63777665	326	#endif
0d986e61 LP	327
	328	/* Load U-Boot Image From MMC */
	329	#ifdef CONFIG_SPL_MMC_LOAD
0d986e61 LP	330	#undef CONFIG_SPL_SPI_LOAD
	331	#endif
	332
ab86f72c	333	/* additions for new relocation code, must added to all boards */
ab86f72c	334	#define CONFIG_SYS_SDRAM_BASE 0xc0000000
63777665 LP	335
	336	#ifdef CONFIG_DIRECT_NOR_BOOT
	337	#define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00
	338	#else
ab86f72c	339	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
25ddd1fb	340	GENERATED_GBL_DATA_SIZE)
63777665	341	#endif /* CONFIG_DIRECT_NOR_BOOT */
89b765c7	342	#endif /* __CONFIG_H */