[J-u-boot.git] / drivers / cache / Kconfig

#
# Cache controllers
#

menu "Cache Controller drivers"

config CACHE
	bool "Enable Driver Model for Cache controllers"
	depends on DM
	help
	  Enable driver model for cache controllers that are found on
	  most CPU's. Cache is memory that the CPU can access directly and
	  is usually located on the same chip. This uclass can be used for
	  configuring settings that be found from a device tree file.

config L2X0_CACHE
	tristate "PL310 cache driver"
	select CACHE
	depends on ARM
	help
	  This driver is for the PL310 cache controller commonly found on
	  ARMv7(32-bit) devices. The driver configures the cache settings
	  found in the device tree.

config ANDES_L2_CACHE
	bool "Andes L2 cache driver"
	select CACHE
	help
	  Support Andes L2 cache controller in AE350 platform.
	  It will configure tag and data ram timing control from the
	  device tree and enable L2 cache.

config NCORE_CACHE
	bool "Arteris Ncore cache coherent unit driver"
	select CACHE
	help
	  This driver is for the Arteris Ncore cache coherent unit (CCU)
	  controller. The driver initializes cache directories and coherent
	  agent interfaces.

config SIFIVE_CCACHE
	bool "SiFive composable cache"
	select CACHE
	help
	  This driver is for SiFive Composable L2/L3 cache. It enables cache
	  ways of composable cache.

config SIFIVE_PL2
	bool "SiFive private L2 cache"
	select CACHE
	help
	  This driver is for SiFive Private L2 cache. It configures registers
	  to enable the clock gating feature.

endmenu
Commit	Line	Data
84b124db DN	1	#
	2	# Cache controllers
	3	#
	4
	5	menu "Cache Controller drivers"
	6
	7	config CACHE
	8	bool "Enable Driver Model for Cache controllers"
	9	depends on DM
	10	help
	11	Enable driver model for cache controllers that are found on
	12	most CPU's. Cache is memory that the CPU can access directly and
	13	is usually located on the same chip. This uclass can be used for
	14	configuring settings that be found from a device tree file.
	15
88ebf583 DN	16	config L2X0_CACHE
	17	tristate "PL310 cache driver"
	18	select CACHE
	19	depends on ARM
	20	help
	21	This driver is for the PL310 cache controller commonly found on
	22	ARMv7(32-bit) devices. The driver configures the cache settings
	23	found in the device tree.
	24
2b8dc36b LYCL	25	config ANDES_L2_CACHE
2b8dc36b LYCL	26	bool "Andes L2 cache driver"
4fa4267d	27	select CACHE
4fa4267d	28	help
2b8dc36b	29	Support Andes L2 cache controller in AE350 platform.
4fa4267d RC	30	It will configure tag and data ram timing control from the
	31	device tree and enable L2 cache.
	32
fec7ddc1 LFT	33	config NCORE_CACHE
	34	bool "Arteris Ncore cache coherent unit driver"
	35	select CACHE
	36	help
	37	This driver is for the Arteris Ncore cache coherent unit (CCU)
	38	controller. The driver initializes cache directories and coherent
	39	agent interfaces.
	40
43a21839 ZL	41	config SIFIVE_CCACHE
	42	bool "SiFive composable cache"
	43	select CACHE
	44	help
	45	This driver is for SiFive Composable L2/L3 cache. It enables cache
	46	ways of composable cache.
	47
64e8482f ZL	48	config SIFIVE_PL2
	49	bool "SiFive private L2 cache"
	50	select CACHE
	51	help
	52	This driver is for SiFive Private L2 cache. It configures registers
	53	to enable the clock gating feature.
	54
84b124db	55	endmenu