]> Git Repo - J-u-boot.git/blame - drivers/serial/serial_xuartlite.c
dm: treewide: Rename dev_get_platdata() to dev_get_plat()
[J-u-boot.git] / drivers / serial / serial_xuartlite.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
507bbe3e 2/*
93768393 3 * (C) Copyright 2008 - 2015 Michal Simek <[email protected]>
53ea981c 4 * Clean driver and add xilinx constant from header file
507bbe3e 5 *
53ea981c 6 * (C) Copyright 2004 Atmark Techno, Inc.
507bbe3e 7 * Yasushi SHOJI <[email protected]>
507bbe3e
WD
8 */
9
10#include <config.h>
49a23e4a 11#include <common.h>
93768393 12#include <dm.h>
53ea981c 13#include <asm/io.h>
cd93d625 14#include <linux/bitops.h>
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15#include <linux/compiler.h>
16#include <serial.h>
507bbe3e 17
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18#define SR_TX_FIFO_FULL BIT(3) /* transmit FIFO full */
19#define SR_TX_FIFO_EMPTY BIT(2) /* transmit FIFO empty */
20#define SR_RX_FIFO_VALID_DATA BIT(0) /* data in receive FIFO */
21#define SR_RX_FIFO_FULL BIT(1) /* receive FIFO full */
507bbe3e 22
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23#define ULITE_CONTROL_RST_TX 0x01
24#define ULITE_CONTROL_RST_RX 0x02
25
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26static bool little_endian;
27
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28struct uartlite {
29 unsigned int rx_fifo;
30 unsigned int tx_fifo;
31 unsigned int status;
8c3bd6b5 32 unsigned int control;
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33};
34
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35struct uartlite_platdata {
36 struct uartlite *regs;
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37};
38
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39static u32 uart_in32(void __iomem *addr)
40{
41 if (little_endian)
42 return in_le32(addr);
43 else
44 return in_be32(addr);
45}
46
47static void uart_out32(void __iomem *addr, u32 val)
48{
49 if (little_endian)
50 out_le32(addr, val);
51 else
52 out_be32(addr, val);
53}
54
93768393 55static int uartlite_serial_putc(struct udevice *dev, const char ch)
49a23e4a 56{
c69cda25 57 struct uartlite_platdata *plat = dev_get_plat(dev);
93768393 58 struct uartlite *regs = plat->regs;
49a23e4a 59
31a359f8 60 if (uart_in32(&regs->status) & SR_TX_FIFO_FULL)
93768393 61 return -EAGAIN;
49a23e4a 62
31a359f8 63 uart_out32(&regs->tx_fifo, ch & 0xff);
49a23e4a 64
93768393 65 return 0;
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66}
67
93768393 68static int uartlite_serial_getc(struct udevice *dev)
49a23e4a 69{
c69cda25 70 struct uartlite_platdata *plat = dev_get_plat(dev);
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71 struct uartlite *regs = plat->regs;
72
31a359f8 73 if (!(uart_in32(&regs->status) & SR_RX_FIFO_VALID_DATA))
93768393 74 return -EAGAIN;
49a23e4a 75
31a359f8 76 return uart_in32(&regs->rx_fifo) & 0xff;
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77}
78
93768393 79static int uartlite_serial_pending(struct udevice *dev, bool input)
49a23e4a 80{
c69cda25 81 struct uartlite_platdata *plat = dev_get_plat(dev);
93768393 82 struct uartlite *regs = plat->regs;
507bbe3e 83
93768393 84 if (input)
31a359f8 85 return uart_in32(&regs->status) & SR_RX_FIFO_VALID_DATA;
93768393 86
31a359f8 87 return !(uart_in32(&regs->status) & SR_TX_FIFO_EMPTY);
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88}
89
93768393 90static int uartlite_serial_probe(struct udevice *dev)
25239e12 91{
c69cda25 92 struct uartlite_platdata *plat = dev_get_plat(dev);
93768393 93 struct uartlite *regs = plat->regs;
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94 int ret;
95
96 uart_out32(&regs->control, 0);
97 uart_out32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
98 ret = uart_in32(&regs->status);
99 /* Endianness detection */
100 if ((ret & SR_TX_FIFO_EMPTY) != SR_TX_FIFO_EMPTY) {
101 little_endian = true;
102 uart_out32(&regs->control, ULITE_CONTROL_RST_RX |
103 ULITE_CONTROL_RST_TX);
104 }
25239e12 105
93768393 106 return 0;
90bad891 107}
49a23e4a 108
93768393 109static int uartlite_serial_ofdata_to_platdata(struct udevice *dev)
49a23e4a 110{
c69cda25 111 struct uartlite_platdata *plat = dev_get_plat(dev);
87d69229 112
8613c8d8 113 plat->regs = dev_read_addr_ptr(dev);
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114
115 return 0;
87d69229 116}
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117
118static const struct dm_serial_ops uartlite_serial_ops = {
119 .putc = uartlite_serial_putc,
120 .pending = uartlite_serial_pending,
121 .getc = uartlite_serial_getc,
122};
123
124static const struct udevice_id uartlite_serial_ids[] = {
125 { .compatible = "xlnx,opb-uartlite-1.00.b", },
126 { .compatible = "xlnx,xps-uartlite-1.00.a" },
127 { }
128};
129
130U_BOOT_DRIVER(serial_uartlite) = {
131 .name = "serial_uartlite",
132 .id = UCLASS_SERIAL,
133 .of_match = uartlite_serial_ids,
134 .ofdata_to_platdata = uartlite_serial_ofdata_to_platdata,
caa4daa2 135 .plat_auto = sizeof(struct uartlite_platdata),
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136 .probe = uartlite_serial_probe,
137 .ops = &uartlite_serial_ops,
93768393 138};
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139
140#ifdef CONFIG_DEBUG_UART_UARTLITE
141
142#include <debug_uart.h>
143
144static inline void _debug_uart_init(void)
145{
146 struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
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147 int ret;
148
149 uart_out32(&regs->control, 0);
150 uart_out32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
151 uart_in32(&regs->status);
152 /* Endianness detection */
153 if ((ret & SR_TX_FIFO_EMPTY) != SR_TX_FIFO_EMPTY) {
154 little_endian = true;
155 uart_out32(&regs->control, ULITE_CONTROL_RST_RX |
156 ULITE_CONTROL_RST_TX);
157 }
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158}
159
160static inline void _debug_uart_putc(int ch)
161{
162 struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
163
31a359f8 164 while (uart_in32(&regs->status) & SR_TX_FIFO_FULL)
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165 ;
166
31a359f8 167 uart_out32(&regs->tx_fifo, ch & 0xff);
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168}
169
170DEBUG_UART_FUNCS
171#endif
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