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ColdFire 5329: Assign correct SDRAM size and fix cache
[J-u-boot.git] / cpu / ppc4xx / 440spe_pcie.c
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692519b1 1/*
c9240981 2 * (C) Copyright 2006 - 2007
692519b1
RJ		 3 * Wolfgang Denk, DENX Software Engineering, [email protected].
4 *
5 * Copyright (c) 2005 Cisco Systems. All rights reserved.
6 * Roland Dreier <[email protected]>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 */
22
23#include <asm/processor.h>
24#include <asm-ppc/io.h>
25#include <ppc4xx.h>
26#include <common.h>
27#include <pci.h>
28
5fb692ca 29#if defined(CONFIG_440SPE) && defined(CONFIG_PCI)
692519b1 30
5fb692ca 31#include "440spe_pcie.h"
692519b1
RJ		 32
33enum {
34 PTYPE_ENDPOINT = 0x0,
35 PTYPE_LEGACY_ENDPOINT = 0x1,
36 PTYPE_ROOT_PORT = 0x4,
37
38 LNKW_X1 = 0x1,
39 LNKW_X4 = 0x4,
40 LNKW_X8 = 0x8
41};
42
7f191393
GB		 43static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
44{
45 u8 *base = (u8*)hose->cfg_data;
46
47 /* use local configuration space for the first bus */
48 if (PCI_BUS(devfn) == 0) {
49 if (hose->cfg_data == (u8*)CFG_PCIE0_CFGBASE)
50 base = (u8*)CFG_PCIE0_XCFGBASE;
51 if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE)
52 base = (u8*)CFG_PCIE1_XCFGBASE;
53 if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE)
54 base = (u8*)CFG_PCIE2_XCFGBASE;
55 }
56
57 return base;
58}
59
15ee4734 60static void pcie_dmer_disable(void)
c9240981 61{
15ee4734
GB		 62 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE),
63 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA);
64 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE),
65 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA);
66 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE),
67 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA);
c9240981
GB		 68}
69
15ee4734 70static void pcie_dmer_enable(void)
c9240981 71{
15ee4734
GB		 72 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE),
73 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA);
74 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE),
75 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA);
76 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE),
77 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA);
c9240981
GB		 78}
79
692519b1
RJ		 80static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
81 int offset, int len, u32 *val) {
82
7f191393 83 u8 *address;
692519b1 84 *val = 0;
7f191393
GB		 85
86 /*
87 * Bus numbers are relative to hose->first_busno
88 */
89 devfn -= PCI_BDF(hose->first_busno, 0, 0);
90
692519b1 91 /*
7f191393
GB		 92 * NOTICE: configuration space ranges are currenlty mapped only for
93 * the first 16 buses, so such limit must be imposed. In case more
94 * buses are required the TLB settings in board/amcc/<board>/init.S
95 * need to be altered accordingly (one bus takes 1 MB of memory space).
692519b1 96 */
7f191393 97 if (PCI_BUS(devfn) >= 16)
692519b1
RJ		 98 return 0;
99
7f191393
GB		 100 /*
101 * Only single device/single function is supported for the primary and
102 * secondary buses of the 440SPe host bridge.
103 */
104 if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
105 ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
106 return 0;
738815c0 107
7f191393 108 address = pcie_get_base(hose, devfn);
692519b1
RJ		 109 offset += devfn << 4;
110
15ee4734
GB		 111 /*
112 * Reading from configuration space of non-existing device can
113 * generate transaction errors. For the read duration we suppress
114 * assertion of machine check exceptions to avoid those.
115 */
116 pcie_dmer_disable ();
117
692519b1
RJ		 118 switch (len) {
119 case 1:
15ee4734 120 *val = in_8(hose->cfg_data + offset);
692519b1
RJ		 121 break;
122 case 2:
15ee4734 123 *val = in_le16((u16 *)(hose->cfg_data + offset));
692519b1
RJ		 124 break;
125 default:
15ee4734 126 *val = in_le32((u32*)(hose->cfg_data + offset));
692519b1
RJ		 127 break;
128 }
15ee4734
GB		 129
130 pcie_dmer_enable ();
131
692519b1
RJ		 132 return 0;
133}
134
135static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
136 int offset, int len, u32 val) {
137
7f191393 138 u8 *address;
738815c0 139
692519b1 140 /*
7f191393 141 * Bus numbers are relative to hose->first_busno
692519b1 142 */
7f191393 143 devfn -= PCI_BDF(hose->first_busno, 0, 0);
738815c0 144
7f191393
GB		 145 /*
146 * Same constraints as in pcie_read_config().
147 */
148 if (PCI_BUS(devfn) >= 16)
692519b1
RJ		 149 return 0;
150
7f191393
GB		 151 if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
152 ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
153 return 0;
738815c0 154
7f191393 155 address = pcie_get_base(hose, devfn);
692519b1
RJ		 156 offset += devfn << 4;
157
15ee4734
GB		 158 /*
159 * Suppress MCK exceptions, similar to pcie_read_config()
160 */
161 pcie_dmer_disable ();
162
692519b1
RJ		 163 switch (len) {
164 case 1:
165 out_8(hose->cfg_data + offset, val);
166 break;
167 case 2:
168 out_le16((u16 *)(hose->cfg_data + offset), val);
169 break;
170 default:
171 out_le32((u32 *)(hose->cfg_data + offset), val);
172 break;
173 }
15ee4734
GB		 174
175 pcie_dmer_enable ();
176
692519b1
RJ		 177 return 0;
178}
179
180int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val)
181{
182 u32 v;
183 int rv;
184
7f191393 185 rv = pcie_read_config(hose, dev, offset, 1, &v);
692519b1
RJ		 186 *val = (u8)v;
187 return rv;
188}
189
190int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val)
191{
192 u32 v;
193 int rv;
194
195 rv = pcie_read_config(hose, dev, offset, 2, &v);
196 *val = (u16)v;
197 return rv;
198}
199
200int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val)
201{
202 u32 v;
203 int rv;
204
205 rv = pcie_read_config(hose, dev, offset, 3, &v);
206 *val = (u32)v;
207 return rv;
208}
209
210int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val)
211{
212 return pcie_write_config(hose,(u32)dev,offset,1,val);
213}
214
215int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val)
216{
217 return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val);
218}
219
220int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val)
221{
222 return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val);
223}
224
225static void ppc440spe_setup_utl(u32 port) {
226
227 volatile void *utl_base = NULL;
228
229 /*
230 * Map UTL registers
231 */
232 switch (port) {
233 case 0:
36b904a7
RJ		 234 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
235 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000);
236 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
692519b1 237 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
692519b1
RJ		 238 break;
239
240 case 1:
36b904a7
RJ		 241 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
242 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000);
243 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
692519b1 244 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
692519b1
RJ		 245 break;
246
247 case 2:
36b904a7
RJ		 248 mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
249 mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000);
250 mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
692519b1 251 mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
692519b1
RJ		 252 break;
253 }
36b904a7 254 utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);
16850919 255
692519b1
RJ		 256 /*
257 * Set buffer allocations and then assert VRB and TXE.
258 */
259 out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
260 out_be32(utl_base + PEUTL_INTR, 0x02000000);
261 out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000);
262 out_be32(utl_base + PEUTL_PBBSZ, 0x53000000);
263 out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
264 out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
265 out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
36b904a7 266 out_be32(utl_base + PEUTL_PCTL, 0x80800066);
692519b1
RJ		 267}
268
269static int check_error(void)
270{
271 u32 valPE0, valPE1, valPE2;
272 int err = 0;
273
274 /* SDR0_PEGPLLLCT1 reset */
275 if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) {
276 printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0);
277 }
278
279 valPE0 = SDR_READ(PESDR0_RCSSET);
280 valPE1 = SDR_READ(PESDR1_RCSSET);
281 valPE2 = SDR_READ(PESDR2_RCSSET);
282
283 /* SDR0_PExRCSSET rstgu */
284 if (!(valPE0 & 0x01000000) ||
285 !(valPE1 & 0x01000000) ||
286 !(valPE2 & 0x01000000)) {
287 printf("PCIE: SDR0_PExRCSSET rstgu error\n");
288 err = -1;
289 }
290
291 /* SDR0_PExRCSSET rstdl */
292 if (!(valPE0 & 0x00010000) ||
293 !(valPE1 & 0x00010000) ||
294 !(valPE2 & 0x00010000)) {
295 printf("PCIE: SDR0_PExRCSSET rstdl error\n");
296 err = -1;
297 }
298
299 /* SDR0_PExRCSSET rstpyn */
300 if ((valPE0 & 0x00001000) ||
301 (valPE1 & 0x00001000) ||
302 (valPE2 & 0x00001000)) {
303 printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
304 err = -1;
305 }
306
307 /* SDR0_PExRCSSET hldplb */
308 if ((valPE0 & 0x10000000) ||
309 (valPE1 & 0x10000000) ||
310 (valPE2 & 0x10000000)) {
311 printf("PCIE: SDR0_PExRCSSET hldplb error\n");
312 err = -1;
313 }
314
315 /* SDR0_PExRCSSET rdy */
316 if ((valPE0 & 0x00100000) ||
317 (valPE1 & 0x00100000) ||
318 (valPE2 & 0x00100000)) {
319 printf("PCIE: SDR0_PExRCSSET rdy error\n");
320 err = -1;
321 }
322
323 /* SDR0_PExRCSSET shutdown */
324 if ((valPE0 & 0x00000100) ||
325 (valPE1 & 0x00000100) ||
326 (valPE2 & 0x00000100)) {
327 printf("PCIE: SDR0_PExRCSSET shutdown error\n");
328 err = -1;
329 }
330 return err;
331}
332
333/*
334 * Initialize PCI Express core
335 */
336int ppc440spe_init_pcie(void)
337{
338 int time_out = 20;
339
340 /* Set PLL clock receiver to LVPECL */
341 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
342
343 if (check_error())
344 return -1;
345
346 if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
347 {
348 printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
349 SDR_READ(PESDR0_PLLLCT2));
350 return -1;
351 }
352 /* De-assert reset of PCIe PLL, wait for lock */
353 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
354 udelay(3);
355
2b393b0f 356 while (time_out) {
692519b1
RJ		 357 if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
358 time_out--;
359 udelay(1);
360 } else
361 break;
362 }
363 if (!time_out) {
364 printf("PCIE: VCO output not locked\n");
365 return -1;
366 }
367 return 0;
368}
369
2b393b0f
SR		 370/*
371 * Yucca board as End point and root point setup
372 * and
373 * testing inbound and out bound windows
374 *
375 * YUCCA board can be plugged into another yucca board or you can get PCI-E
376 * cable which can be used to setup loop back from one port to another port.
377 * Please rememeber that unless there is a endpoint plugged in to root port it
378 * will not initialize. It is the same in case of endpoint , unless there is
379 * root port attached it will not initialize.
380 *
381 * In this release of software all the PCI-E ports are configured as either
382 * endpoint or rootpoint.In future we will have support for selective ports
383 * setup as endpoint and root point in single board.
384 *
385 * Once your board came up as root point , you can verify by reading
386 * /proc/bus/pci/devices. Where you can see the configuration registers
387 * of end point device attached to the port.
388 *
389 * Enpoint cofiguration can be verified by connecting Yucca board to any
390 * host or another yucca board. Then try to scan the device. In case of
391 * linux use "lspci" or appripriate os command.
392 *
393 * How do I verify the inbound and out bound windows ?(yucca to yucca)
394 * in this configuration inbound and outbound windows are setup to access
395 * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address
396 * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000,
397 * This is waere your POM(PLB out bound memory window) mapped. then
398 * read the data from other yucca board's u-boot prompt at address
399 * 0x9000 0000(SRAM). Data should match.
400 * In case of inbound , write data to u-boot command prompt at 0xb000 0000
401 * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check
402 * data at 0x9000 0000(SRAM).Data should match.
403 */
692519b1
RJ		 404int ppc440spe_init_pcie_rootport(int port)
405{
406 static int core_init;
407 volatile u32 val = 0;
408 int attempts;
409
410 if (!core_init) {
411 ++core_init;
412 if (ppc440spe_init_pcie())
413 return -1;
414 }
415
416 /*
417 * Initialize various parts of the PCI Express core for our port:
418 *
419 * - Set as a root port and enable max width
420 * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
421 * - Set up UTL configuration.
422 * - Increase SERDES drive strength to levels suggested by AMCC.
423 * - De-assert RSTPYN, RSTDL and RSTGU.
424 *
425 * NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with
426 * default setting 0x11310000. The register has new fields,
427 * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
428 * hang.
429 */
430 switch (port) {
431 case 0:
432 SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X8 << 12);
433
434 SDR_WRITE(PESDR0_UTLSET1, 0x21222222);
435 if (!ppc440spe_revB())
436 SDR_WRITE(PESDR0_UTLSET2, 0x11000000);
437 SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000);
438 SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000);
439 SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000);
440 SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000);
441 SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
442 SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
443 SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
444 SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
445 SDR_WRITE(PESDR0_RCSSET,
2b393b0f 446 (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
692519b1
RJ		 447 break;
448
449 case 1:
450 SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
451 SDR_WRITE(PESDR1_UTLSET1, 0x21222222);
452 if (!ppc440spe_revB())
453 SDR_WRITE(PESDR1_UTLSET2, 0x11000000);
454 SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000);
455 SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000);
456 SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000);
457 SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000);
458 SDR_WRITE(PESDR1_RCSSET,
2b393b0f 459 (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
692519b1
RJ		 460 break;
461
462 case 2:
463 SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
464 SDR_WRITE(PESDR2_UTLSET1, 0x21222222);
465 if (!ppc440spe_revB())
466 SDR_WRITE(PESDR2_UTLSET2, 0x11000000);
467 SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000);
468 SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000);
469 SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000);
470 SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000);
2b393b0f
SR		 471 SDR_WRITE(PESDR2_RCSSET,
472 (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
473 break;
474 }
475 /*
476 * Notice: the following delay has critical impact on device
477 * initialization - if too short (<50ms) the link doesn't get up.
478 */
479 mdelay(100);
480
481 switch (port) {
482 case 0:
483 val = SDR_READ(PESDR0_RCSSTS);
484 break;
485 case 1:
486 val = SDR_READ(PESDR1_RCSSTS);
487 break;
488 case 2:
489 val = SDR_READ(PESDR2_RCSSTS);
490 break;
491 }
492
493 if (val & (1 << 20)) {
494 printf("PCIE%d: PGRST failed %08x\n", port, val);
495 return -1;
496 }
497
498 /*
499 * Verify link is up
500 */
501 val = 0;
502 switch (port) {
503 case 0:
504 val = SDR_READ(PESDR0_LOOP);
505 break;
506 case 1:
507 val = SDR_READ(PESDR1_LOOP);
508 break;
509 case 2:
510 val = SDR_READ(PESDR2_LOOP);
511 break;
512 }
513 if (!(val & 0x00001000)) {
514 printf("PCIE%d: link is not up.\n", port);
515 return -1;
516 }
517
518 /*
519 * Setup UTL registers - but only on revA!
520 * We use default settings for revB chip.
521 */
522 if (!ppc440spe_revB())
523 ppc440spe_setup_utl(port);
524
525 /*
526 * We map PCI Express configuration access into the 512MB regions
527 *
528 * NOTICE: revB is very strict about PLB real addressess and ranges to
529 * be mapped for config space; it seems to only work with d_nnnn_nnnn
530 * range (hangs the core upon config transaction attempts when set
531 * otherwise) while revA uses c_nnnn_nnnn.
532 *
533 * For revA:
534 * PCIE0: 0xc_4000_0000
535 * PCIE1: 0xc_8000_0000
536 * PCIE2: 0xc_c000_0000
537 *
538 * For revB:
539 * PCIE0: 0xd_0000_0000
540 * PCIE1: 0xd_2000_0000
541 * PCIE2: 0xd_4000_0000
542 */
543
544 switch (port) {
545 case 0:
546 if (ppc440spe_revB()) {
547 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d);
548 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000);
549 } else {
550 /* revA */
551 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c);
552 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000);
553 }
554 mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
555 break;
556
557 case 1:
558 if (ppc440spe_revB()) {
559 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d);
560 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000);
561 } else {
562 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c);
563 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000);
564 }
565 mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
566 break;
567
568 case 2:
569 if (ppc440spe_revB()) {
570 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d);
571 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000);
572 } else {
573 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c);
574 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000);
575 }
576 mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
577 break;
578 }
579
580 /*
581 * Check for VC0 active and assert RDY.
582 */
583 attempts = 10;
584 switch (port) {
585 case 0:
586 while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) {
587 if (!(attempts--)) {
588 printf("PCIE0: VC0 not active\n");
589 return -1;
590 }
591 mdelay(1000);
592 }
593 SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20);
594 break;
595 case 1:
596 while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) {
597 if (!(attempts--)) {
598 printf("PCIE1: VC0 not active\n");
599 return -1;
600 }
601 mdelay(1000);
602 }
603
604 SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20);
605 break;
606 case 2:
607 while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) {
608 if (!(attempts--)) {
609 printf("PCIE2: VC0 not active\n");
610 return -1;
611 }
612 mdelay(1000);
613 }
614
615 SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20);
616 break;
617 }
618 mdelay(100);
619
620 return 0;
621}
622
623int ppc440spe_init_pcie_endport(int port)
624{
625 static int core_init;
626 volatile u32 val = 0;
627 int attempts;
628
629 if (!core_init) {
630 ++core_init;
631 if (ppc440spe_init_pcie())
632 return -1;
633 }
634
635 /*
636 * Initialize various parts of the PCI Express core for our port:
637 *
638 * - Set as a end port and enable max width
639 * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
640 * - Set up UTL configuration.
641 * - Increase SERDES drive strength to levels suggested by AMCC.
642 * - De-assert RSTPYN, RSTDL and RSTGU.
643 *
644 * NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with
645 * default setting 0x11310000. The register has new fields,
646 * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
647 * hang.
648 */
649 switch (port) {
650 case 0:
651 SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X8 << 12);
652
653 SDR_WRITE(PESDR0_UTLSET1, 0x20222222);
654 if (!ppc440spe_revB())
655 SDR_WRITE(PESDR0_UTLSET2, 0x11000000);
656 SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000);
657 SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000);
658 SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000);
659 SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000);
660 SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
661 SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
662 SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
663 SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
664 SDR_WRITE(PESDR0_RCSSET,
665 (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
666 break;
667
668 case 1:
669 SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X4 << 12);
670 SDR_WRITE(PESDR1_UTLSET1, 0x20222222);
671 if (!ppc440spe_revB())
672 SDR_WRITE(PESDR1_UTLSET2, 0x11000000);
673 SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000);
674 SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000);
675 SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000);
676 SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000);
677 SDR_WRITE(PESDR1_RCSSET,
678 (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
679 break;
680
681 case 2:
682 SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X4 << 12);
683 SDR_WRITE(PESDR2_UTLSET1, 0x20222222);
684 if (!ppc440spe_revB())
685 SDR_WRITE(PESDR2_UTLSET2, 0x11000000);
686 SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000);
687 SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000);
688 SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000);
689 SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000);
692519b1
RJ		 690 SDR_WRITE(PESDR2_RCSSET,
691 (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
692 break;
693 }
694 /*
695 * Notice: the following delay has critical impact on device
696 * initialization - if too short (<50ms) the link doesn't get up.
697 */
698 mdelay(100);
699
700 switch (port) {
701 case 0: val = SDR_READ(PESDR0_RCSSTS); break;
702 case 1: val = SDR_READ(PESDR1_RCSSTS); break;
703 case 2: val = SDR_READ(PESDR2_RCSSTS); break;
704 }
705
706 if (val & (1 << 20)) {
707 printf("PCIE%d: PGRST failed %08x\n", port, val);
708 return -1;
709 }
710
711 /*
712 * Verify link is up
713 */
714 val = 0;
715 switch (port)
716 {
717 case 0:
718 val = SDR_READ(PESDR0_LOOP);
719 break;
720 case 1:
721 val = SDR_READ(PESDR1_LOOP);
722 break;
723 case 2:
724 val = SDR_READ(PESDR2_LOOP);
725 break;
726 }
727 if (!(val & 0x00001000)) {
728 printf("PCIE%d: link is not up.\n", port);
729 return -1;
730 }
731
732 /*
733 * Setup UTL registers - but only on revA!
734 * We use default settings for revB chip.
735 */
736 if (!ppc440spe_revB())
737 ppc440spe_setup_utl(port);
738
739 /*
740 * We map PCI Express configuration access into the 512MB regions
741 *
742 * NOTICE: revB is very strict about PLB real addressess and ranges to
743 * be mapped for config space; it seems to only work with d_nnnn_nnnn
744 * range (hangs the core upon config transaction attempts when set
745 * otherwise) while revA uses c_nnnn_nnnn.
746 *
747 * For revA:
748 * PCIE0: 0xc_4000_0000
749 * PCIE1: 0xc_8000_0000
750 * PCIE2: 0xc_c000_0000
751 *
752 * For revB:
753 * PCIE0: 0xd_0000_0000
754 * PCIE1: 0xd_2000_0000
755 * PCIE2: 0xd_4000_0000
756 */
757 switch (port) {
758 case 0:
759 if (ppc440spe_revB()) {
760 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d);
761 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000);
762 } else {
763 /* revA */
764 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c);
765 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000);
766 }
767 mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
768 break;
769
770 case 1:
771 if (ppc440spe_revB()) {
772 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d);
773 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000);
774 } else {
775 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c);
776 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000);
777 }
778 mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
779 break;
780
781 case 2:
782 if (ppc440spe_revB()) {
783 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d);
784 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000);
785 } else {
786 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c);
787 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000);
788 }
789 mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
790 break;
791 }
792
793 /*
794 * Check for VC0 active and assert RDY.
795 */
796 attempts = 10;
797 switch (port) {
798 case 0:
799 while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) {
800 if (!(attempts--)) {
801 printf("PCIE0: VC0 not active\n");
802 return -1;
803 }
804 mdelay(1000);
805 }
806 SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20);
807 break;
808 case 1:
809 while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) {
810 if (!(attempts--)) {
811 printf("PCIE1: VC0 not active\n");
812 return -1;
813 }
814 mdelay(1000);
815 }
816
817 SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20);
818 break;
819 case 2:
820 while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) {
821 if (!(attempts--)) {
822 printf("PCIE2: VC0 not active\n");
823 return -1;
824 }
825 mdelay(1000);
826 }
827
828 SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20);
829 break;
830 }
831 mdelay(100);
832
833 return 0;
834}
835
2b393b0f 836void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
692519b1
RJ		 837{
838 volatile void *mbase = NULL;
2b393b0f 839 volatile void *rmbase = NULL;
692519b1
RJ		 840
841 pci_set_ops(hose,
7f191393
GB		 842 pcie_read_config_byte,
843 pcie_read_config_word,
844 pcie_read_config_dword,
845 pcie_write_config_byte,
846 pcie_write_config_word,
847 pcie_write_config_dword);
2b393b0f
SR		 848
849 switch (port) {
692519b1
RJ		 850 case 0:
851 mbase = (u32 *)CFG_PCIE0_XCFGBASE;
2b393b0f 852 rmbase = (u32 *)CFG_PCIE0_CFGBASE;
692519b1
RJ		 853 hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
854 break;
855 case 1:
856 mbase = (u32 *)CFG_PCIE1_XCFGBASE;
2b393b0f 857 rmbase = (u32 *)CFG_PCIE1_CFGBASE;
692519b1
RJ		 858 hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
859 break;
860 case 2:
861 mbase = (u32 *)CFG_PCIE2_XCFGBASE;
2b393b0f 862 rmbase = (u32 *)CFG_PCIE2_CFGBASE;
692519b1
RJ		 863 hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
864 break;
865 }
866
867 /*
868 * Set bus numbers on our root port
869 */
7f191393
GB		 870 out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
871 out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
872 out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
692519b1
RJ		 873
874 /*
875 * Set up outbound translation to hose->mem_space from PLB
876 * addresses at an offset of 0xd_0000_0000. We set the low
877 * bits of the mask to 11 to turn off splitting into 8
878 * subregions and to enable the outbound translation.
879 */
880 out_le32(mbase + PECFG_POM0LAH, 0x00000000);
2b393b0f 881 out_le32(mbase + PECFG_POM0LAL, 0x00000000);
692519b1
RJ		 882
883 switch (port) {
884 case 0:
885 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
886 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
887 port * CFG_PCIE_MEMSIZE);
888 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
889 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
890 ~(CFG_PCIE_MEMSIZE - 1) | 3);
891 break;
892 case 1:
893 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
894 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE +
895 port * CFG_PCIE_MEMSIZE));
896 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
897 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
898 ~(CFG_PCIE_MEMSIZE - 1) | 3);
899 break;
900 case 2:
901 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
902 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE +
903 port * CFG_PCIE_MEMSIZE));
904 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
905 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
906 ~(CFG_PCIE_MEMSIZE - 1) | 3);
907 break;
908 }
909
910 /* Set up 16GB inbound memory window at 0 */
911 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
912 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
913 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
914 out_le32(mbase + PECFG_BAR0LMPA, 0);
2b393b0f
SR		 915
916 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
917 out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
692519b1
RJ		 918 out_le32(mbase + PECFG_PIM0LAL, 0);
919 out_le32(mbase + PECFG_PIM0LAH, 0);
2b393b0f
SR		 920 out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
921 out_le32(mbase + PECFG_PIM1LAH, 0x00000004);
922 out_le32(mbase + PECFG_PIMEN, 0x1);
923
924 /* Enable I/O, Mem, and Busmaster cycles */
925 out_le16((u16 *)(mbase + PCI_COMMAND),
926 in_le16((u16 *)(mbase + PCI_COMMAND)) |
927 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
928 printf("PCIE:%d successfully set as rootpoint\n",port);
738815c0 929
7f191393
GB		 930 /* Set Device and Vendor Id */
931 switch (port) {
932 case 0:
933 out_le16(mbase + 0x200, 0xaaa0);
934 out_le16(mbase + 0x202, 0xbed0);
935 break;
936 case 1:
937 out_le16(mbase + 0x200, 0xaaa1);
938 out_le16(mbase + 0x202, 0xbed1);
939 break;
940 case 2:
941 out_le16(mbase + 0x200, 0xaaa2);
942 out_le16(mbase + 0x202, 0xbed2);
943 break;
944 default:
945 out_le16(mbase + 0x200, 0xaaa3);
946 out_le16(mbase + 0x202, 0xbed3);
947 }
948
949 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
950 out_le32(mbase + 0x208, 0x06040001);
951
2b393b0f
SR		 952}
953
954int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
955{
956 volatile void *mbase = NULL;
957 int attempts = 0;
958
959 pci_set_ops(hose,
960 pcie_read_config_byte,
961 pcie_read_config_word,
962 pcie_read_config_dword,
963 pcie_write_config_byte,
964 pcie_write_config_word,
965 pcie_write_config_dword);
966
967 switch (port) {
968 case 0:
969 mbase = (u32 *)CFG_PCIE0_XCFGBASE;
970 hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
971 break;
972 case 1:
973 mbase = (u32 *)CFG_PCIE1_XCFGBASE;
974 hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
975 break;
976 case 2:
977 mbase = (u32 *)CFG_PCIE2_XCFGBASE;
978 hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
979 break;
980 }
981
982 /*
983 * Set up outbound translation to hose->mem_space from PLB
984 * addresses at an offset of 0xd_0000_0000. We set the low
985 * bits of the mask to 11 to turn off splitting into 8
986 * subregions and to enable the outbound translation.
987 */
988 out_le32(mbase + PECFG_POM0LAH, 0x00001ff8);
989 out_le32(mbase + PECFG_POM0LAL, 0x00001000);
990
991 switch (port) {
992 case 0:
993 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
994 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
995 port * CFG_PCIE_MEMSIZE);
996 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
997 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
998 ~(CFG_PCIE_MEMSIZE - 1) | 3);
999 break;
1000 case 1:
1001 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
1002 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE +
1003 port * CFG_PCIE_MEMSIZE));
1004 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
1005 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
1006 ~(CFG_PCIE_MEMSIZE - 1) | 3);
1007 break;
1008 case 2:
1009 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
1010 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE +
1011 port * CFG_PCIE_MEMSIZE));
1012 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
1013 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
1014 ~(CFG_PCIE_MEMSIZE - 1) | 3);
1015 break;
1016 }
1017
1018 /* Set up 16GB inbound memory window at 0 */
1019 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
1020 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
1021 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
1022 out_le32(mbase + PECFG_BAR0LMPA, 0);
1023 out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
1024 out_le32(mbase + PECFG_PIM0LAH, 0x00000004); /* pointing to SRAM */
692519b1
RJ		 1025 out_le32(mbase + PECFG_PIMEN, 0x1);
1026
1027 /* Enable I/O, Mem, and Busmaster cycles */
1028 out_le16((u16 *)(mbase + PCI_COMMAND),
7f191393
GB		 1029 in_le16((u16 *)(mbase + PCI_COMMAND)) |
1030 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
2b393b0f
SR		 1031 out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */
1032 out_le16(mbase + 0x202,0xfeed); /* Setting device ID */
1033 attempts = 10;
1034 switch (port) {
1035 case 0:
1036 while (!(SDR_READ(PESDR0_RCSSTS) & (1 << 8))) {
1037 if (!(attempts--)) {
1038 printf("PCIE0: BMEN is not active\n");
1039 return -1;
1040 }
1041 mdelay(1000);
1042 }
1043 break;
1044 case 1:
1045 while (!(SDR_READ(PESDR1_RCSSTS) & (1 << 8))) {
1046 if (!(attempts--)) {
1047 printf("PCIE1: BMEN is not active\n");
1048 return -1;
1049 }
1050 mdelay(1000);
1051 }
1052 break;
1053 case 2:
1054 while (!(SDR_READ(PESDR2_RCSSTS) & (1 << 8))) {
1055 if (!(attempts--)) {
1056 printf("PCIE2: BMEN is not active\n");
1057 return -1;
1058 }
1059 mdelay(1000);
1060 }
1061 break;
1062 }
1063 printf("PCIE:%d successfully set as endpoint\n",port);
1064
1065 return 0;
692519b1 1066}
5fb692ca 1067#endif /* CONFIG_440SPE && CONFIG_PCI */
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