[J-u-boot.git] / include / configs / ppmc7xx.h

/*
 * ppmc7xx.h
 * ---------
 *
 * Wind River PPMC 7xx/74xx board configuration file.
 *
 * By Richard Danter ([email protected])
 * Copyright (C) 2005 Wind River Systems
 */


#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_PPMC7XX


/*===================================================================
 *
 * User configurable settings - Modify to your preference
 *
 *===================================================================
 */

/*
 * Debug
 *
 * DEBUG		- Define this is you want extra debug info
 * GTREGREAD		- Required to build with debug
 * do_bdinfo		- Required to build with debug
 */

#ifdef	DEBUG
#define	GTREGREAD(x)	0xFFFFFFFF
#define	do_bdinfo(a,b,c,d)
#endif

/*
 * CPU type
 *
 * CONFIG_7xx		- We have a 750 or 755 CPU
 * CONFIG_74xx		- We have a 7400 CPU
 * CONFIG_ALTIVEC	- We have altivec enabled CPU (only 7400)
 * CONFIG_BUS_CLK	- System bus clock in Hz
 */

#define	CONFIG_7xx
#undef	CONFIG_74xx
#undef	CONFIG_ALTIVEC
#define CONFIG_BUS_CLK	66000000


/*
 * Monitor configuration
 *
 * List of command sets to include in shell
 *
 * The following command sets have been tested and known to work:
 *
 * CMD_CACHE		- Cache control commands
 * CMD_MEMORY		- Memory display, change and test commands
 * CMD_FLASH		- Erase and program flash
 * CMD_ENV		- Environment commands
 * CMD_RUN		- Run commands stored in env vars
 * CMD_ELF		- Load ELF files
 * CMD_NET		- Networking/file download commands
 * CMD_PIN		- ICMP Echo Request command
 * CMD_PCI		- PCI Bus scanning command
 */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_FLASH
#define CONFIG_CMD_ENV
#define CONFIG_CMD_RUN
#define CONFIG_CMD_ELF
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_PCI

#undef CONFIG_CMD_KGDB


/*
 * Serial configuration
 *
 * CONFIG_CONS_INDEX		- Serial console port number (COM1)
 * CONFIG_BAUDRATE		- Serial speed
 */

#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		9600


/*
 * PCI config
 *
 * CONFIG_PCI			- Enable PCI bus
 * CONFIG_PCI_PNP		- Enable Plug & Play support
 * CONFIG_PCI_SCAN_SHOW		- Enable display of devices at startup
 */

#define	CONFIG_PCI
#define	CONFIG_PCI_PNP
#undef	CONFIG_PCI_SCAN_SHOW


/*
 * Network config
 *
 * CONFIG_NET_MULTI		- Support for multiple network interfaces
 * CONFIG_EEPRO100		- Intel 8255x Ethernet Controller
 * CONFIG_EEPRO100_SROM_WRITE	- Enable writing to network card ROM
 */

#define	CONFIG_NET_MULTI
#define	CONFIG_EEPRO100
#define	CONFIG_EEPRO100_SROM_WRITE


/*
 * Enable extra init functions
 *
 * CONFIG_MISC_INIT_F		- Call pre-relocation init functions
 * CONFIG_MISC_INIT_R		- Call post relocation init functions
 */

#undef	CONFIG_MISC_INIT_F
#define CONFIG_MISC_INIT_R


/*
 * Boot config
 *
 * CONFIG_BOOTCOMMAND		- Command(s) to execute to auto-boot
 * CONFIG_BOOTDELAY		- How long to wait before auto-boot (in sec)
 */

#define CONFIG_BOOTCOMMAND		\
	"bootp;" \
	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
	"bootm"
#define CONFIG_BOOTDELAY		5


/*===================================================================
 *
 * Board configuration settings - You should not need to modify these
 *
 *===================================================================
 */


/*
 * Memory map
 *
 * This board runs in a standard CHRP (Map-B) configuration.
 *
 *	Type	    Start	End	    Size    Width   Chip Sel
 *	----------- ----------- ----------- ------- ------- --------
 *	SDRAM	    0x00000000	0x04000000  64MB    64b	    SDRAMCS0
 *	User LED's  0x78000000				    RCS3
 *	UART	    0x7C000000				    RCS2
 *	Mailbox	    0xFF000000				    RCS1
 *	Flash	    0xFFC00000	0xFFFFFFFF   4MB    64b	    RCS0
 *
 * Flash sectors are laid out as follows.
 *
 *	Sector	Start		End	Size	Comments
 *	------- ----------- ----------- ------- -----------
 *	 0	0xFFC00000  0xFFC3FFFF	256KB
 *	 1	0xFFC40000  0xFFC7FFFF	256KB
 *	 2	0xFFC80000  0xFFCBFFFF	256KB
 *	 3	0xFFCC0000  0xFFCFFFFF	256KB
 *	 4	0xFFD00000  0xFFD3FFFF	256KB
 *	 5	0xFFD40000  0xFFD7FFFF	256KB
 *	 6	0xFFD80000  0xFFDBFFFF	256KB
 *	 7	0xFFDC0000  0xFFDFFFFF	256KB
 *	 8	0xFFE00000  0xFFE3FFFF	256KB
 *	 9	0xFFE40000  0xFFE7FFFF	256KB
 *	10	0xFFE80000  0xFFEBFFFF	256KB
 *	11	0xFFEC0000  0xFFEFFFFF	256KB
 *	12	0xFFF00000  0xFFF3FFFF	256KB	U-Boot code here
 *	13	0xFFF40000  0xFFF7FFFF	256KB
 *	14	0xFFF80000  0xFFFBFFFF	256KB
 *	15	0xFFFC0000  0xFFFDFFFF	128KB
 *	16	0xFFFE0000  0xFFFE7FFF	 32KB	U-Boot env vars here
 *	17	0xFFFE8000  0xFFFEFFFF	 32KB	U-Boot backup copy of env vars here
 *	18	0xFFFF0000  0xFFFFFFFF	 64KB
 */


/*
 * SDRAM config - see memory map details above.
 *
 * CFG_SDRAM_BASE		- Start address of SDRAM, this _must_ be zero!
 * CFG_SDRAM_SIZE		- Total size of contiguous SDRAM bank(s)
 */

#define CFG_SDRAM_BASE		0x00000000
#define CFG_SDRAM_SIZE		0x04000000


/*
 * Flash config - see memory map details above.
 *
 * CFG_FLASH_BASE		- Start address of flash memory
 * CFG_FLASH_SIZE		- Total size of contiguous flash mem
 * CFG_FLASH_ERASE_TOUT		- Erase timeout in ms
 * CFG_FLASH_WRITE_TOUT		- Write timeout in ms
 * CFG_MAX_FLASH_BANKS		- Number of banks of flash on board
 * CFG_MAX_FLASH_SECT		- Number of sectors in a bank
 */

#define CFG_FLASH_BASE		0xFFC00000
#define CFG_FLASH_SIZE		0x00400000
#define CFG_FLASH_ERASE_TOUT	250000
#define CFG_FLASH_WRITE_TOUT	5000
#define CFG_MAX_FLASH_BANKS	1
#define CFG_MAX_FLASH_SECT	19


/*
 * Monitor config - see memory map details above
 *
 * CFG_MONITOR_BASE		- Base address of monitor code
 * CFG_MALLOC_LEN		- Size of malloc pool (128KB)
 */

#define CFG_MONITOR_BASE	TEXT_BASE
#define CFG_MALLOC_LEN		0x20000


/*
 * Command shell settings
 *
 * CFG_BARGSIZE			- Boot Argument buffer size
 * CFG_BOOTMAPSZ		- Size of app's mapped RAM at boot (Linux=8MB)
 * CFG_CBSIZE			- Console Buffer (input) size
 * CFG_LOAD_ADDR		- Default load address
 * CFG_LONGHELP			- Provide more detailed help
 * CFG_MAXARGS			- Number of args accepted by monitor commands
 * CFG_MEMTEST_START		- Start address of test to run on RAM
 * CFG_MEMTEST_END		- End address of RAM test
 * CFG_PBSIZE			- Print Buffer (output) size
 * CFG_PROMPT			- Prompt string
 */

#define CFG_BARGSIZE		1024
#define CFG_BOOTMAPSZ		0x800000
#define CFG_CBSIZE		1024
#define CFG_LOAD_ADDR		0x100000
#define CFG_LONGHELP
#define CFG_MAXARGS		16
#define CFG_MEMTEST_START	0x00040000
#define CFG_MEMTEST_END		0x00040100
#define CFG_PBSIZE		1024
#define CFG_PROMPT		"=> "


/*
 * Environment config - see memory map details above
 *
 * CFG_ENV_IS_IN_FLASH		- The env variables are stored in flash
 * CFG_ENV_ADDR			- Address of the sector containing env vars
 * CFG_ENV_SIZE			- Ammount of RAM for env vars (used to save RAM, 4KB)
 * CFG_ENV_SECT_SIZE		- Size of sector containing env vars (32KB)
 */

#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_ADDR		0xFFFE0000
#define CFG_ENV_SIZE		0x1000
#define CFG_ENV_ADDR_REDUND	0xFFFE8000
#define CFG_ENV_SIZE_REDUND	0x1000
#define CFG_ENV_SECT_SIZE	0x8000


/*
 * Initial RAM config
 *
 * Since the main system RAM is initialised very early, we place the INIT_RAM
 * in the main system RAM just above the exception vectors. The contents are
 * copied to top of RAM by the init code.
 *
 * CFG_INIT_RAM_ADDR		- Address of Init RAM, above exception vect
 * CFG_INIT_RAM_END		- Size of Init RAM
 * CFG_GBL_DATA_SIZE		- Ammount of RAM to reserve for global data
 * CFG_GBL_DATA_OFFSET		- Start of global data, top of stack
 */

#define CFG_INIT_RAM_ADDR	(CFG_SDRAM_BASE + 0x4000)
#define CFG_INIT_RAM_END	0x4000
#define CFG_GBL_DATA_SIZE	128
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)


/*
 * Initial BAT config
 *
 * BAT0	- System SDRAM
 * BAT1 - LED's and Serial Port
 * BAT2 - PCI Memory
 * BAT3 - PCI I/O including Flash Memory
 */

#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
#define CFG_DBAT0L CFG_IBAT0L
#define CFG_DBAT0U CFG_IBAT0U

#define CFG_IBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CFG_IBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CFG_IBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)


/*
 * Cache config
 *
 * CFG_CACHELINE_SIZE		- Size of a cache line (CPU specific)
 * CFG_L2			- L2 cache enabled if defined
 * L2_INIT			- L2 cache init flags
 * L2_ENABLE			- L2 cache enable flags
 */

#define CFG_CACHELINE_SIZE	32
#undef	CFG_L2
#define L2_INIT			0
#define L2_ENABLE		0


/*
 * Clocks config
 *
 * CFG_BUS_HZ			- Bus clock frequency in Hz
 * CFG_BUS_CLK			- As above (?)
 * CFG_HZ			- Decrementer freq in Hz
 */

#define CFG_BUS_HZ		CONFIG_BUS_CLK
#define CFG_BUS_CLK		CONFIG_BUS_CLK
#define CFG_HZ			1000


/*
 * Serial port config
 *
 * CFG_BAUDRATE_TABLE		- List of valid baud rates
 * CFG_NS16550			- Include the NS16550 driver
 * CFG_NS16550_SERIAL		- Include the serial (wrapper) driver
 * CFG_NS16550_CLK		- Frequency of reference clock
 * CFG_NS16550_REG_SIZE		- 64-bit accesses to 8-bit port
 * CFG_NS16550_COM1		- Base address of 1st serial port
 */

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_CLK		3686400
#define CFG_NS16550_REG_SIZE	-8
#define CFG_NS16550_COM1	0x7C000000


/*
 * PCI Config - Address Map B (CHRP)
 */

#define CFG_PCI_MEMORY_BUS	0x00000000
#define CFG_PCI_MEMORY_PHYS	0x00000000
#define CFG_PCI_MEMORY_SIZE	0x40000000
#define CFG_PCI_MEM_BUS		0x80000000
#define CFG_PCI_MEM_PHYS	0x80000000
#define CFG_PCI_MEM_SIZE	0x7D000000
#define CFG_ISA_MEM_BUS		0x00000000
#define CFG_ISA_MEM_PHYS	0xFD000000
#define CFG_ISA_MEM_SIZE	0x01000000
#define CFG_PCI_IO_BUS		0x00800000
#define CFG_PCI_IO_PHYS		0xFE800000
#define CFG_PCI_IO_SIZE		0x00400000
#define CFG_ISA_IO_BUS		0x00000000
#define CFG_ISA_IO_PHYS		0xFE000000
#define CFG_ISA_IO_SIZE		0x00800000
#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
#define CFG_ISA_IO		CFG_ISA_IO_PHYS
#define CFG_60X_PCI_IO_OFFSET	CFG_ISA_IO_PHYS


/*
 * Extra init functions
 *
 * CFG_BOARD_ASM_INIT		- Call assembly init code
 */

#define CFG_BOARD_ASM_INIT


/*
 * Boot flags
 *
 * BOOTFLAG_COLD		- Indicates a power-on boot
 * BOOTFLAG_WARM		- Indicates a software reset
 */

#define BOOTFLAG_COLD		0x01
#define BOOTFLAG_WARM		0x02


#endif /* __CONFIG_H */
Commit	Line	Data
f5e0d039 HS	1	/*
	2	* ppmc7xx.h
	3	* ---------
b87dfd28	4	*
f5e0d039	5	* Wind River PPMC 7xx/74xx board configuration file.
b87dfd28	6	*
f5e0d039 HS	7	* By Richard Danter ([email protected])
	8	* Copyright (C) 2005 Wind River Systems
	9	*/
	10
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	#define CONFIG_PPMC7XX
	16
	17
	18	/*===================================================================
b87dfd28	19	*
f5e0d039	20	* User configurable settings - Modify to your preference
b87dfd28	21	*
f5e0d039 HS	22	*===================================================================
	23	*/
	24
	25	/*
	26	* Debug
b87dfd28	27	*
cdd917a4 WD	28	* DEBUG - Define this is you want extra debug info
	29	* GTREGREAD - Required to build with debug
	30	* do_bdinfo - Required to build with debug
f5e0d039 HS	31	*/
f5e0d039 HS	32
cdd917a4 WD	33	#ifdef DEBUG
cdd917a4 WD	34	#define GTREGREAD(x) 0xFFFFFFFF
f5e0d039	35	#define do_bdinfo(a,b,c,d)
cdd917a4	36	#endif
f5e0d039 HS	37
	38	/*
	39	* CPU type
b87dfd28	40	*
cdd917a4 WD	41	* CONFIG_7xx - We have a 750 or 755 CPU
	42	* CONFIG_74xx - We have a 7400 CPU
	43	* CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400)
	44	* CONFIG_BUS_CLK - System bus clock in Hz
f5e0d039 HS	45	*/
	46
	47	#define CONFIG_7xx
	48	#undef CONFIG_74xx
	49	#undef CONFIG_ALTIVEC
cdd917a4	50	#define CONFIG_BUS_CLK 66000000
f5e0d039 HS	51
	52
	53	/*
	54	* Monitor configuration
b87dfd28	55	*
26a34560	56	* List of command sets to include in shell
b87dfd28	57	*
f5e0d039	58	* The following command sets have been tested and known to work:
b87dfd28	59	*
26a34560 JL	60	* CMD_CACHE - Cache control commands
	61	* CMD_MEMORY - Memory display, change and test commands
	62	* CMD_FLASH - Erase and program flash
	63	* CMD_ENV - Environment commands
	64	* CMD_RUN - Run commands stored in env vars
	65	* CMD_ELF - Load ELF files
	66	* CMD_NET - Networking/file download commands
	67	* CMD_PIN - ICMP Echo Request command
	68	* CMD_PCI - PCI Bus scanning command
f5e0d039 HS	69	*/
f5e0d039 HS	70
079a136c JL	71	/*
	72	* BOOTP options
	73	*/
	74	#define CONFIG_BOOTP_BOOTFILESIZE
	75	#define CONFIG_BOOTP_BOOTPATH
	76	#define CONFIG_BOOTP_GATEWAY
	77	#define CONFIG_BOOTP_HOSTNAME
	78
	79
26a34560 JL	80	/*
	81	* Command line configuration.
	82	*/
	83	#include <config_cmd_default.h>
	84
	85	#define CONFIG_CMD_FLASH
	86	#define CONFIG_CMD_ENV
	87	#define CONFIG_CMD_RUN
	88	#define CONFIG_CMD_ELF
	89	#define CONFIG_CMD_NET
	90	#define CONFIG_CMD_PING
	91	#define CONFIG_CMD_PCI
	92
	93	#undef CONFIG_CMD_KGDB
f5e0d039 HS	94
	95
	96	/*
	97	* Serial configuration
	98	*
	99	* CONFIG_CONS_INDEX - Serial console port number (COM1)
cdd917a4	100	* CONFIG_BAUDRATE - Serial speed
f5e0d039 HS	101	*/
f5e0d039 HS	102
cdd917a4 WD	103	#define CONFIG_CONS_INDEX 1
cdd917a4 WD	104	#define CONFIG_BAUDRATE 9600
f5e0d039 HS	105
	106
	107	/*
	108	* PCI config
b87dfd28	109	*
cdd917a4 WD	110	* CONFIG_PCI - Enable PCI bus
cdd917a4 WD	111	* CONFIG_PCI_PNP - Enable Plug & Play support
f5e0d039 HS	112	* CONFIG_PCI_SCAN_SHOW - Enable display of devices at startup
	113	*/
	114
	115	#define CONFIG_PCI
	116	#define CONFIG_PCI_PNP
	117	#undef CONFIG_PCI_SCAN_SHOW
	118
	119
	120	/*
	121	* Network config
b87dfd28	122	*
cdd917a4 WD	123	* CONFIG_NET_MULTI - Support for multiple network interfaces
	124	* CONFIG_EEPRO100 - Intel 8255x Ethernet Controller
	125	* CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM
f5e0d039 HS	126	*/
	127
	128	#define CONFIG_NET_MULTI
	129	#define CONFIG_EEPRO100
	130	#define CONFIG_EEPRO100_SROM_WRITE
	131
	132
	133	/*
	134	* Enable extra init functions
b87dfd28	135	*
f5e0d039 HS	136	* CONFIG_MISC_INIT_F - Call pre-relocation init functions
	137	* CONFIG_MISC_INIT_R - Call post relocation init functions
	138	*/
	139
	140	#undef CONFIG_MISC_INIT_F
b87dfd28	141	#define CONFIG_MISC_INIT_R
f5e0d039 HS	142
	143
	144	/*
	145	* Boot config
b87dfd28	146	*
f5e0d039	147	* CONFIG_BOOTCOMMAND - Command(s) to execute to auto-boot
cdd917a4	148	* CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec)
f5e0d039 HS	149	*/
	150
	151	#define CONFIG_BOOTCOMMAND \
	152	"bootp;" \
	153	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
	154	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
	155	"bootm"
	156	#define CONFIG_BOOTDELAY 5
	157
	158
	159	/*===================================================================
b87dfd28	160	*
f5e0d039	161	* Board configuration settings - You should not need to modify these
b87dfd28	162	*
f5e0d039 HS	163	*===================================================================
	164	*/
	165
	166
f5e0d039 HS	167	/*
f5e0d039 HS	168	* Memory map
b87dfd28	169	*
f5e0d039	170	* This board runs in a standard CHRP (Map-B) configuration.
b87dfd28	171	*
cdd917a4	172	* Type Start End Size Width Chip Sel
f5e0d039	173	* ----------- ----------- ----------- ------- ------- --------
cdd917a4 WD	174	* SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0
	175	* User LED's 0x78000000 RCS3
	176	* UART 0x7C000000 RCS2
	177	* Mailbox 0xFF000000 RCS1
	178	* Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0
b87dfd28	179	*
f5e0d039	180	* Flash sectors are laid out as follows.
b87dfd28	181	*
cdd917a4	182	* Sector Start End Size Comments
f5e0d039	183	* ------- ----------- ----------- ------- -----------
cdd917a4 WD	184	* 0 0xFFC00000 0xFFC3FFFF 256KB
	185	* 1 0xFFC40000 0xFFC7FFFF 256KB
	186	* 2 0xFFC80000 0xFFCBFFFF 256KB
	187	* 3 0xFFCC0000 0xFFCFFFFF 256KB
	188	* 4 0xFFD00000 0xFFD3FFFF 256KB
	189	* 5 0xFFD40000 0xFFD7FFFF 256KB
	190	* 6 0xFFD80000 0xFFDBFFFF 256KB
	191	* 7 0xFFDC0000 0xFFDFFFFF 256KB
	192	* 8 0xFFE00000 0xFFE3FFFF 256KB
	193	* 9 0xFFE40000 0xFFE7FFFF 256KB
	194	* 10 0xFFE80000 0xFFEBFFFF 256KB
	195	* 11 0xFFEC0000 0xFFEFFFFF 256KB
	196	* 12 0xFFF00000 0xFFF3FFFF 256KB U-Boot code here
	197	* 13 0xFFF40000 0xFFF7FFFF 256KB
	198	* 14 0xFFF80000 0xFFFBFFFF 256KB
	199	* 15 0xFFFC0000 0xFFFDFFFF 128KB
	200	* 16 0xFFFE0000 0xFFFE7FFF 32KB U-Boot env vars here
	201	* 17 0xFFFE8000 0xFFFEFFFF 32KB U-Boot backup copy of env vars here
	202	* 18 0xFFFF0000 0xFFFFFFFF 64KB
f5e0d039 HS	203	*/
	204
	205
	206	/*
	207	* SDRAM config - see memory map details above.
b87dfd28	208	*
cdd917a4 WD	209	* CFG_SDRAM_BASE - Start address of SDRAM, this _must_ be zero!
cdd917a4 WD	210	* CFG_SDRAM_SIZE - Total size of contiguous SDRAM bank(s)
f5e0d039 HS	211	*/
f5e0d039 HS	212
cdd917a4 WD	213	#define CFG_SDRAM_BASE 0x00000000
cdd917a4 WD	214	#define CFG_SDRAM_SIZE 0x04000000
f5e0d039 HS	215
f5e0d039 HS	216
b87dfd28	217	/*
f5e0d039	218	* Flash config - see memory map details above.
b87dfd28	219	*
cdd917a4 WD	220	* CFG_FLASH_BASE - Start address of flash memory
cdd917a4 WD	221	* CFG_FLASH_SIZE - Total size of contiguous flash mem
f5e0d039 HS	222	* CFG_FLASH_ERASE_TOUT - Erase timeout in ms
	223	* CFG_FLASH_WRITE_TOUT - Write timeout in ms
	224	* CFG_MAX_FLASH_BANKS - Number of banks of flash on board
	225	* CFG_MAX_FLASH_SECT - Number of sectors in a bank
	226	*/
	227
cdd917a4 WD	228	#define CFG_FLASH_BASE 0xFFC00000
cdd917a4 WD	229	#define CFG_FLASH_SIZE 0x00400000
f5e0d039 HS	230	#define CFG_FLASH_ERASE_TOUT 250000
f5e0d039 HS	231	#define CFG_FLASH_WRITE_TOUT 5000
cdd917a4 WD	232	#define CFG_MAX_FLASH_BANKS 1
cdd917a4 WD	233	#define CFG_MAX_FLASH_SECT 19
f5e0d039 HS	234
	235
	236	/*
	237	* Monitor config - see memory map details above
b87dfd28	238	*
cdd917a4 WD	239	* CFG_MONITOR_BASE - Base address of monitor code
cdd917a4 WD	240	* CFG_MALLOC_LEN - Size of malloc pool (128KB)
f5e0d039 HS	241	*/
f5e0d039 HS	242
cdd917a4 WD	243	#define CFG_MONITOR_BASE TEXT_BASE
cdd917a4 WD	244	#define CFG_MALLOC_LEN 0x20000
f5e0d039 HS	245
	246
	247	/*
	248	* Command shell settings
b87dfd28	249	*
f5e0d039 HS	250	* CFG_BARGSIZE - Boot Argument buffer size
	251	* CFG_BOOTMAPSZ - Size of app's mapped RAM at boot (Linux=8MB)
	252	* CFG_CBSIZE - Console Buffer (input) size
	253	* CFG_LOAD_ADDR - Default load address
	254	* CFG_LONGHELP - Provide more detailed help
	255	* CFG_MAXARGS - Number of args accepted by monitor commands
	256	* CFG_MEMTEST_START - Start address of test to run on RAM
	257	* CFG_MEMTEST_END - End address of RAM test
	258	* CFG_PBSIZE - Print Buffer (output) size
	259	* CFG_PROMPT - Prompt string
	260	*/
	261
cdd917a4 WD	262	#define CFG_BARGSIZE 1024
	263	#define CFG_BOOTMAPSZ 0x800000
	264	#define CFG_CBSIZE 1024
	265	#define CFG_LOAD_ADDR 0x100000
f5e0d039	266	#define CFG_LONGHELP
cdd917a4 WD	267	#define CFG_MAXARGS 16
	268	#define CFG_MEMTEST_START 0x00040000
	269	#define CFG_MEMTEST_END 0x00040100
	270	#define CFG_PBSIZE 1024
	271	#define CFG_PROMPT "=> "
f5e0d039 HS	272
	273
	274	/*
	275	* Environment config - see memory map details above
b87dfd28	276	*
f5e0d039 HS	277	* CFG_ENV_IS_IN_FLASH - The env variables are stored in flash
f5e0d039 HS	278	* CFG_ENV_ADDR - Address of the sector containing env vars
b87dfd28	279	* CFG_ENV_SIZE - Ammount of RAM for env vars (used to save RAM, 4KB)
f5e0d039 HS	280	* CFG_ENV_SECT_SIZE - Size of sector containing env vars (32KB)
	281	*/
	282
cdd917a4 WD	283	#define CFG_ENV_IS_IN_FLASH 1
	284	#define CFG_ENV_ADDR 0xFFFE0000
	285	#define CFG_ENV_SIZE 0x1000
	286	#define CFG_ENV_ADDR_REDUND 0xFFFE8000
	287	#define CFG_ENV_SIZE_REDUND 0x1000
	288	#define CFG_ENV_SECT_SIZE 0x8000
f5e0d039 HS	289
	290
	291	/*
	292	* Initial RAM config
	293	*
	294	* Since the main system RAM is initialised very early, we place the INIT_RAM
	295	* in the main system RAM just above the exception vectors. The contents are
	296	* copied to top of RAM by the init code.
b87dfd28	297	*
f5e0d039	298	* CFG_INIT_RAM_ADDR - Address of Init RAM, above exception vect
cdd917a4	299	* CFG_INIT_RAM_END - Size of Init RAM
f5e0d039 HS	300	* CFG_GBL_DATA_SIZE - Ammount of RAM to reserve for global data
	301	* CFG_GBL_DATA_OFFSET - Start of global data, top of stack
	302	*/
	303
cdd917a4 WD	304	#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + 0x4000)
	305	#define CFG_INIT_RAM_END 0x4000
	306	#define CFG_GBL_DATA_SIZE 128
	307	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
f5e0d039 HS	308
	309
	310	/*
	311	* Initial BAT config
b87dfd28	312	*
f5e0d039 HS	313	* BAT0 - System SDRAM
	314	* BAT1 - LED's and Serial Port
	315	* BAT2 - PCI Memory
	316	* BAT3 - PCI I/O including Flash Memory
	317	*/
	318
	319	#define CFG_IBAT0L (CFG_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	320	#define CFG_IBAT0U (CFG_SDRAM_BASE \| BATU_BL_64M \| BATU_VS \| BATU_VP)
	321	#define CFG_DBAT0L CFG_IBAT0L
	322	#define CFG_DBAT0U CFG_IBAT0U
	323
	324	#define CFG_IBAT1L (0x70000000 \| BATL_PP_RW \| BATL_CACHEINHIBIT)
	325	#define CFG_IBAT1U (0x70000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	326	#define CFG_DBAT1L (0x70000000 \| BATL_PP_RW \| BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	327	#define CFG_DBAT1U (0x70000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	328
	329	#define CFG_IBAT2L (0x80000000 \| BATL_PP_RW \| BATL_CACHEINHIBIT)
	330	#define CFG_IBAT2U (0x80000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	331	#define CFG_DBAT2L (0x80000000 \| BATL_PP_RW \| BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	332	#define CFG_DBAT2U (0x80000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	333
	334	#define CFG_IBAT3L (0xF0000000 \| BATL_PP_RW \| BATL_CACHEINHIBIT)
	335	#define CFG_IBAT3U (0xF0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	336	#define CFG_DBAT3L (0xF0000000 \| BATL_PP_RW \| BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	337	#define CFG_DBAT3U (0xF0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	338
	339
	340	/*
	341	* Cache config
b87dfd28	342	*
f5e0d039	343	* CFG_CACHELINE_SIZE - Size of a cache line (CPU specific)
cdd917a4 WD	344	* CFG_L2 - L2 cache enabled if defined
	345	* L2_INIT - L2 cache init flags
	346	* L2_ENABLE - L2 cache enable flags
f5e0d039 HS	347	*/
f5e0d039 HS	348
cdd917a4	349	#define CFG_CACHELINE_SIZE 32
f5e0d039	350	#undef CFG_L2
cdd917a4 WD	351	#define L2_INIT 0
cdd917a4 WD	352	#define L2_ENABLE 0
f5e0d039 HS	353
	354
	355	/*
	356	* Clocks config
b87dfd28	357	*
cdd917a4 WD	358	* CFG_BUS_HZ - Bus clock frequency in Hz
	359	* CFG_BUS_CLK - As above (?)
	360	* CFG_HZ - Decrementer freq in Hz
f5e0d039 HS	361	*/
f5e0d039 HS	362
cdd917a4 WD	363	#define CFG_BUS_HZ CONFIG_BUS_CLK
	364	#define CFG_BUS_CLK CONFIG_BUS_CLK
	365	#define CFG_HZ 1000
f5e0d039 HS	366
	367
	368	/*
	369	* Serial port config
b87dfd28	370	*
f5e0d039	371	* CFG_BAUDRATE_TABLE - List of valid baud rates
cdd917a4	372	* CFG_NS16550 - Include the NS16550 driver
f5e0d039	373	* CFG_NS16550_SERIAL - Include the serial (wrapper) driver
cdd917a4	374	* CFG_NS16550_CLK - Frequency of reference clock
f5e0d039	375	* CFG_NS16550_REG_SIZE - 64-bit accesses to 8-bit port
cdd917a4	376	* CFG_NS16550_COM1 - Base address of 1st serial port
f5e0d039 HS	377	*/
f5e0d039 HS	378
cdd917a4	379	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
f5e0d039 HS	380	#define CFG_NS16550
f5e0d039 HS	381	#define CFG_NS16550_SERIAL
cdd917a4	382	#define CFG_NS16550_CLK 3686400
f5e0d039	383	#define CFG_NS16550_REG_SIZE -8
cdd917a4	384	#define CFG_NS16550_COM1 0x7C000000
f5e0d039 HS	385
	386
	387	/*
	388	* PCI Config - Address Map B (CHRP)
	389	*/
	390
cdd917a4 WD	391	#define CFG_PCI_MEMORY_BUS 0x00000000
	392	#define CFG_PCI_MEMORY_PHYS 0x00000000
	393	#define CFG_PCI_MEMORY_SIZE 0x40000000
	394	#define CFG_PCI_MEM_BUS 0x80000000
	395	#define CFG_PCI_MEM_PHYS 0x80000000
	396	#define CFG_PCI_MEM_SIZE 0x7D000000
	397	#define CFG_ISA_MEM_BUS 0x00000000
	398	#define CFG_ISA_MEM_PHYS 0xFD000000
	399	#define CFG_ISA_MEM_SIZE 0x01000000
	400	#define CFG_PCI_IO_BUS 0x00800000
	401	#define CFG_PCI_IO_PHYS 0xFE800000
	402	#define CFG_PCI_IO_SIZE 0x00400000
	403	#define CFG_ISA_IO_BUS 0x00000000
	404	#define CFG_ISA_IO_PHYS 0xFE000000
	405	#define CFG_ISA_IO_SIZE 0x00800000
f5e0d039	406	#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
cdd917a4 WD	407	#define CFG_ISA_IO CFG_ISA_IO_PHYS
cdd917a4 WD	408	#define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS
f5e0d039 HS	409
	410
	411	/*
	412	* Extra init functions
b87dfd28	413	*
f5e0d039 HS	414	* CFG_BOARD_ASM_INIT - Call assembly init code
	415	*/
	416
	417	#define CFG_BOARD_ASM_INIT
	418
	419
	420	/*
	421	* Boot flags
b87dfd28	422	*
cdd917a4 WD	423	* BOOTFLAG_COLD - Indicates a power-on boot
cdd917a4 WD	424	* BOOTFLAG_WARM - Indicates a software reset
f5e0d039	425	*/
b87dfd28	426
cdd917a4 WD	427	#define BOOTFLAG_COLD 0x01
cdd917a4 WD	428	#define BOOTFLAG_WARM 0x02
f5e0d039 HS	429
	430
	431	#endif /* __CONFIG_H */