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Commit | Line | Data |
---|---|---|
0cc2a078 TR |
1 | CONFIG_ARM=y |
2 | CONFIG_ARCH_IMX8M=y | |
98463903 | 3 | CONFIG_TEXT_BASE=0x40200000 |
9802154a | 4 | CONFIG_SYS_MALLOC_LEN=0x2000000 |
83061dbd | 5 | CONFIG_SPL_GPIO=y |
0cc2a078 TR |
6 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
7 | CONFIG_SPL_LIBGENERIC_SUPPORT=y | |
c960c0fd | 8 | CONFIG_SF_DEFAULT_SPEED=80000000 |
0cc2a078 TR |
9 | CONFIG_ENV_SIZE=0x10000 |
10 | CONFIG_ENV_OFFSET=0x3C0000 | |
0cc2a078 | 11 | CONFIG_DM_GPIO=y |
c16aa668 | 12 | CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-phyboard-polis-rdk" |
0cc2a078 TR |
13 | CONFIG_SPL_TEXT_BASE=0x7E1000 |
14 | CONFIG_TARGET_PHYCORE_IMX8MM=y | |
0ee02e1c | 15 | CONFIG_DM_RESET=y |
c90e1893 | 16 | CONFIG_SYS_MONITOR_LEN=524288 |
103c5f18 | 17 | CONFIG_SPL_MMC=y |
2a736066 | 18 | CONFIG_SPL_SERIAL=y |
9ca00684 | 19 | CONFIG_SPL_DRIVERS_MISC=y |
fcb5117d | 20 | CONFIG_SPL_STACK=0x920000 |
18e791c4 TR |
21 | CONFIG_SPL_HAS_BSS_LINKER_SECTION=y |
22 | CONFIG_SPL_BSS_START_ADDR=0x910000 | |
23 | CONFIG_SPL_BSS_MAX_SIZE=0x2000 | |
0cc2a078 TR |
24 | CONFIG_SPL=y |
25 | CONFIG_ENV_OFFSET_REDUND=0x3E0000 | |
49c8ef0e | 26 | CONFIG_SYS_LOAD_ADDR=0x40480000 |
0ee02e1c | 27 | CONFIG_PCI=y |
0cc2a078 TR |
28 | CONFIG_FIT=y |
29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 | |
30 | CONFIG_SPL_LOAD_FIT=y | |
0cc2a078 | 31 | CONFIG_OF_SYSTEM_SETUP=y |
970bf860 TR |
32 | CONFIG_USE_BOOTCOMMAND=y |
33 | CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;" | |
0cc2a078 | 34 | CONFIG_DEFAULT_FDT_FILE="oftree" |
42fb448a TR |
35 | CONFIG_SYS_CBSIZE=2048 |
36 | CONFIG_SYS_PBSIZE=2074 | |
0cc2a078 | 37 | CONFIG_BOARD_LATE_INIT=y |
f113d7d3 | 38 | # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set |
82e26e0d SG |
39 | CONFIG_SPL_SYS_MALLOC=y |
40 | CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y | |
41 | CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 | |
42 | CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 | |
2a00d73d | 43 | CONFIG_SPL_SYS_MMCSD_RAW_MODE=y |
f76750d1 TR |
44 | CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y |
45 | CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 | |
975e7cf3 | 46 | CONFIG_SPL_I2C=y |
933b2f09 | 47 | CONFIG_SPL_POWER=y |
f38b1da8 | 48 | CONFIG_SPL_SPI_FLASH_MTD=y |
078111b9 | 49 | CONFIG_SPL_WATCHDOG=y |
0cc2a078 | 50 | CONFIG_HUSH_PARSER=y |
ba6d575e | 51 | CONFIG_SYS_PROMPT="u-boot=> " |
0cc2a078 TR |
52 | # CONFIG_CMD_EXPORTENV is not set |
53 | # CONFIG_CMD_IMPORTENV is not set | |
60e01c6d | 54 | CONFIG_CMD_ERASEENV=y |
0cc2a078 TR |
55 | # CONFIG_CMD_CRC32 is not set |
56 | CONFIG_CMD_EEPROM=y | |
88cd7d0e TR |
57 | CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 |
58 | CONFIG_SYS_EEPROM_SIZE=4096 | |
59 | CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 | |
60 | CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 | |
454ea0e2 | 61 | CONFIG_CMD_CLK=y |
0cc2a078 TR |
62 | CONFIG_CMD_FUSE=y |
63 | CONFIG_CMD_GPIO=y | |
64 | CONFIG_CMD_I2C=y | |
65 | CONFIG_CMD_MMC=y | |
0ee02e1c | 66 | CONFIG_CMD_PCI=y |
f38b1da8 | 67 | CONFIG_CMD_SF_TEST=y |
0cc2a078 TR |
68 | CONFIG_CMD_DHCP=y |
69 | CONFIG_CMD_MII=y | |
70 | CONFIG_CMD_PING=y | |
71 | CONFIG_CMD_CACHE=y | |
72 | CONFIG_CMD_REGULATOR=y | |
73 | CONFIG_CMD_EXT2=y | |
74 | CONFIG_CMD_EXT4=y | |
75 | CONFIG_CMD_EXT4_WRITE=y | |
76 | CONFIG_CMD_FAT=y | |
77 | CONFIG_OF_CONTROL=y | |
78 | CONFIG_SPL_OF_CONTROL=y | |
79 | CONFIG_ENV_OVERWRITE=y | |
80 | CONFIG_ENV_IS_IN_MMC=y | |
81 | CONFIG_SYS_REDUNDAND_ENVIRONMENT=y | |
82 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y | |
83 | CONFIG_SYS_MMC_ENV_DEV=2 | |
84 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y | |
85 | CONFIG_SPL_DM=y | |
86 | CONFIG_SPL_CLK_COMPOSITE_CCF=y | |
87 | CONFIG_CLK_COMPOSITE_CCF=y | |
88 | CONFIG_SPL_CLK_IMX8MM=y | |
89 | CONFIG_CLK_IMX8MM=y | |
90 | CONFIG_MXC_GPIO=y | |
91 | CONFIG_DM_I2C=y | |
0cc2a078 TR |
92 | CONFIG_MISC=y |
93 | CONFIG_I2C_EEPROM=y | |
94 | CONFIG_SYS_I2C_EEPROM_ADDR=0x51 | |
0cc2a078 TR |
95 | CONFIG_SUPPORT_EMMC_BOOT=y |
96 | CONFIG_MMC_IO_VOLTAGE=y | |
97 | CONFIG_MMC_UHS_SUPPORT=y | |
98 | CONFIG_MMC_HS400_ES_SUPPORT=y | |
99 | CONFIG_MMC_HS400_SUPPORT=y | |
1ed68f92 | 100 | CONFIG_FSL_USDHC=y |
f38b1da8 TR |
101 | CONFIG_MTD=y |
102 | CONFIG_DM_MTD=y | |
103 | CONFIG_DM_SPI_FLASH=y | |
104 | CONFIG_SF_DEFAULT_BUS=3 | |
f38b1da8 TR |
105 | CONFIG_SPI_FLASH_BAR=y |
106 | CONFIG_SPI_FLASH_MACRONIX=y | |
107 | CONFIG_SPI_FLASH_SPANSION=y | |
108 | CONFIG_SPI_FLASH_STMICRO=y | |
109 | CONFIG_SPI_FLASH_SST=y | |
110 | CONFIG_SPI_FLASH_WINBOND=y | |
111 | # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set | |
112 | CONFIG_SPI_FLASH_MTD=y | |
0cc2a078 TR |
113 | CONFIG_PHYLIB=y |
114 | CONFIG_PHY_TI_DP83867=y | |
0cc2a078 TR |
115 | CONFIG_PHY_GIGE=y |
116 | CONFIG_FEC_MXC=y | |
117 | CONFIG_MII=y | |
0ee02e1c LM |
118 | CONFIG_NVME_PCI=y |
119 | CONFIG_PCIE_DW_IMX=y | |
120 | CONFIG_PHY=y | |
121 | CONFIG_PHY_IMX8M_PCIE=y | |
0cc2a078 TR |
122 | CONFIG_PINCTRL=y |
123 | CONFIG_SPL_PINCTRL=y | |
124 | CONFIG_PINCTRL_IMX8M=y | |
0ee02e1c LM |
125 | CONFIG_POWER_DOMAIN=y |
126 | CONFIG_IMX8M_POWER_DOMAIN=y | |
0cc2a078 TR |
127 | CONFIG_DM_REGULATOR_FIXED=y |
128 | CONFIG_DM_REGULATOR_GPIO=y | |
64d118b2 | 129 | CONFIG_DM_SERIAL=y |
0cc2a078 | 130 | CONFIG_MXC_UART=y |
f38b1da8 TR |
131 | CONFIG_SPI=y |
132 | CONFIG_DM_SPI=y | |
133 | CONFIG_NXP_FSPI=y | |
0cc2a078 TR |
134 | CONFIG_SYSRESET=y |
135 | CONFIG_SPL_SYSRESET=y | |
136 | CONFIG_SYSRESET_PSCI=y | |
137 | CONFIG_SYSRESET_WATCHDOG=y | |
138 | CONFIG_DM_THERMAL=y | |
feb2d51c | 139 | CONFIG_IMX_TMU=y |
0cc2a078 | 140 | CONFIG_IMX_WATCHDOG=y |