[J-u-boot.git] / include / configs / ls2085a_common.h

/*
 * Copyright (C) 2014 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __LS2_COMMON_H
#define __LS2_COMMON_H

#define CONFIG_SYS_GENERIC_BOARD

#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LSCH3
#define CONFIG_LS2085A
#define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147

/* Errata fixes */
#define CONFIG_ARM_ERRATA_828024
#define CONFIG_ARM_ERRATA_826974

/* We need architecture specific misc initializations */
#define CONFIG_ARCH_MISC_INIT

/* Link Definitions */
#define CONFIG_SYS_TEXT_BASE		0x30001000

#ifdef CONFIG_EMU
#define CONFIG_SYS_NO_FLASH
#endif

#define CONFIG_SUPPORT_RAW_INITRD

#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F	1

/* Flat Device Tree Definitions */
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP

/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */

#define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
#ifndef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_FSL_DDR3		/* Use DDR3 memory */
#define CONFIG_SYS_DDR_RAW_TIMING
#endif
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	4

#define CONFIG_SYS_FSL_DDR_INTLV_256B	/* force 256 byte interleaving */

#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE	0x8080000000ULL
#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	2

/*
 * SMP Definitinos
 */
#define CPU_RELEASE_ADDR		secondary_boot_func

#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
#define CONFIG_SYS_DP_DDR_BASE		0x6000000000ULL
/*
 * DDR controller use 0 as the base address for binding.
 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
 */
#define CONFIG_SYS_DP_DDR_BASE_PHY	0
#define CONFIG_DP_DDR_CTRL		2
#define CONFIG_DP_DDR_NUM_CTRLS		1
#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1

/* Generic Timer Definitions */
#define COUNTER_FREQUENCY		12000000	/* 12MHz */

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)

/* I2C */
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_MXC_I2C1_SPEED	40000000
#define CONFIG_SYS_MXC_I2C2_SPEED	40000000

/* Serial Port */
#define CONFIG_CONS_INDEX       2
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE     1
#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)

#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/* IFC */
#define CONFIG_FSL_IFC
#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
/*
 * During booting, CS0 needs to be at the region of 0x30000000, i.e. the IFC
 * address 0. But this region is limited to 256MB. To accommodate bigger NOR
 * flash and other devices, we will map CS0 to 0x580000000 after relocation.
 * CONFIG_SYS_FLASH_BASE has the final address (core view)
 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
 */
#define CONFIG_SYS_FLASH_BASE			0x580000000ULL
#define CONFIG_SYS_FLASH_BASE_PHYS		0x80000000
#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000

/*
 * NOR Flash Timing Params
 */
#define CONFIG_SYS_NOR0_CSPR					\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR0_CSPR_EARLY				\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x1) | \
				FTIM0_NOR_TEADC(0x1) | \
				FTIM0_NOR_TEAHC(0x1))
#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1) | \
				FTIM1_NOR_TRAD_NOR(0x1))
#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x0) | \
				FTIM2_NOR_TCH(0x0) | \
				FTIM2_NOR_TWP(0x1))
#define CONFIG_SYS_NOR_FTIM3	0x04000000
#define CONFIG_SYS_IFC_CCR	0x01000000

#ifndef CONFIG_SYS_NO_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
#endif

#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_MAX_ECCPOS	256
#define CONFIG_SYS_NAND_MAX_OOBFREE	2
#define CONFIG_SYS_NAND_BASE		0x520000000
#define CONFIG_SYS_NAND_BASE_PHYS	0x20000000

#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)

#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/

#define CONFIG_SYS_NAND_ONFI_DETECTION

/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x07) | \
					FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0x0e)   | \
					FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
					FTIM2_NAND_TREH(0x0a) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3		0x0

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_CMD_NAND

#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)

#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3

/* Debug Server firmware */
#define CONFIG_FSL_DEBUG_SERVER
#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE	(512UL * 1024 * 1024)
#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR			0x580C00000ULL
/* 2 sec timeout */
#define CONFIG_SYS_DEBUG_SERVER_TIMEOUT			(2 * 1000 * 1000)

/* MC firmware */
#define CONFIG_FSL_MC_ENET
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE	(512UL * 1024 * 1024)
#define CONFIG_SYS_LS_MC_FW_IN_NOR
#define CONFIG_SYS_LS_MC_FW_ADDR	0x580200000ULL
#define CONFIG_SYS_LS_MC_DPL_IN_NOR
#define CONFIG_SYS_LS_MC_DPL_ADDR	0x5806C0000ULL
/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH	(256 * 1024)
#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0xe00000

/* Carve out a DDR region which will not be used by u-boot/Linux */
#if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
#define CONFIG_SYS_MEM_TOP_HIDE		get_dram_size_to_hide()
#endif

/* Command line configuration */
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_BDI
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_RUN
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_SOURCE
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION

/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
#define CONFIG_ARCH_EARLY_INIT_R

/* Physical Memory Map */
/* fixme: these need to be checked against the board */
#define CONFIG_CHIP_SELECTS_PER_CTRL	4
#define CONFIG_SYS_CLK_FREQ	100000000
#define CONFIG_DDR_CLK_FREQ	133333333

#define CONFIG_NR_DRAM_BANKS		3

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		128

#define CONFIG_DISPLAY_CPUINFO

/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"loadaddr=0x80100000\0"			\
	"kernel_addr=0x100000\0"		\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xffffffffffffffff\0"		\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0x581200000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x1000000\0"		\
	"console=ttyAMA0,38400n8\0"

#define CONFIG_BOOTARGS		"console=ttyS1,115200 root=/dev/ram0 " \
				"earlycon=uart8250,mmio,0x21c0600,115200 " \
				"default_hugepagesz=2m hugepagesz=2m " \
				"hugepages=16"
#define CONFIG_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
					"$kernel_size && bootm $kernel_load"
#define CONFIG_BOOTDELAY		1

/* Store environment at top of flash */
#define CONFIG_ENV_IS_NOWHERE		1
#define CONFIG_ENV_SIZE			0x1000

/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
#define CONFIG_SYS_PROMPT		"> "
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING		1
#define CONFIG_SYS_MAXARGS		64	/* max command args */

#ifndef __ASSEMBLY__
unsigned long get_dram_size_to_hide(void);
#endif

#endif /* __LS2_COMMON_H */
Commit	Line	Data
f749db3a YS	1	/*
	2	* Copyright (C) 2014 Freescale Semiconductor
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __LS2_COMMON_H
	8	#define __LS2_COMMON_H
	9
	10	#define CONFIG_SYS_GENERIC_BOARD
	11
	12	#define CONFIG_REMAKE_ELF
	13	#define CONFIG_FSL_LSCH3
	14	#define CONFIG_LS2085A
	15	#define CONFIG_GICV3
9c66ce66	16	#define CONFIG_FSL_TZPC_BP147
f749db3a	17
1b1069cd BS	18	/* Errata fixes */
	19	#define CONFIG_ARM_ERRATA_828024
	20	#define CONFIG_ARM_ERRATA_826974
	21
422cb08a BS	22	/* We need architecture specific misc initializations */
	23	#define CONFIG_ARCH_MISC_INIT
	24
f749db3a	25	/* Link Definitions */
8aeb893a	26	#define CONFIG_SYS_TEXT_BASE 0x30001000
f749db3a	27
e211c12e	28	#ifdef CONFIG_EMU
f749db3a	29	#define CONFIG_SYS_NO_FLASH
e211c12e	30	#endif
f749db3a YS	31
	32	#define CONFIG_SUPPORT_RAW_INITRD
	33
	34	#define CONFIG_SKIP_LOWLEVEL_INIT
	35	#define CONFIG_BOARD_EARLY_INIT_F 1
	36
f749db3a YS	37	/* Flat Device Tree Definitions */
	38	#define CONFIG_OF_LIBFDT
	39	#define CONFIG_OF_BOARD_SETUP
	40
	41	/* new uImage format support */
	42	#define CONFIG_FIT
	43	#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
	44
	45	#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
	46	#ifndef CONFIG_SYS_FSL_DDR4
	47	#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
	48	#define CONFIG_SYS_DDR_RAW_TIMING
	49	#endif
	50	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	51	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
	52
	53	#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
	54
f749db3a YS	55	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
	56	#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
	57	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	58	#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
d9c68b14 YS	59	#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
d9c68b14 YS	60
8bfa301b YS	61	/*
	62	* SMP Definitinos
	63	*/
	64	#define CPU_RELEASE_ADDR secondary_boot_func
	65
d9c68b14 YS	66	#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
	67	#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
	68	/*
	69	* DDR controller use 0 as the base address for binding.
	70	* It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
	71	*/
	72	#define CONFIG_SYS_DP_DDR_BASE_PHY 0
	73	#define CONFIG_DP_DDR_CTRL 2
	74	#define CONFIG_DP_DDR_NUM_CTRLS 1
	75	#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
f749db3a YS	76
	77	/* Generic Timer Definitions */
	78	#define COUNTER_FREQUENCY 12000000 /* 12MHz */
	79
	80	/* Size of malloc() pool */
	81	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
	82
	83	/* I2C */
	84	#define CONFIG_CMD_I2C
	85	#define CONFIG_SYS_I2C
	86	#define CONFIG_SYS_I2C_MXC
	87	#define CONFIG_SYS_MXC_I2C1_SPEED 40000000
	88	#define CONFIG_SYS_MXC_I2C2_SPEED 40000000
	89
	90	/* Serial Port */
	91	#define CONFIG_CONS_INDEX 2
	92	#define CONFIG_SYS_NS16550
	93	#define CONFIG_SYS_NS16550_SERIAL
	94	#define CONFIG_SYS_NS16550_REG_SIZE 1
	95	#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
	96
	97	#define CONFIG_BAUDRATE 115200
	98	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	99
	100	/* IFC */
	101	#define CONFIG_FSL_IFC
	102	#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
	103	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(12810241024)
	104	/*
	105	* During booting, CS0 needs to be at the region of 0x30000000, i.e. the IFC
	106	* address 0. But this region is limited to 256MB. To accommodate bigger NOR
	107	* flash and other devices, we will map CS0 to 0x580000000 after relocation.
	108	* CONFIG_SYS_FLASH_BASE has the final address (core view)
	109	* CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
	110	* CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
	111	* CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
	112	*/
	113	#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
	114	#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
	115	#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
	116
	117	/*
	118	* NOR Flash Timing Params
	119	*/
	120	#define CONFIG_SYS_NOR0_CSPR \
	121	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	122	CSPR_PORT_SIZE_16 \| \
	123	CSPR_MSEL_NOR \| \
	124	CSPR_V)
	125	#define CONFIG_SYS_NOR0_CSPR_EARLY \
	126	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) \| \
	127	CSPR_PORT_SIZE_16 \| \
	128	CSPR_MSEL_NOR \| \
	129	CSPR_V)
	130	#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
	131	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) \| \
	132	FTIM0_NOR_TEADC(0x1) \| \
	133	FTIM0_NOR_TEAHC(0x1))
	134	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) \| \
	135	FTIM1_NOR_TRAD_NOR(0x1))
	136	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) \| \
	137	FTIM2_NOR_TCH(0x0) \| \
	138	FTIM2_NOR_TWP(0x1))
	139	#define CONFIG_SYS_NOR_FTIM3 0x04000000
140	#define CONFIG_SYS_IFC_CCR 0x01000000
141
e211c12e PK	142	#ifndef CONFIG_SYS_NO_FLASH
	143	#define CONFIG_FLASH_CFI_DRIVER
	144	#define CONFIG_SYS_FLASH_CFI
	145	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	146	#define CONFIG_SYS_FLASH_QUIET_TEST
	147	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	148
	149	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	150	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	151	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	152	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	153
	154	#define CONFIG_SYS_FLASH_EMPTY_INFO
	155	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	156	#endif
	157
	158	#define CONFIG_NAND_FSL_IFC
	159	#define CONFIG_SYS_NAND_MAX_ECCPOS 256
	160	#define CONFIG_SYS_NAND_MAX_OOBFREE 2
	161	#define CONFIG_SYS_NAND_BASE 0x520000000
	162	#define CONFIG_SYS_NAND_BASE_PHYS 0x20000000
	163
	164	#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
	165	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	166	\| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
	167	\| CSPR_MSEL_NAND /* MSEL = NAND */ \
	168	\| CSPR_V)
	169	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
	170
	171	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	172	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	173	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
	174	\| CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
	175	\| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
	176	\| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
	177	\| CSOR_NAND_PB(64)) /Pages Per Block = 64/
	178
	179	#define CONFIG_SYS_NAND_ONFI_DETECTION
	180
	181	/* ONFI NAND Flash mode0 Timing Params */
	182	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) \| \
	183	FTIM0_NAND_TWP(0x18) \| \
	184	FTIM0_NAND_TWCHT(0x07) \| \
	185	FTIM0_NAND_TWH(0x0a))
	186	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
	187	FTIM1_NAND_TWBE(0x39) \| \
	188	FTIM1_NAND_TRR(0x0e) \| \
	189	FTIM1_NAND_TRP(0x18))
	190	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) \| \
	191	FTIM2_NAND_TREH(0x0a) \| \
	192	FTIM2_NAND_TWHRE(0x1e))
	193	#define CONFIG_SYS_NAND_FTIM3 0x0
	194
	195	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	196	#define CONFIG_SYS_MAX_NAND_DEVICE 1
e211c12e PK	197	#define CONFIG_CMD_NAND
	198
	199	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
	200
f749db3a YS	201	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	202	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
	203	#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
	204	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	205	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	206	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	207	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	208	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	209	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	210
422cb08a BS	211	/* Debug Server firmware */
	212	#define CONFIG_FSL_DEBUG_SERVER
	213	#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
	214	#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
	215	#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL
	216	/* 2 sec timeout */
	217	#define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000)
	218
f749db3a YS	219	/* MC firmware */
	220	#define CONFIG_FSL_MC_ENET
	221	#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
	222	#define CONFIG_SYS_LS_MC_FW_IN_NOR
	223	#define CONFIG_SYS_LS_MC_FW_ADDR 0x580200000ULL
f749db3a YS	224	#define CONFIG_SYS_LS_MC_DPL_IN_NOR
	225	#define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL
	226	/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
7b3bd9a7	227	#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH (256 * 1024)
f749db3a YS	228	#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0xe00000
f749db3a YS	229
422cb08a BS	230	/* Carve out a DDR region which will not be used by u-boot/Linux */
	231	#if defined(CONFIG_FSL_MC_ENET) \|\| defined(CONFIG_FSL_DEBUG_SERVER)
	232	#define CONFIG_SYS_MEM_TOP_HIDE get_dram_size_to_hide()
f749db3a YS	233	#endif
	234
	235	/* Command line configuration */
	236	#define CONFIG_CMD_CACHE
	237	#define CONFIG_CMD_BDI
	238	#define CONFIG_CMD_DHCP
	239	#define CONFIG_CMD_ENV
	240	#define CONFIG_CMD_FLASH
	241	#define CONFIG_CMD_IMI
	242	#define CONFIG_CMD_MEMORY
	243	#define CONFIG_CMD_MII
	244	#define CONFIG_CMD_NET
	245	#define CONFIG_CMD_PING
	246	#define CONFIG_CMD_SAVEENV
	247	#define CONFIG_CMD_RUN
	248	#define CONFIG_CMD_BOOTD
	249	#define CONFIG_CMD_ECHO
	250	#define CONFIG_CMD_SOURCE
	251	#define CONFIG_CMD_FAT
	252	#define CONFIG_DOS_PARTITION
	253
	254	/* Miscellaneous configurable options */
	255	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
8bfa301b	256	#define CONFIG_ARCH_EARLY_INIT_R
f749db3a YS	257
	258	/* Physical Memory Map */
	259	/* fixme: these need to be checked against the board */
	260	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
064d031c YS	261	#define CONFIG_SYS_CLK_FREQ 100000000
064d031c YS	262	#define CONFIG_DDR_CLK_FREQ 133333333
f749db3a	263
d9c68b14	264	#define CONFIG_NR_DRAM_BANKS 3
f749db3a	265
f749db3a YS	266	#define CONFIG_HWCONFIG
	267	#define HWCONFIG_BUFFER_SIZE 128
	268
	269	#define CONFIG_DISPLAY_CPUINFO
	270
	271	/* Initial environment variables */
	272	#define CONFIG_EXTRA_ENV_SETTINGS \
	273	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	274	"loadaddr=0x80100000\0" \
	275	"kernel_addr=0x100000\0" \
	276	"ramdisk_addr=0x800000\0" \
	277	"ramdisk_size=0x2000000\0" \
	278	"fdt_high=0xffffffffffffffff\0" \
	279	"initrd_high=0xffffffffffffffff\0" \
	280	"kernel_start=0x581200000\0" \
052ddd5c	281	"kernel_load=0xa0000000\0" \
f749db3a YS	282	"kernel_size=0x1000000\0" \
	283	"console=ttyAMA0,38400n8\0"
	284
40e61f8e AB	285	#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \
	286	"earlycon=uart8250,mmio,0x21c0600,115200 " \
	287	"default_hugepagesz=2m hugepagesz=2m " \
	288	"hugepages=16"
f749db3a YS	289	#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
	290	"$kernel_size && bootm $kernel_load"
	291	#define CONFIG_BOOTDELAY 1
	292
	293	/* Store environment at top of flash */
	294	#define CONFIG_ENV_IS_NOWHERE 1
	295	#define CONFIG_ENV_SIZE 0x1000
	296
	297	/* Monitor Command Prompt */
	298	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	299	#define CONFIG_SYS_PROMPT "> "
	300	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	301	sizeof(CONFIG_SYS_PROMPT) + 16)
	302	#define CONFIG_SYS_HUSH_PARSER
	303	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	304	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
	305	#define CONFIG_SYS_LONGHELP
	306	#define CONFIG_CMDLINE_EDITING 1
	307	#define CONFIG_SYS_MAXARGS 64 /* max command args */
	308
	309	#ifndef __ASSEMBLY__
422cb08a	310	unsigned long get_dram_size_to_hide(void);
f749db3a YS	311	#endif
	312
	313	#endif /* __LS2_COMMON_H */