[J-u-boot.git] / arch / arm / mach-imx / ddrmc-vf610.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2015 Toradex, Inc.
 *
 * Based on vf610twr:
 * Copyright 2013 Freescale Semiconductor, Inc.
 */

#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux-vf610.h>
#include <asm/arch/ddrmc-vf610.h>
#include <linux/delay.h>
#include "ddrmc-vf610-calibration.h"

void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count)
{
	static const iomux_v3_cfg_t default_pads[] = {
		VF610_PAD_DDR_A15__DDR_A_15,
		VF610_PAD_DDR_A14__DDR_A_14,
		VF610_PAD_DDR_A13__DDR_A_13,
		VF610_PAD_DDR_A12__DDR_A_12,
		VF610_PAD_DDR_A11__DDR_A_11,
		VF610_PAD_DDR_A10__DDR_A_10,
		VF610_PAD_DDR_A9__DDR_A_9,
		VF610_PAD_DDR_A8__DDR_A_8,
		VF610_PAD_DDR_A7__DDR_A_7,
		VF610_PAD_DDR_A6__DDR_A_6,
		VF610_PAD_DDR_A5__DDR_A_5,
		VF610_PAD_DDR_A4__DDR_A_4,
		VF610_PAD_DDR_A3__DDR_A_3,
		VF610_PAD_DDR_A2__DDR_A_2,
		VF610_PAD_DDR_A1__DDR_A_1,
		VF610_PAD_DDR_A0__DDR_A_0,
		VF610_PAD_DDR_BA2__DDR_BA_2,
		VF610_PAD_DDR_BA1__DDR_BA_1,
		VF610_PAD_DDR_BA0__DDR_BA_0,
		VF610_PAD_DDR_CAS__DDR_CAS_B,
		VF610_PAD_DDR_CKE__DDR_CKE_0,
		VF610_PAD_DDR_CLK__DDR_CLK_0,
		VF610_PAD_DDR_CS__DDR_CS_B_0,
		VF610_PAD_DDR_D15__DDR_D_15,
		VF610_PAD_DDR_D14__DDR_D_14,
		VF610_PAD_DDR_D13__DDR_D_13,
		VF610_PAD_DDR_D12__DDR_D_12,
		VF610_PAD_DDR_D11__DDR_D_11,
		VF610_PAD_DDR_D10__DDR_D_10,
		VF610_PAD_DDR_D9__DDR_D_9,
		VF610_PAD_DDR_D8__DDR_D_8,
		VF610_PAD_DDR_D7__DDR_D_7,
		VF610_PAD_DDR_D6__DDR_D_6,
		VF610_PAD_DDR_D5__DDR_D_5,
		VF610_PAD_DDR_D4__DDR_D_4,
		VF610_PAD_DDR_D3__DDR_D_3,
		VF610_PAD_DDR_D2__DDR_D_2,
		VF610_PAD_DDR_D1__DDR_D_1,
		VF610_PAD_DDR_D0__DDR_D_0,
		VF610_PAD_DDR_DQM1__DDR_DQM_1,
		VF610_PAD_DDR_DQM0__DDR_DQM_0,
		VF610_PAD_DDR_DQS1__DDR_DQS_1,
		VF610_PAD_DDR_DQS0__DDR_DQS_0,
		VF610_PAD_DDR_RAS__DDR_RAS_B,
		VF610_PAD_DDR_WE__DDR_WE_B,
		VF610_PAD_DDR_ODT1__DDR_ODT_0,
		VF610_PAD_DDR_ODT0__DDR_ODT_1,
		VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1,
		VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2,
		VF610_PAD_DDR_RESETB,
	};

	if ((pads == NULL) || (pads_count == 0)) {
		pads = default_pads;
		pads_count = ARRAY_SIZE(default_pads);
	}

	imx_iomux_v3_setup_multiple_pads(pads, pads_count);
}

static struct ddrmc_phy_setting default_phy_settings[] = {
	{ DDRMC_PHY_DQ_TIMING,  0 },
	{ DDRMC_PHY_DQ_TIMING, 16 },
	{ DDRMC_PHY_DQ_TIMING, 32 },

	{ DDRMC_PHY_DQS_TIMING,  1 },
	{ DDRMC_PHY_DQS_TIMING, 17 },

	{ DDRMC_PHY_CTRL,  2 },
	{ DDRMC_PHY_CTRL, 18 },
	{ DDRMC_PHY_CTRL, 34 },

	{ DDRMC_PHY_MASTER_CTRL,  3 },
	{ DDRMC_PHY_MASTER_CTRL, 19 },
	{ DDRMC_PHY_MASTER_CTRL, 35 },

	{ DDRMC_PHY_SLAVE_CTRL,  4 },
	{ DDRMC_PHY_SLAVE_CTRL, 20 },
	{ DDRMC_PHY_SLAVE_CTRL, 36 },

	/* LPDDR2 only parameter */
	{ DDRMC_PHY_OFF, 49 },

	{ DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },

	/* Processor Pad ODT settings */
	{ DDRMC_PHY_PROC_PAD_ODT, 52 },

	/* end marker */
	{ 0, -1 }
};

void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
			  struct ddrmc_cr_setting *board_cr_settings,
			  struct ddrmc_phy_setting *board_phy_settings,
			  int col_diff, int row_diff)
{
	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
	struct ddrmc_cr_setting *cr_setting;
	struct ddrmc_phy_setting *phy_setting;

	writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
	writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]);
	writel(DDRMC_CR10_TRST_PWRON(timings->trst_pwron), &ddrmr->cr[10]);

	writel(DDRMC_CR11_CKE_INACTIVE(timings->cke_inactive), &ddrmr->cr[11]);
	writel(DDRMC_CR12_WRLAT(timings->wrlat) |
		   DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]);
	writel(DDRMC_CR13_TRC(timings->trc) | DDRMC_CR13_TRRD(timings->trrd) |
		   DDRMC_CR13_TCCD(timings->tccd) |
		   DDRMC_CR13_TBST_INT_INTERVAL(timings->tbst_int_interval),
		   &ddrmr->cr[13]);
	writel(DDRMC_CR14_TFAW(timings->tfaw) | DDRMC_CR14_TRP(timings->trp) |
		   DDRMC_CR14_TWTR(timings->twtr) |
		   DDRMC_CR14_TRAS_MIN(timings->tras_min), &ddrmr->cr[14]);
	writel(DDRMC_CR16_TMRD(timings->tmrd) |
		   DDRMC_CR16_TRTP(timings->trtp), &ddrmr->cr[16]);
	writel(DDRMC_CR17_TRAS_MAX(timings->tras_max) |
		   DDRMC_CR17_TMOD(timings->tmod), &ddrmr->cr[17]);
	writel(DDRMC_CR18_TCKESR(timings->tckesr) |
		   DDRMC_CR18_TCKE(timings->tcke), &ddrmr->cr[18]);

	writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
	writel(DDRMC_CR21_TRCD_INT(timings->trcd_int) | DDRMC_CR21_CCMAP_EN |
		   DDRMC_CR21_TRAS_LOCKOUT(timings->tras_lockout),
		   &ddrmr->cr[21]);

	writel(DDRMC_CR22_TDAL(timings->tdal), &ddrmr->cr[22]);
	writel(DDRMC_CR23_BSTLEN(timings->bstlen) |
		   DDRMC_CR23_TDLL(timings->tdll), &ddrmr->cr[23]);
	writel(DDRMC_CR24_TRP_AB(timings->trp_ab), &ddrmr->cr[24]);

	writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
	writel(DDRMC_CR26_TREF(timings->tref) |
		   DDRMC_CR26_TRFC(timings->trfc), &ddrmr->cr[26]);
	writel(DDRMC_CR28_TREF_INT(timings->tref_int), &ddrmr->cr[28]);
	writel(DDRMC_CR29_TPDEX(timings->tpdex), &ddrmr->cr[29]);

	writel(DDRMC_CR30_TXPDLL(timings->txpdll), &ddrmr->cr[30]);
	writel(DDRMC_CR31_TXSNR(timings->txsnr) |
		   DDRMC_CR31_TXSR(timings->txsr), &ddrmr->cr[31]);
	writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]);
	writel(DDRMC_CR34_CKSRX(timings->cksrx) |
		   DDRMC_CR34_CKSRE(timings->cksre), &ddrmr->cr[34]);

	writel(DDRMC_CR38_FREQ_CHG_EN(timings->freq_chg_en), &ddrmr->cr[38]);
	writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
		   DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);

	writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]);
	writel(DDRMC_CR48_MR1_DA_0(70) |
		   DDRMC_CR48_MR0_DA_0(1056), &ddrmr->cr[48]);

	writel(DDRMC_CR66_ZQCL(timings->zqcl) |
		   DDRMC_CR66_ZQINIT(timings->zqinit), &ddrmr->cr[66]);
	writel(DDRMC_CR67_ZQCS(timings->zqcs), &ddrmr->cr[67]);
	writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);

	writel(DDRMC_CR70_REF_PER_ZQ(timings->ref_per_zq), &ddrmr->cr[70]);
	writel(DDRMC_CR72_ZQCS_ROTATE(timings->zqcs_rotate), &ddrmr->cr[72]);

	writel(DDRMC_CR73_APREBIT(timings->aprebit) |
		   DDRMC_CR73_COL_DIFF(col_diff) |
		   DDRMC_CR73_ROW_DIFF(row_diff), &ddrmr->cr[73]);
	writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
		   DDRMC_CR74_CMD_AGE_CNT(timings->cmd_age_cnt) |
		   DDRMC_CR74_AGE_CNT(timings->age_cnt),
		   &ddrmr->cr[74]);
	writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
		   DDRMC_CR75_PLEN, &ddrmr->cr[75]);
	writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) |
		   DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]);
	writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
		   DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
	writel(DDRMC_CR78_Q_FULLNESS(timings->q_fullness) |
		   DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);

	writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);

	writel(DDRMC_CR87_ODT_RD_MAPCS0(timings->odt_rd_mapcs0) |
		   DDRMC_CR87_ODT_WR_MAPCS0(timings->odt_wr_mapcs0),
		   &ddrmr->cr[87]);
	writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
	writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);

	writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]);
	writel(DDRMC_CR96_WLMRD(timings->wlmrd) |
		   DDRMC_CR96_WLDQSEN(timings->wldqsen), &ddrmr->cr[96]);

	/* execute custom CR setting sequence (may be NULL) */
	cr_setting = board_cr_settings;
	if (cr_setting != NULL)
		while (cr_setting->cr_rnum >= 0) {
			writel(cr_setting->setting,
			       &ddrmr->cr[cr_setting->cr_rnum]);
			cr_setting++;
		}

	/* perform default PHY settings (may be overridden by custom settings */
	phy_setting = default_phy_settings;
	while (phy_setting->phy_rnum >= 0) {
		writel(phy_setting->setting,
		       &ddrmr->phy[phy_setting->phy_rnum]);
		phy_setting++;
	}

	/* execute custom PHY setting sequence (may be NULL) */
	phy_setting = board_phy_settings;
	if (phy_setting != NULL)
		while (phy_setting->phy_rnum >= 0) {
			writel(phy_setting->setting,
			       &ddrmr->phy[phy_setting->phy_rnum]);
			phy_setting++;
		}

	/* all inits done, start the DDR controller */
	writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);

	while (!(readl(&ddrmr->cr[80]) & DDRMC_CR80_MC_INIT_COMPLETE))
		udelay(10);
	writel(DDRMC_CR80_MC_INIT_COMPLETE, &ddrmr->cr[81]);

#ifdef CONFIG_DDRMC_VF610_CALIBRATION
	ddrmc_calibration(ddrmr);
#endif
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
c7ea243c SM	2	/*
	3	* Copyright 2015 Toradex, Inc.
	4	*
	5	* Based on vf610twr:
	6	* Copyright 2013 Freescale Semiconductor, Inc.
c7ea243c SM	7	*/
	8
	9	#include <asm/io.h>
	10	#include <asm/arch/imx-regs.h>
	11	#include <asm/arch/iomux-vf610.h>
	12	#include <asm/arch/ddrmc-vf610.h>
c05ed00a	13	#include <linux/delay.h>
dc619924	14	#include "ddrmc-vf610-calibration.h"
c7ea243c	15
3f353cec	16	void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count)
c7ea243c	17	{
3f353cec	18	static const iomux_v3_cfg_t default_pads[] = {
c7ea243c SM	19	VF610_PAD_DDR_A15__DDR_A_15,
	20	VF610_PAD_DDR_A14__DDR_A_14,
	21	VF610_PAD_DDR_A13__DDR_A_13,
	22	VF610_PAD_DDR_A12__DDR_A_12,
	23	VF610_PAD_DDR_A11__DDR_A_11,
	24	VF610_PAD_DDR_A10__DDR_A_10,
	25	VF610_PAD_DDR_A9__DDR_A_9,
	26	VF610_PAD_DDR_A8__DDR_A_8,
	27	VF610_PAD_DDR_A7__DDR_A_7,
	28	VF610_PAD_DDR_A6__DDR_A_6,
	29	VF610_PAD_DDR_A5__DDR_A_5,
	30	VF610_PAD_DDR_A4__DDR_A_4,
	31	VF610_PAD_DDR_A3__DDR_A_3,
	32	VF610_PAD_DDR_A2__DDR_A_2,
	33	VF610_PAD_DDR_A1__DDR_A_1,
	34	VF610_PAD_DDR_A0__DDR_A_0,
	35	VF610_PAD_DDR_BA2__DDR_BA_2,
	36	VF610_PAD_DDR_BA1__DDR_BA_1,
	37	VF610_PAD_DDR_BA0__DDR_BA_0,
	38	VF610_PAD_DDR_CAS__DDR_CAS_B,
	39	VF610_PAD_DDR_CKE__DDR_CKE_0,
	40	VF610_PAD_DDR_CLK__DDR_CLK_0,
	41	VF610_PAD_DDR_CS__DDR_CS_B_0,
	42	VF610_PAD_DDR_D15__DDR_D_15,
	43	VF610_PAD_DDR_D14__DDR_D_14,
	44	VF610_PAD_DDR_D13__DDR_D_13,
	45	VF610_PAD_DDR_D12__DDR_D_12,
	46	VF610_PAD_DDR_D11__DDR_D_11,
	47	VF610_PAD_DDR_D10__DDR_D_10,
	48	VF610_PAD_DDR_D9__DDR_D_9,
	49	VF610_PAD_DDR_D8__DDR_D_8,
	50	VF610_PAD_DDR_D7__DDR_D_7,
	51	VF610_PAD_DDR_D6__DDR_D_6,
	52	VF610_PAD_DDR_D5__DDR_D_5,
	53	VF610_PAD_DDR_D4__DDR_D_4,
	54	VF610_PAD_DDR_D3__DDR_D_3,
	55	VF610_PAD_DDR_D2__DDR_D_2,
	56	VF610_PAD_DDR_D1__DDR_D_1,
	57	VF610_PAD_DDR_D0__DDR_D_0,
	58	VF610_PAD_DDR_DQM1__DDR_DQM_1,
	59	VF610_PAD_DDR_DQM0__DDR_DQM_0,
	60	VF610_PAD_DDR_DQS1__DDR_DQS_1,
	61	VF610_PAD_DDR_DQS0__DDR_DQS_0,
	62	VF610_PAD_DDR_RAS__DDR_RAS_B,
	63	VF610_PAD_DDR_WE__DDR_WE_B,
	64	VF610_PAD_DDR_ODT1__DDR_ODT_0,
	65	VF610_PAD_DDR_ODT0__DDR_ODT_1,
a95d4440 SA	66	VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1,
a95d4440 SA	67	VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2,
c7ea243c SM	68	VF610_PAD_DDR_RESETB,
	69	};
	70
3f353cec AA	71	if ((pads == NULL) \|\| (pads_count == 0)) {
	72	pads = default_pads;
	73	pads_count = ARRAY_SIZE(default_pads);
	74	}
c7ea243c	75
3f353cec AA	76	imx_iomux_v3_setup_multiple_pads(pads, pads_count);
3f353cec AA	77	}
c7ea243c	78
3f353cec AA	79	static struct ddrmc_phy_setting default_phy_settings[] = {
	80	{ DDRMC_PHY_DQ_TIMING, 0 },
	81	{ DDRMC_PHY_DQ_TIMING, 16 },
	82	{ DDRMC_PHY_DQ_TIMING, 32 },
c7ea243c	83
3f353cec AA	84	{ DDRMC_PHY_DQS_TIMING, 1 },
3f353cec AA	85	{ DDRMC_PHY_DQS_TIMING, 17 },
c7ea243c	86
3f353cec AA	87	{ DDRMC_PHY_CTRL, 2 },
	88	{ DDRMC_PHY_CTRL, 18 },
	89	{ DDRMC_PHY_CTRL, 34 },
c7ea243c	90
3f353cec AA	91	{ DDRMC_PHY_MASTER_CTRL, 3 },
	92	{ DDRMC_PHY_MASTER_CTRL, 19 },
	93	{ DDRMC_PHY_MASTER_CTRL, 35 },
c7ea243c	94
3f353cec AA	95	{ DDRMC_PHY_SLAVE_CTRL, 4 },
	96	{ DDRMC_PHY_SLAVE_CTRL, 20 },
	97	{ DDRMC_PHY_SLAVE_CTRL, 36 },
c7ea243c SM	98
c7ea243c SM	99	/* LPDDR2 only parameter */
3f353cec	100	{ DDRMC_PHY_OFF, 49 },
c7ea243c	101
3f353cec	102	{ DDRMC_PHY50_DDR3_MODE \| DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
c7ea243c SM	103
c7ea243c SM	104	/* Processor Pad ODT settings */
3f353cec	105	{ DDRMC_PHY_PROC_PAD_ODT, 52 },
c7ea243c	106
3f353cec AA	107	/* end marker */
	108	{ 0, -1 }
	109	};
c7ea243c SM	110
c7ea243c SM	111	void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
3f353cec AA	112	struct ddrmc_cr_setting *board_cr_settings,
	113	struct ddrmc_phy_setting *board_phy_settings,
	114	int col_diff, int row_diff)
c7ea243c SM	115	{
c7ea243c SM	116	struct ddrmr_regs ddrmr = (struct ddrmr_regs )DDR_BASE_ADDR;
3f353cec AA	117	struct ddrmc_cr_setting *cr_setting;
3f353cec AA	118	struct ddrmc_phy_setting *phy_setting;
c7ea243c SM	119
	120	writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
	121	writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]);
	122	writel(DDRMC_CR10_TRST_PWRON(timings->trst_pwron), &ddrmr->cr[10]);
	123
	124	writel(DDRMC_CR11_CKE_INACTIVE(timings->cke_inactive), &ddrmr->cr[11]);
	125	writel(DDRMC_CR12_WRLAT(timings->wrlat) \|
	126	DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]);
	127	writel(DDRMC_CR13_TRC(timings->trc) \| DDRMC_CR13_TRRD(timings->trrd) \|
3f353cec AA	128	DDRMC_CR13_TCCD(timings->tccd) \|
	129	DDRMC_CR13_TBST_INT_INTERVAL(timings->tbst_int_interval),
	130	&ddrmr->cr[13]);
c7ea243c SM	131	writel(DDRMC_CR14_TFAW(timings->tfaw) \| DDRMC_CR14_TRP(timings->trp) \|
	132	DDRMC_CR14_TWTR(timings->twtr) \|
	133	DDRMC_CR14_TRAS_MIN(timings->tras_min), &ddrmr->cr[14]);
	134	writel(DDRMC_CR16_TMRD(timings->tmrd) \|
	135	DDRMC_CR16_TRTP(timings->trtp), &ddrmr->cr[16]);
	136	writel(DDRMC_CR17_TRAS_MAX(timings->tras_max) \|
	137	DDRMC_CR17_TMOD(timings->tmod), &ddrmr->cr[17]);
	138	writel(DDRMC_CR18_TCKESR(timings->tckesr) \|
	139	DDRMC_CR18_TCKE(timings->tcke), &ddrmr->cr[18]);
	140
	141	writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
3f353cec AA	142	writel(DDRMC_CR21_TRCD_INT(timings->trcd_int) \| DDRMC_CR21_CCMAP_EN \|
	143	DDRMC_CR21_TRAS_LOCKOUT(timings->tras_lockout),
	144	&ddrmr->cr[21]);
c7ea243c SM	145
c7ea243c SM	146	writel(DDRMC_CR22_TDAL(timings->tdal), &ddrmr->cr[22]);
3f353cec	147	writel(DDRMC_CR23_BSTLEN(timings->bstlen) \|
c7ea243c SM	148	DDRMC_CR23_TDLL(timings->tdll), &ddrmr->cr[23]);
	149	writel(DDRMC_CR24_TRP_AB(timings->trp_ab), &ddrmr->cr[24]);
	150
	151	writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
	152	writel(DDRMC_CR26_TREF(timings->tref) \|
	153	DDRMC_CR26_TRFC(timings->trfc), &ddrmr->cr[26]);
3f353cec	154	writel(DDRMC_CR28_TREF_INT(timings->tref_int), &ddrmr->cr[28]);
c7ea243c SM	155	writel(DDRMC_CR29_TPDEX(timings->tpdex), &ddrmr->cr[29]);
	156
	157	writel(DDRMC_CR30_TXPDLL(timings->txpdll), &ddrmr->cr[30]);
	158	writel(DDRMC_CR31_TXSNR(timings->txsnr) \|
	159	DDRMC_CR31_TXSR(timings->txsr), &ddrmr->cr[31]);
	160	writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]);
	161	writel(DDRMC_CR34_CKSRX(timings->cksrx) \|
	162	DDRMC_CR34_CKSRE(timings->cksre), &ddrmr->cr[34]);
	163
3f353cec	164	writel(DDRMC_CR38_FREQ_CHG_EN(timings->freq_chg_en), &ddrmr->cr[38]);
c7ea243c SM	165	writel(DDRMC_CR39_PHY_INI_COM(1024) \| DDRMC_CR39_PHY_INI_STA(16) \|
	166	DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
	167
	168	writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]);
	169	writel(DDRMC_CR48_MR1_DA_0(70) \|
	170	DDRMC_CR48_MR0_DA_0(1056), &ddrmr->cr[48]);
	171
	172	writel(DDRMC_CR66_ZQCL(timings->zqcl) \|
	173	DDRMC_CR66_ZQINIT(timings->zqinit), &ddrmr->cr[66]);
	174	writel(DDRMC_CR67_ZQCS(timings->zqcs), &ddrmr->cr[67]);
	175	writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
	176
	177	writel(DDRMC_CR70_REF_PER_ZQ(timings->ref_per_zq), &ddrmr->cr[70]);
3f353cec	178	writel(DDRMC_CR72_ZQCS_ROTATE(timings->zqcs_rotate), &ddrmr->cr[72]);
c7ea243c SM	179
	180	writel(DDRMC_CR73_APREBIT(timings->aprebit) \|
	181	DDRMC_CR73_COL_DIFF(col_diff) \|
	182	DDRMC_CR73_ROW_DIFF(row_diff), &ddrmr->cr[73]);
	183	writel(DDRMC_CR74_BANKSPLT_EN \| DDRMC_CR74_ADDR_CMP_EN \|
3f353cec AA	184	DDRMC_CR74_CMD_AGE_CNT(timings->cmd_age_cnt) \|
3f353cec AA	185	DDRMC_CR74_AGE_CNT(timings->age_cnt),
c7ea243c SM	186	&ddrmr->cr[74]);
	187	writel(DDRMC_CR75_RW_PG_EN \| DDRMC_CR75_RW_EN \| DDRMC_CR75_PRI_EN \|
	188	DDRMC_CR75_PLEN, &ddrmr->cr[75]);
	189	writel(DDRMC_CR76_NQENT_ACTDIS(3) \| DDRMC_CR76_D_RW_G_BKCN(3) \|
	190	DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]);
	191	writel(DDRMC_CR77_CS_MAP \| DDRMC_CR77_DI_RD_INTLEAVE \|
	192	DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
3f353cec	193	writel(DDRMC_CR78_Q_FULLNESS(timings->q_fullness) \|
c7ea243c	194	DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
c7ea243c SM	195
	196	writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
	197
3f353cec AA	198	writel(DDRMC_CR87_ODT_RD_MAPCS0(timings->odt_rd_mapcs0) \|
	199	DDRMC_CR87_ODT_WR_MAPCS0(timings->odt_wr_mapcs0),
	200	&ddrmr->cr[87]);
c7ea243c SM	201	writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
	202	writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
	203
	204	writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]);
	205	writel(DDRMC_CR96_WLMRD(timings->wlmrd) \|
	206	DDRMC_CR96_WLDQSEN(timings->wldqsen), &ddrmr->cr[96]);
	207
3f353cec AA	208	/* execute custom CR setting sequence (may be NULL) */
	209	cr_setting = board_cr_settings;
	210	if (cr_setting != NULL)
	211	while (cr_setting->cr_rnum >= 0) {
	212	writel(cr_setting->setting,
	213	&ddrmr->cr[cr_setting->cr_rnum]);
	214	cr_setting++;
	215	}
	216
62a3b7dd	217	/* perform default PHY settings (may be overridden by custom settings */
3f353cec AA	218	phy_setting = default_phy_settings;
	219	while (phy_setting->phy_rnum >= 0) {
	220	writel(phy_setting->setting,
	221	&ddrmr->phy[phy_setting->phy_rnum]);
	222	phy_setting++;
	223	}
	224
	225	/* execute custom PHY setting sequence (may be NULL) */
	226	phy_setting = board_phy_settings;
	227	if (phy_setting != NULL)
	228	while (phy_setting->phy_rnum >= 0) {
	229	writel(phy_setting->setting,
	230	&ddrmr->phy[phy_setting->phy_rnum]);
	231	phy_setting++;
	232	}
c7ea243c	233
3f353cec	234	/* all inits done, start the DDR controller */
c7ea243c SM	235	writel(DDRMC_CR00_DRAM_CLASS_DDR3 \| DDRMC_CR00_START, &ddrmr->cr[0]);
c7ea243c SM	236
52c2c97e	237	while (!(readl(&ddrmr->cr[80]) & DDRMC_CR80_MC_INIT_COMPLETE))
c7ea243c	238	udelay(10);
52c2c97e	239	writel(DDRMC_CR80_MC_INIT_COMPLETE, &ddrmr->cr[81]);
dc619924 LM	240
	241	#ifdef CONFIG_DDRMC_VF610_CALIBRATION
	242	ddrmc_calibration(ddrmr);
	243	#endif
c7ea243c	244	}